[deliverable/linux.git] / arch / arm / boot / dts / imx28.dtsi

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&icoll>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		saif0 = &saif0;
		saif1 = &saif1;
		serial0 = &auart0;
		serial1 = &auart1;
		serial2 = &auart2;
		serial3 = &auart3;
		serial4 = &auart4;
	};

	cpus {
		cpu@0 {
			compatible = "arm,arm926ejs";
		};
	};

	apb@80000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x80000000 0x80000>;
		ranges;

		apbh@80000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80000000 0x3c900>;
			ranges;

			icoll: interrupt-controller@80000000 {
				compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x80000000 0x2000>;
			};

			hsadc@80002000 {
				reg = <0x80002000 2000>;
				interrupts = <13 87>;
				status = "disabled";
			};

			dma-apbh@80004000 {
				compatible = "fsl,imx28-dma-apbh";
				reg = <0x80004000 2000>;
			};

			perfmon@80006000 {
				reg = <0x80006000 800>;
				interrupts = <27>;
				status = "disabled";
			};

			gpmi-nand@8000c000 {
				compatible = "fsl,imx28-gpmi-nand";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x8000c000 2000>, <0x8000a000 2000>;
				reg-names = "gpmi-nand", "bch";
				interrupts = <88>, <41>;
				interrupt-names = "gpmi-dma", "bch";
				fsl,gpmi-dma-channel = <4>;
				status = "disabled";
			};

			ssp0: ssp@80010000 {
				reg = <0x80010000 2000>;
				interrupts = <96 82>;
				fsl,ssp-dma-channel = <0>;
				status = "disabled";
			};

			ssp1: ssp@80012000 {
				reg = <0x80012000 2000>;
				interrupts = <97 83>;
				fsl,ssp-dma-channel = <1>;
				status = "disabled";
			};

			ssp2: ssp@80014000 {
				reg = <0x80014000 2000>;
				interrupts = <98 84>;
				fsl,ssp-dma-channel = <2>;
				status = "disabled";
			};

			ssp3: ssp@80016000 {
				reg = <0x80016000 2000>;
				interrupts = <99 85>;
				fsl,ssp-dma-channel = <3>;
				status = "disabled";
			};

			pinctrl@80018000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx28-pinctrl", "simple-bus";
				reg = <0x80018000 2000>;

				gpio0: gpio@0 {
					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
					interrupts = <127>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio1: gpio@1 {
					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
					interrupts = <126>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@2 {
					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
					interrupts = <125>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio3: gpio@3 {
					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
					interrupts = <124>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio4: gpio@4 {
					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
					interrupts = <123>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				duart_pins_a: duart@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x3102 /* MX28_PAD_PWM0__DUART_RX */
						0x3112 /* MX28_PAD_PWM1__DUART_TX */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				duart_pins_b: duart@1 {
					reg = <1>;
					fsl,pinmux-ids = <
						0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
						0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				gpmi_pins_a: gpmi-nand@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
						0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
						0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
						0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
						0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
						0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
						0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
						0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
						0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
						0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */
						0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
						0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */
						0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
						0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
						0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
						0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
						0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				gpmi_status_cfg: gpmi-status-cfg {
					fsl,pinmux-ids = <
						0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
						0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
						0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
					>;
					fsl,drive-strength = <2>;
				};

				auart0_pins_a: auart0@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
						0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
						0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
						0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				auart3_pins_a: auart3@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
						0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
						0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
						0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				mac0_pins_a: mac0@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
						0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
						0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
						0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
						0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
						0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
						0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
						0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
						0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
					>;
					fsl,drive-strength = <1>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				mac1_pins_a: mac1@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
						0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
						0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
						0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
						0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
						0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
					>;
					fsl,drive-strength = <1>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				mmc0_8bit_pins_a: mmc0-8bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
						0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
						0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
						0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
						0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
						0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
						0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
						0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
						0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
						0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
						0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
					>;
					fsl,drive-strength = <1>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				mmc0_4bit_pins_a: mmc0-4bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
						0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
						0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
						0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
						0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
						0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
						0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
					>;
					fsl,drive-strength = <1>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				mmc0_cd_cfg: mmc0-cd-cfg {
					fsl,pinmux-ids = <
						0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
					>;
					fsl,pull-up = <0>;
				};

				mmc0_sck_cfg: mmc0-sck-cfg {
					fsl,pinmux-ids = <
						0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
					>;
					fsl,drive-strength = <2>;
					fsl,pull-up = <0>;
				};

				i2c0_pins_a: i2c0@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
						0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
					>;
					fsl,drive-strength = <1>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				saif0_pins_a: saif0@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
						0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
						0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
						0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
					>;
					fsl,drive-strength = <2>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				saif1_pins_a: saif1@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
					>;
					fsl,drive-strength = <2>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};

				pwm2_pins_a: pwm2@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x3120 /* MX28_PAD_PWM2__PWM_2 */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				lcdif_24bit_pins_a: lcdif-24bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
						0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
						0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
						0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
						0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
						0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
						0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
						0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
						0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
						0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
						0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
						0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
						0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
						0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
						0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
						0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
						0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
						0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
						0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
						0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
						0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
						0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
						0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
						0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
						0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
						0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
						0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
						0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};
			};

			digctl@8001c000 {
				reg = <0x8001c000 2000>;
				interrupts = <89>;
				status = "disabled";
			};

			etm@80022000 {
				reg = <0x80022000 2000>;
				status = "disabled";
			};

			dma-apbx@80024000 {
				compatible = "fsl,imx28-dma-apbx";
				reg = <0x80024000 2000>;
			};

			dcp@80028000 {
				reg = <0x80028000 2000>;
				interrupts = <52 53 54>;
				status = "disabled";
			};

			pxp@8002a000 {
				reg = <0x8002a000 2000>;
				interrupts = <39>;
				status = "disabled";
			};

			ocotp@8002c000 {
				reg = <0x8002c000 2000>;
				status = "disabled";
			};

			axi-ahb@8002e000 {
				reg = <0x8002e000 2000>;
				status = "disabled";
			};

			lcdif@80030000 {
				compatible = "fsl,imx28-lcdif";
				reg = <0x80030000 2000>;
				interrupts = <38 86>;
				status = "disabled";
			};

			can0: can@80032000 {
				reg = <0x80032000 2000>;
				interrupts = <8>;
				status = "disabled";
			};

			can1: can@80034000 {
				reg = <0x80034000 2000>;
				interrupts = <9>;
				status = "disabled";
			};

			simdbg@8003c000 {
				reg = <0x8003c000 200>;
				status = "disabled";
			};

			simgpmisel@8003c200 {
				reg = <0x8003c200 100>;
				status = "disabled";
			};

			simsspsel@8003c300 {
				reg = <0x8003c300 100>;
				status = "disabled";
			};

			simmemsel@8003c400 {
				reg = <0x8003c400 100>;
				status = "disabled";
			};

			gpiomon@8003c500 {
				reg = <0x8003c500 100>;
				status = "disabled";
			};

			simenet@8003c700 {
				reg = <0x8003c700 100>;
				status = "disabled";
			};

			armjtag@8003c800 {
				reg = <0x8003c800 100>;
				status = "disabled";
			};
                };

		apbx@80040000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80040000 0x40000>;
			ranges;

			clkctl@80040000 {
				reg = <0x80040000 2000>;
				status = "disabled";
			};

			saif0: saif@80042000 {
				compatible = "fsl,imx28-saif";
				reg = <0x80042000 2000>;
				interrupts = <59 80>;
				fsl,saif-dma-channel = <4>;
				status = "disabled";
			};

			power@80044000 {
				reg = <0x80044000 2000>;
				status = "disabled";
			};

			saif1: saif@80046000 {
				compatible = "fsl,imx28-saif";
				reg = <0x80046000 2000>;
				interrupts = <58 81>;
				fsl,saif-dma-channel = <5>;
				status = "disabled";
			};

			lradc@80050000 {
				reg = <0x80050000 2000>;
				status = "disabled";
			};

			spdif@80054000 {
				reg = <0x80054000 2000>;
				interrupts = <45 66>;
				status = "disabled";
			};

			rtc@80056000 {
				compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
				reg = <0x80056000 2000>;
				interrupts = <29>;
			};

			i2c0: i2c@80058000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx28-i2c";
				reg = <0x80058000 2000>;
				interrupts = <111 68>;
				status = "disabled";
			};

			i2c1: i2c@8005a000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx28-i2c";
				reg = <0x8005a000 2000>;
				interrupts = <110 69>;
				status = "disabled";
			};

			pwm: pwm@80064000 {
				compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
				reg = <0x80064000 2000>;
				#pwm-cells = <2>;
				fsl,pwm-number = <8>;
				status = "disabled";
			};

			timrot@80068000 {
				reg = <0x80068000 2000>;
				status = "disabled";
			};

			auart0: serial@8006a000 {
				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
				reg = <0x8006a000 0x2000>;
				interrupts = <112 70 71>;
				status = "disabled";
			};

			auart1: serial@8006c000 {
				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
				reg = <0x8006c000 0x2000>;
				interrupts = <113 72 73>;
				status = "disabled";
			};

			auart2: serial@8006e000 {
				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
				reg = <0x8006e000 0x2000>;
				interrupts = <114 74 75>;
				status = "disabled";
			};

			auart3: serial@80070000 {
				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
				reg = <0x80070000 0x2000>;
				interrupts = <115 76 77>;
				status = "disabled";
			};

			auart4: serial@80072000 {
				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
				reg = <0x80072000 0x2000>;
				interrupts = <116 78 79>;
				status = "disabled";
			};

			duart: serial@80074000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x80074000 0x1000>;
				interrupts = <47>;
				status = "disabled";
			};

			usbphy0: usbphy@8007c000 {
				reg = <0x8007c000 0x2000>;
				status = "disabled";
			};

			usbphy1: usbphy@8007e000 {
				reg = <0x8007e000 0x2000>;
				status = "disabled";
			};
		};
	};

	ahb@80080000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x80080000 0x80000>;
		ranges;

		usbctrl0: usbctrl@80080000 {
			reg = <0x80080000 0x10000>;
			status = "disabled";
		};

		usbctrl1: usbctrl@80090000 {
			reg = <0x80090000 0x10000>;
			status = "disabled";
		};

		dflpt@800c0000 {
			reg = <0x800c0000 0x10000>;
			status = "disabled";
		};

		mac0: ethernet@800f0000 {
			compatible = "fsl,imx28-fec";
			reg = <0x800f0000 0x4000>;
			interrupts = <101>;
			status = "disabled";
		};

		mac1: ethernet@800f4000 {
			compatible = "fsl,imx28-fec";
			reg = <0x800f4000 0x4000>;
			interrupts = <102>;
			status = "disabled";
		};

		switch@800f8000 {
			reg = <0x800f8000 0x8000>;
			status = "disabled";
		};

	};
};
Commit	Line	Data
bc3a59c1 DA	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
	14	/ {
	15	interrupt-parent = <&icoll>;
	16
ce4c6f9b SG	17	aliases {
	18	gpio0 = &gpio0;
	19	gpio1 = &gpio1;
	20	gpio2 = &gpio2;
	21	gpio3 = &gpio3;
	22	gpio4 = &gpio4;
530f1d41 SG	23	saif0 = &saif0;
530f1d41 SG	24	saif1 = &saif1;
80d969e4 FE	25	serial0 = &auart0;
	26	serial1 = &auart1;
	27	serial2 = &auart2;
	28	serial3 = &auart3;
	29	serial4 = &auart4;
ce4c6f9b SG	30	};
ce4c6f9b SG	31
bc3a59c1 DA	32	cpus {
	33	cpu@0 {
	34	compatible = "arm,arm926ejs";
	35	};
	36	};
	37
	38	apb@80000000 {
	39	compatible = "simple-bus";
	40	#address-cells = <1>;
	41	#size-cells = <1>;
	42	reg = <0x80000000 0x80000>;
	43	ranges;
	44
	45	apbh@80000000 {
	46	compatible = "simple-bus";
	47	#address-cells = <1>;
	48	#size-cells = <1>;
	49	reg = <0x80000000 0x3c900>;
	50	ranges;
	51
	52	icoll: interrupt-controller@80000000 {
	53	compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
	54	interrupt-controller;
	55	#interrupt-cells = <1>;
	56	reg = <0x80000000 0x2000>;
	57	};
	58
	59	hsadc@80002000 {
	60	reg = <0x80002000 2000>;
	61	interrupts = <13 87>;
	62	status = "disabled";
	63	};
	64
	65	dma-apbh@80004000 {
84f3570a	66	compatible = "fsl,imx28-dma-apbh";
bc3a59c1	67	reg = <0x80004000 2000>;
bc3a59c1 DA	68	};
	69
	70	perfmon@80006000 {
	71	reg = <0x80006000 800>;
	72	interrupts = <27>;
	73	status = "disabled";
	74	};
	75
7a8e5149 HS	76	gpmi-nand@8000c000 {
	77	compatible = "fsl,imx28-gpmi-nand";
	78	#address-cells = <1>;
	79	#size-cells = <1>;
	80	reg = <0x8000c000 2000>, <0x8000a000 2000>;
	81	reg-names = "gpmi-nand", "bch";
	82	interrupts = <88>, <41>;
	83	interrupt-names = "gpmi-dma", "bch";
	84	fsl,gpmi-dma-channel = <4>;
bc3a59c1 DA	85	status = "disabled";
	86	};
	87
	88	ssp0: ssp@80010000 {
	89	reg = <0x80010000 2000>;
	90	interrupts = <96 82>;
35d23047	91	fsl,ssp-dma-channel = <0>;
bc3a59c1 DA	92	status = "disabled";
	93	};
	94
	95	ssp1: ssp@80012000 {
	96	reg = <0x80012000 2000>;
	97	interrupts = <97 83>;
35d23047	98	fsl,ssp-dma-channel = <1>;
bc3a59c1 DA	99	status = "disabled";
	100	};
	101
	102	ssp2: ssp@80014000 {
	103	reg = <0x80014000 2000>;
	104	interrupts = <98 84>;
35d23047	105	fsl,ssp-dma-channel = <2>;
bc3a59c1 DA	106	status = "disabled";
	107	};
	108
	109	ssp3: ssp@80016000 {
	110	reg = <0x80016000 2000>;
	111	interrupts = <99 85>;
35d23047	112	fsl,ssp-dma-channel = <3>;
bc3a59c1 DA	113	status = "disabled";
	114	};
	115
	116	pinctrl@80018000 {
	117	#address-cells = <1>;
	118	#size-cells = <0>;
ce4c6f9b	119	compatible = "fsl,imx28-pinctrl", "simple-bus";
bc3a59c1 DA	120	reg = <0x80018000 2000>;
bc3a59c1 DA	121
ce4c6f9b SG	122	gpio0: gpio@0 {
	123	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	124	interrupts = <127>;
	125	gpio-controller;
	126	#gpio-cells = <2>;
	127	interrupt-controller;
	128	#interrupt-cells = <2>;
	129	};
	130
	131	gpio1: gpio@1 {
	132	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	133	interrupts = <126>;
	134	gpio-controller;
	135	#gpio-cells = <2>;
	136	interrupt-controller;
	137	#interrupt-cells = <2>;
	138	};
	139
	140	gpio2: gpio@2 {
	141	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	142	interrupts = <125>;
	143	gpio-controller;
	144	#gpio-cells = <2>;
	145	interrupt-controller;
	146	#interrupt-cells = <2>;
	147	};
	148
	149	gpio3: gpio@3 {
	150	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	151	interrupts = <124>;
	152	gpio-controller;
	153	#gpio-cells = <2>;
	154	interrupt-controller;
	155	#interrupt-cells = <2>;
	156	};
	157
	158	gpio4: gpio@4 {
	159	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	160	interrupts = <123>;
	161	gpio-controller;
	162	#gpio-cells = <2>;
	163	interrupt-controller;
	164	#interrupt-cells = <2>;
	165	};
	166
bc3a59c1 DA	167	duart_pins_a: duart@0 {
bc3a59c1 DA	168	reg = <0>;
f14da767 SG	169	fsl,pinmux-ids = <
	170	0x3102 /* MX28_PAD_PWM0__DUART_RX */
	171	0x3112 /* MX28_PAD_PWM1__DUART_TX */
	172	>;
bc3a59c1 DA	173	fsl,drive-strength = <0>;
	174	fsl,voltage = <1>;
	175	fsl,pull-up = <0>;
	176	};
	177
8385e7c1 MR	178	duart_pins_b: duart@1 {
8385e7c1 MR	179	reg = <1>;
f14da767 SG	180	fsl,pinmux-ids = <
	181	0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
	182	0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
	183	>;
8385e7c1 MR	184	fsl,drive-strength = <0>;
	185	fsl,voltage = <1>;
	186	fsl,pull-up = <0>;
	187	};
	188
7a8e5149 HS	189	gpmi_pins_a: gpmi-nand@0 {
7a8e5149 HS	190	reg = <0>;
f14da767 SG	191	fsl,pinmux-ids = <
	192	0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
	193	0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
	194	0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
	195	0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
	196	0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
	197	0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
	198	0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
	199	0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
	200	0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
	201	0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */
	202	0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
	203	0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */
	204	0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
	205	0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
	206	0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
	207	0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
	208	0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
	209	>;
7a8e5149 HS	210	fsl,drive-strength = <0>;
	211	fsl,voltage = <1>;
	212	fsl,pull-up = <0>;
	213	};
	214
	215	gpmi_status_cfg: gpmi-status-cfg {
f14da767 SG	216	fsl,pinmux-ids = <
	217	0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
	218	0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
	219	0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
	220	>;
7a8e5149 HS	221	fsl,drive-strength = <2>;
	222	};
	223
80d969e4 FE	224	auart0_pins_a: auart0@0 {
80d969e4 FE	225	reg = <0>;
f14da767 SG	226	fsl,pinmux-ids = <
	227	0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
	228	0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
	229	0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
	230	0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
	231	>;
80d969e4 FE	232	fsl,drive-strength = <0>;
	233	fsl,voltage = <1>;
	234	fsl,pull-up = <0>;
	235	};
	236
	237	auart3_pins_a: auart3@0 {
	238	reg = <0>;
f14da767 SG	239	fsl,pinmux-ids = <
	240	0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
	241	0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
	242	0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
	243	0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
	244	>;
80d969e4 FE	245	fsl,drive-strength = <0>;
	246	fsl,voltage = <1>;
	247	fsl,pull-up = <0>;
	248	};
	249
bc3a59c1 DA	250	mac0_pins_a: mac0@0 {
bc3a59c1 DA	251	reg = <0>;
f14da767 SG	252	fsl,pinmux-ids = <
	253	0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
	254	0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
	255	0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
	256	0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
	257	0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
	258	0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
	259	0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
	260	0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
	261	0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
	262	>;
bc3a59c1 DA	263	fsl,drive-strength = <1>;
	264	fsl,voltage = <1>;
	265	fsl,pull-up = <1>;
	266	};
	267
	268	mac1_pins_a: mac1@0 {
	269	reg = <0>;
f14da767 SG	270	fsl,pinmux-ids = <
	271	0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
	272	0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
	273	0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
	274	0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
	275	0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
	276	0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
	277	>;
bc3a59c1 DA	278	fsl,drive-strength = <1>;
	279	fsl,voltage = <1>;
	280	fsl,pull-up = <1>;
	281	};
35d23047 SG	282
	283	mmc0_8bit_pins_a: mmc0-8bit@0 {
	284	reg = <0>;
f14da767 SG	285	fsl,pinmux-ids = <
	286	0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
	287	0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
	288	0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
	289	0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
	290	0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
	291	0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
	292	0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
	293	0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
	294	0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
	295	0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
	296	0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
	297	>;
35d23047 SG	298	fsl,drive-strength = <1>;
	299	fsl,voltage = <1>;
	300	fsl,pull-up = <1>;
	301	};
	302
8385e7c1 MR	303	mmc0_4bit_pins_a: mmc0-4bit@0 {
8385e7c1 MR	304	reg = <0>;
f14da767 SG	305	fsl,pinmux-ids = <
	306	0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
	307	0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
	308	0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
	309	0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
	310	0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
	311	0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
	312	0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
	313	>;
8385e7c1 MR	314	fsl,drive-strength = <1>;
	315	fsl,voltage = <1>;
	316	fsl,pull-up = <1>;
	317	};
	318
35d23047	319	mmc0_cd_cfg: mmc0-cd-cfg {
f14da767 SG	320	fsl,pinmux-ids = <
	321	0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
	322	>;
35d23047 SG	323	fsl,pull-up = <0>;
	324	};
	325
	326	mmc0_sck_cfg: mmc0-sck-cfg {
f14da767 SG	327	fsl,pinmux-ids = <
	328	0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
	329	>;
35d23047 SG	330	fsl,drive-strength = <2>;
	331	fsl,pull-up = <0>;
	332	};
2a96e391 SG	333
	334	i2c0_pins_a: i2c0@0 {
	335	reg = <0>;
f14da767 SG	336	fsl,pinmux-ids = <
	337	0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
	338	0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
	339	>;
2a96e391 SG	340	fsl,drive-strength = <1>;
	341	fsl,voltage = <1>;
	342	fsl,pull-up = <1>;
	343	};
530f1d41 SG	344
	345	saif0_pins_a: saif0@0 {
	346	reg = <0>;
f14da767 SG	347	fsl,pinmux-ids = <
	348	0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
	349	0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
	350	0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
	351	0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
	352	>;
530f1d41 SG	353	fsl,drive-strength = <2>;
	354	fsl,voltage = <1>;
	355	fsl,pull-up = <1>;
	356	};
	357
	358	saif1_pins_a: saif1@0 {
	359	reg = <0>;
f14da767 SG	360	fsl,pinmux-ids = <
	361	0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
	362	>;
530f1d41 SG	363	fsl,drive-strength = <2>;
	364	fsl,voltage = <1>;
	365	fsl,pull-up = <1>;
	366	};
52f7176b SG	367
	368	pwm2_pins_a: pwm2@0 {
	369	reg = <0>;
	370	fsl,pinmux-ids = <
	371	0x3120 /* MX28_PAD_PWM2__PWM_2 */
	372	>;
	373	fsl,drive-strength = <0>;
	374	fsl,voltage = <1>;
	375	fsl,pull-up = <0>;
	376	};
a915ee42 SG	377
	378	lcdif_24bit_pins_a: lcdif-24bit@0 {
	379	reg = <0>;
	380	fsl,pinmux-ids = <
	381	0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
	382	0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
	383	0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
	384	0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
	385	0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
	386	0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
	387	0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
	388	0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
	389	0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
	390	0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
	391	0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
	392	0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
	393	0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
	394	0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
	395	0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
	396	0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
	397	0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
	398	0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
	399	0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
	400	0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
	401	0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
	402	0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
	403	0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
	404	0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
	405	0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
	406	0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
	407	0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
	408	0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
	409	>;
	410	fsl,drive-strength = <0>;
	411	fsl,voltage = <1>;
	412	fsl,pull-up = <0>;
	413	};
bc3a59c1 DA	414	};
	415
	416	digctl@8001c000 {
	417	reg = <0x8001c000 2000>;
	418	interrupts = <89>;
	419	status = "disabled";
	420	};
	421
	422	etm@80022000 {
	423	reg = <0x80022000 2000>;
	424	status = "disabled";
	425	};
	426
	427	dma-apbx@80024000 {
84f3570a	428	compatible = "fsl,imx28-dma-apbx";
bc3a59c1	429	reg = <0x80024000 2000>;
bc3a59c1 DA	430	};
	431
	432	dcp@80028000 {
	433	reg = <0x80028000 2000>;
	434	interrupts = <52 53 54>;
	435	status = "disabled";
	436	};
	437
	438	pxp@8002a000 {
	439	reg = <0x8002a000 2000>;
	440	interrupts = <39>;
	441	status = "disabled";
	442	};
	443
	444	ocotp@8002c000 {
	445	reg = <0x8002c000 2000>;
	446	status = "disabled";
	447	};
	448
	449	axi-ahb@8002e000 {
	450	reg = <0x8002e000 2000>;
	451	status = "disabled";
	452	};
	453
	454	lcdif@80030000 {
a915ee42	455	compatible = "fsl,imx28-lcdif";
bc3a59c1 DA	456	reg = <0x80030000 2000>;
	457	interrupts = <38 86>;
	458	status = "disabled";
	459	};
	460
	461	can0: can@80032000 {
	462	reg = <0x80032000 2000>;
	463	interrupts = <8>;
	464	status = "disabled";
	465	};
	466
	467	can1: can@80034000 {
	468	reg = <0x80034000 2000>;
	469	interrupts = <9>;
	470	status = "disabled";
	471	};
	472
	473	simdbg@8003c000 {
	474	reg = <0x8003c000 200>;
	475	status = "disabled";
	476	};
	477
	478	simgpmisel@8003c200 {
	479	reg = <0x8003c200 100>;
	480	status = "disabled";
	481	};
	482
	483	simsspsel@8003c300 {
	484	reg = <0x8003c300 100>;
	485	status = "disabled";
	486	};
	487
	488	simmemsel@8003c400 {
	489	reg = <0x8003c400 100>;
	490	status = "disabled";
	491	};
	492
	493	gpiomon@8003c500 {
	494	reg = <0x8003c500 100>;
	495	status = "disabled";
	496	};
	497
	498	simenet@8003c700 {
	499	reg = <0x8003c700 100>;
	500	status = "disabled";
	501	};
	502
	503	armjtag@8003c800 {
	504	reg = <0x8003c800 100>;
	505	status = "disabled";
	506	};
	507	};
	508
	509	apbx@80040000 {
	510	compatible = "simple-bus";
	511	#address-cells = <1>;
	512	#size-cells = <1>;
	513	reg = <0x80040000 0x40000>;
	514	ranges;
	515
	516	clkctl@80040000 {
	517	reg = <0x80040000 2000>;
	518	status = "disabled";
	519	};
520
521	saif0: saif@80042000 {
530f1d41	522	compatible = "fsl,imx28-saif";
bc3a59c1 DA	523	reg = <0x80042000 2000>;
bc3a59c1 DA	524	interrupts = <59 80>;
530f1d41	525	fsl,saif-dma-channel = <4>;
bc3a59c1 DA	526	status = "disabled";
	527	};
	528
	529	power@80044000 {
	530	reg = <0x80044000 2000>;
	531	status = "disabled";
	532	};
	533
	534	saif1: saif@80046000 {
530f1d41	535	compatible = "fsl,imx28-saif";
bc3a59c1 DA	536	reg = <0x80046000 2000>;
bc3a59c1 DA	537	interrupts = <58 81>;
530f1d41	538	fsl,saif-dma-channel = <5>;
bc3a59c1 DA	539	status = "disabled";
	540	};
	541
	542	lradc@80050000 {
	543	reg = <0x80050000 2000>;
	544	status = "disabled";
	545	};
	546
	547	spdif@80054000 {
	548	reg = <0x80054000 2000>;
	549	interrupts = <45 66>;
	550	status = "disabled";
	551	};
	552
	553	rtc@80056000 {
f98c990c	554	compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
bc3a59c1	555	reg = <0x80056000 2000>;
f98c990c	556	interrupts = <29>;
bc3a59c1 DA	557	};
	558
	559	i2c0: i2c@80058000 {
2a96e391 SG	560	#address-cells = <1>;
	561	#size-cells = <0>;
	562	compatible = "fsl,imx28-i2c";
bc3a59c1 DA	563	reg = <0x80058000 2000>;
	564	interrupts = <111 68>;
	565	status = "disabled";
	566	};
	567
	568	i2c1: i2c@8005a000 {
2a96e391 SG	569	#address-cells = <1>;
	570	#size-cells = <0>;
	571	compatible = "fsl,imx28-i2c";
bc3a59c1 DA	572	reg = <0x8005a000 2000>;
	573	interrupts = <110 69>;
	574	status = "disabled";
	575	};
	576
52f7176b SG	577	pwm: pwm@80064000 {
52f7176b SG	578	compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
bc3a59c1	579	reg = <0x80064000 2000>;
52f7176b SG	580	#pwm-cells = <2>;
52f7176b SG	581	fsl,pwm-number = <8>;
bc3a59c1 DA	582	status = "disabled";
	583	};
	584
	585	timrot@80068000 {
	586	reg = <0x80068000 2000>;
	587	status = "disabled";
	588	};
	589
	590	auart0: serial@8006a000 {
80d969e4	591	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 DA	592	reg = <0x8006a000 0x2000>;
	593	interrupts = <112 70 71>;
	594	status = "disabled";
	595	};
	596
	597	auart1: serial@8006c000 {
80d969e4	598	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 DA	599	reg = <0x8006c000 0x2000>;
	600	interrupts = <113 72 73>;
	601	status = "disabled";
	602	};
	603
	604	auart2: serial@8006e000 {
80d969e4	605	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 DA	606	reg = <0x8006e000 0x2000>;
	607	interrupts = <114 74 75>;
	608	status = "disabled";
	609	};
	610
	611	auart3: serial@80070000 {
80d969e4	612	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 DA	613	reg = <0x80070000 0x2000>;
	614	interrupts = <115 76 77>;
	615	status = "disabled";
	616	};
	617
	618	auart4: serial@80072000 {
80d969e4	619	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 DA	620	reg = <0x80072000 0x2000>;
	621	interrupts = <116 78 79>;
	622	status = "disabled";
	623	};
	624
	625	duart: serial@80074000 {
	626	compatible = "arm,pl011", "arm,primecell";
	627	reg = <0x80074000 0x1000>;
	628	interrupts = <47>;
	629	status = "disabled";
	630	};
	631
	632	usbphy0: usbphy@8007c000 {
	633	reg = <0x8007c000 0x2000>;
	634	status = "disabled";
	635	};
	636
	637	usbphy1: usbphy@8007e000 {
	638	reg = <0x8007e000 0x2000>;
	639	status = "disabled";
	640	};
	641	};
	642	};
	643
	644	ahb@80080000 {
	645	compatible = "simple-bus";
	646	#address-cells = <1>;
	647	#size-cells = <1>;
	648	reg = <0x80080000 0x80000>;
	649	ranges;
	650
	651	usbctrl0: usbctrl@80080000 {
	652	reg = <0x80080000 0x10000>;
	653	status = "disabled";
	654	};
	655
	656	usbctrl1: usbctrl@80090000 {
	657	reg = <0x80090000 0x10000>;
	658	status = "disabled";
	659	};
	660
	661	dflpt@800c0000 {
	662	reg = <0x800c0000 0x10000>;
	663	status = "disabled";
	664	};
	665
	666	mac0: ethernet@800f0000 {
	667	compatible = "fsl,imx28-fec";
	668	reg = <0x800f0000 0x4000>;
	669	interrupts = <101>;
	670	status = "disabled";
	671	};
	672
	673	mac1: ethernet@800f4000 {
	674	compatible = "fsl,imx28-fec";
	675	reg = <0x800f4000 0x4000>;
	676	interrupts = <102>;
	677	status = "disabled";
	678	};
	679
	680	switch@800f8000 {
	681	reg = <0x800f8000 0x8000>;
	682	status = "disabled";
	683	};
684
685	};
686	};