[deliverable/linux.git] / arch / arm / boot / dts / imx50.dtsi

/*
 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
					         <&clks IMX5_CLK_UART3_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx50-ssi",
							"fsl,imx51-ssi",
							"fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks IMX5_CLK_DUMMY>;
			};

			gpt: timer@53fa0000 {
				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
				reg = <0x53fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
				         <&clks IMX5_CLK_GPT_HF_GATE>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;
			};

			gpr: iomuxc-gpr@53fa8000 {
				compatible = "fsl,imx50-iomuxc-gpr", "syscon";
				reg = <0x53fa8000 0xc>;
			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
				         <&clks IMX5_CLK_PWM1_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
				         <&clks IMX5_CLK_PWM2_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
				         <&clks IMX5_CLK_UART1_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
				         <&clks IMX5_CLK_UART2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@53fd0000 {
				compatible = "fsl,imx50-src", "fsl,imx51-src";
				reg = <0x53fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx50-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks IMX5_CLK_I2C3_GATE>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
				         <&clks IMX5_CLK_UART4_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
				         <&clks IMX5_CLK_UART5_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks IMX5_CLK_SDMA_GATE>,
				         <&clks IMX5_CLK_SDMA_GATE>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks IMX5_CLK_I2C2_GATE>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks IMX5_CLK_I2C1_GATE>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
							"fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
64972acd GU	1	/*
	2	* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
	3	* Copyright 2011 Freescale Semiconductor, Inc.
	4	* Copyright 2011 Linaro Ltd.
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	#include "skeleton.dtsi"
	15	#include "imx50-pinfunc.h"
6650d6db	16	#include <dt-bindings/clock/imx5-clock.h>
64972acd GU	17
	18	/ {
	19	aliases {
	20	gpio0 = &gpio1;
	21	gpio1 = &gpio2;
	22	gpio2 = &gpio3;
	23	gpio3 = &gpio4;
	24	gpio4 = &gpio5;
	25	gpio5 = &gpio6;
	26	serial0 = &uart1;
	27	serial1 = &uart2;
	28	serial2 = &uart3;
	29	serial3 = &uart4;
	30	serial4 = &uart5;
	31	};
	32
	33	cpus {
	34	#address-cells = <1>;
	35	#size-cells = <0>;
	36	cpu@0 {
	37	device_type = "cpu";
	38	compatible = "arm,cortex-a8";
	39	reg = <0x0>;
	40	};
	41	};
	42
	43	tzic: tz-interrupt-controller@0fffc000 {
	44	compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
	45	interrupt-controller;
	46	#interrupt-cells = <1>;
	47	reg = <0x0fffc000 0x4000>;
	48	};
	49
	50	clocks {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53
	54	ckil {
	55	compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043	56	#clock-cells = <0>;
64972acd GU	57	clock-frequency = <32768>;
	58	};
	59
	60	ckih1 {
	61	compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043	62	#clock-cells = <0>;
64972acd GU	63	clock-frequency = <22579200>;
	64	};
	65
	66	ckih2 {
	67	compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043	68	#clock-cells = <0>;
64972acd GU	69	clock-frequency = <0>;
	70	};
	71
	72	osc {
	73	compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043	74	#clock-cells = <0>;
64972acd GU	75	clock-frequency = <24000000>;
	76	};
	77	};
	78
	79	soc {
	80	#address-cells = <1>;
	81	#size-cells = <1>;
	82	compatible = "simple-bus";
	83	interrupt-parent = <&tzic>;
	84	ranges;
	85
	86	aips@50000000 { /* AIPS1 */
	87	compatible = "fsl,aips-bus", "simple-bus";
	88	#address-cells = <1>;
	89	#size-cells = <1>;
	90	reg = <0x50000000 0x10000000>;
	91	ranges;
	92
	93	spba@50000000 {
	94	compatible = "fsl,spba-bus", "simple-bus";
	95	#address-cells = <1>;
	96	#size-cells = <1>;
	97	reg = <0x50000000 0x40000>;
	98	ranges;
	99
	100	esdhc1: esdhc@50004000 {
	101	compatible = "fsl,imx50-esdhc";
	102	reg = <0x50004000 0x4000>;
	103	interrupts = <1>;
6650d6db LS	104	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	105	<&clks IMX5_CLK_DUMMY>,
	106	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
64972acd GU	107	clock-names = "ipg", "ahb", "per";
	108	bus-width = <4>;
	109	status = "disabled";
	110	};
	111
	112	esdhc2: esdhc@50008000 {
	113	compatible = "fsl,imx50-esdhc";
	114	reg = <0x50008000 0x4000>;
	115	interrupts = <2>;
6650d6db LS	116	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	117	<&clks IMX5_CLK_DUMMY>,
	118	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
64972acd GU	119	clock-names = "ipg", "ahb", "per";
	120	bus-width = <4>;
	121	status = "disabled";
	122	};
	123
	124	uart3: serial@5000c000 {
	125	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	126	reg = <0x5000c000 0x4000>;
	127	interrupts = <33>;
6650d6db LS	128	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
6650d6db LS	129	<&clks IMX5_CLK_UART3_PER_GATE>;
64972acd GU	130	clock-names = "ipg", "per";
	131	status = "disabled";
	132	};
	133
	134	ecspi1: ecspi@50010000 {
	135	#address-cells = <1>;
	136	#size-cells = <0>;
	137	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	138	reg = <0x50010000 0x4000>;
	139	interrupts = <36>;
6650d6db LS	140	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
6650d6db LS	141	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
64972acd GU	142	clock-names = "ipg", "per";
	143	status = "disabled";
	144	};
	145
	146	ssi2: ssi@50014000 {
28f93d0b MP	147	compatible = "fsl,imx50-ssi",
	148	"fsl,imx51-ssi",
	149	"fsl,imx21-ssi";
64972acd GU	150	reg = <0x50014000 0x4000>;
64972acd GU	151	interrupts = <30>;
6650d6db	152	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
64972acd GU	153	fsl,fifo-depth = <15>;
	154	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	155	status = "disabled";
	156	};
	157
	158	esdhc3: esdhc@50020000 {
	159	compatible = "fsl,imx50-esdhc";
	160	reg = <0x50020000 0x4000>;
	161	interrupts = <3>;
6650d6db LS	162	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	163	<&clks IMX5_CLK_DUMMY>,
	164	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
64972acd GU	165	clock-names = "ipg", "ahb", "per";
	166	bus-width = <4>;
	167	status = "disabled";
	168	};
	169
	170	esdhc4: esdhc@50024000 {
	171	compatible = "fsl,imx50-esdhc";
	172	reg = <0x50024000 0x4000>;
	173	interrupts = <4>;
6650d6db LS	174	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	175	<&clks IMX5_CLK_DUMMY>,
	176	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
64972acd GU	177	clock-names = "ipg", "ahb", "per";
	178	bus-width = <4>;
	179	status = "disabled";
	180	};
	181	};
	182
	183	usbotg: usb@53f80000 {
	184	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	185	reg = <0x53f80000 0x0200>;
	186	interrupts = <18>;
6650d6db	187	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
64972acd GU	188	status = "disabled";
	189	};
	190
	191	usbh1: usb@53f80200 {
	192	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	193	reg = <0x53f80200 0x0200>;
	194	interrupts = <14>;
6650d6db	195	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
64972acd GU	196	status = "disabled";
	197	};
	198
	199	usbh2: usb@53f80400 {
	200	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	201	reg = <0x53f80400 0x0200>;
	202	interrupts = <16>;
6650d6db	203	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	204	status = "disabled";
	205	};
	206
	207	usbh3: usb@53f80600 {
	208	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	209	reg = <0x53f80600 0x0200>;
	210	interrupts = <17>;
6650d6db	211	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	212	status = "disabled";
	213	};
	214
	215	gpio1: gpio@53f84000 {
	216	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	217	reg = <0x53f84000 0x4000>;
	218	interrupts = <50 51>;
	219	gpio-controller;
	220	#gpio-cells = <2>;
	221	interrupt-controller;
	222	#interrupt-cells = <2>;
	223	};
	224
	225	gpio2: gpio@53f88000 {
	226	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	227	reg = <0x53f88000 0x4000>;
	228	interrupts = <52 53>;
	229	gpio-controller;
	230	#gpio-cells = <2>;
	231	interrupt-controller;
	232	#interrupt-cells = <2>;
	233	};
	234
	235	gpio3: gpio@53f8c000 {
	236	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	237	reg = <0x53f8c000 0x4000>;
	238	interrupts = <54 55>;
	239	gpio-controller;
	240	#gpio-cells = <2>;
	241	interrupt-controller;
	242	#interrupt-cells = <2>;
	243	};
	244
	245	gpio4: gpio@53f90000 {
	246	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	247	reg = <0x53f90000 0x4000>;
	248	interrupts = <56 57>;
	249	gpio-controller;
	250	#gpio-cells = <2>;
	251	interrupt-controller;
	252	#interrupt-cells = <2>;
	253	};
	254
	255	wdog1: wdog@53f98000 {
	256	compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
	257	reg = <0x53f98000 0x4000>;
	258	interrupts = <58>;
6650d6db	259	clocks = <&clks IMX5_CLK_DUMMY>;
64972acd GU	260	};
	261
	262	gpt: timer@53fa0000 {
	263	compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
	264	reg = <0x53fa0000 0x4000>;
	265	interrupts = <39>;
6650d6db LS	266	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
6650d6db LS	267	<&clks IMX5_CLK_GPT_HF_GATE>;
64972acd GU	268	clock-names = "ipg", "per";
	269	};
	270
	271	iomuxc: iomuxc@53fa8000 {
	272	compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
	273	reg = <0x53fa8000 0x4000>;
	274	};
	275
	276	gpr: iomuxc-gpr@53fa8000 {
	277	compatible = "fsl,imx50-iomuxc-gpr", "syscon";
	278	reg = <0x53fa8000 0xc>;
	279	};
	280
	281	pwm1: pwm@53fb4000 {
	282	#pwm-cells = <2>;
	283	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	284	reg = <0x53fb4000 0x4000>;
6650d6db LS	285	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
6650d6db LS	286	<&clks IMX5_CLK_PWM1_HF_GATE>;
64972acd GU	287	clock-names = "ipg", "per";
	288	interrupts = <61>;
	289	};
	290
	291	pwm2: pwm@53fb8000 {
	292	#pwm-cells = <2>;
	293	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	294	reg = <0x53fb8000 0x4000>;
6650d6db LS	295	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
6650d6db LS	296	<&clks IMX5_CLK_PWM2_HF_GATE>;
64972acd GU	297	clock-names = "ipg", "per";
	298	interrupts = <94>;
	299	};
	300
	301	uart1: serial@53fbc000 {
	302	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	303	reg = <0x53fbc000 0x4000>;
	304	interrupts = <31>;
6650d6db LS	305	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
6650d6db LS	306	<&clks IMX5_CLK_UART1_PER_GATE>;
64972acd GU	307	clock-names = "ipg", "per";
	308	status = "disabled";
	309	};
	310
	311	uart2: serial@53fc0000 {
	312	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	313	reg = <0x53fc0000 0x4000>;
	314	interrupts = <32>;
6650d6db LS	315	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
6650d6db LS	316	<&clks IMX5_CLK_UART2_PER_GATE>;
64972acd GU	317	clock-names = "ipg", "per";
	318	status = "disabled";
	319	};
	320
	321	src: src@53fd0000 {
	322	compatible = "fsl,imx50-src", "fsl,imx51-src";
	323	reg = <0x53fd0000 0x4000>;
	324	#reset-cells = <1>;
	325	};
	326
	327	clks: ccm@53fd4000{
	328	compatible = "fsl,imx50-ccm";
	329	reg = <0x53fd4000 0x4000>;
	330	interrupts = <0 71 0x04 0 72 0x04>;
	331	#clock-cells = <1>;
	332	};
	333
	334	gpio5: gpio@53fdc000 {
	335	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	336	reg = <0x53fdc000 0x4000>;
	337	interrupts = <103 104>;
	338	gpio-controller;
	339	#gpio-cells = <2>;
	340	interrupt-controller;
	341	#interrupt-cells = <2>;
	342	};
	343
	344	gpio6: gpio@53fe0000 {
	345	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	346	reg = <0x53fe0000 0x4000>;
	347	interrupts = <105 106>;
	348	gpio-controller;
	349	#gpio-cells = <2>;
	350	interrupt-controller;
	351	#interrupt-cells = <2>;
	352	};
	353
	354	i2c3: i2c@53fec000 {
	355	#address-cells = <1>;
	356	#size-cells = <0>;
	357	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	358	reg = <0x53fec000 0x4000>;
	359	interrupts = <64>;
6650d6db	360	clocks = <&clks IMX5_CLK_I2C3_GATE>;
64972acd GU	361	status = "disabled";
	362	};
	363
	364	uart4: serial@53ff0000 {
	365	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	366	reg = <0x53ff0000 0x4000>;
	367	interrupts = <13>;
6650d6db LS	368	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
6650d6db LS	369	<&clks IMX5_CLK_UART4_PER_GATE>;
64972acd GU	370	clock-names = "ipg", "per";
	371	status = "disabled";
	372	};
	373	};
	374
	375	aips@60000000 { /* AIPS2 */
	376	compatible = "fsl,aips-bus", "simple-bus";
	377	#address-cells = <1>;
	378	#size-cells = <1>;
	379	reg = <0x60000000 0x10000000>;
	380	ranges;
	381
	382	uart5: serial@63f90000 {
	383	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	384	reg = <0x63f90000 0x4000>;
	385	interrupts = <86>;
6650d6db LS	386	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
6650d6db LS	387	<&clks IMX5_CLK_UART5_PER_GATE>;
64972acd GU	388	clock-names = "ipg", "per";
	389	status = "disabled";
	390	};
	391
	392	owire: owire@63fa4000 {
	393	compatible = "fsl,imx50-owire", "fsl,imx21-owire";
	394	reg = <0x63fa4000 0x4000>;
6650d6db	395	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
64972acd GU	396	status = "disabled";
	397	};
	398
	399	ecspi2: ecspi@63fac000 {
	400	#address-cells = <1>;
	401	#size-cells = <0>;
	402	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	403	reg = <0x63fac000 0x4000>;
	404	interrupts = <37>;
6650d6db LS	405	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
6650d6db LS	406	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
64972acd GU	407	clock-names = "ipg", "per";
	408	status = "disabled";
	409	};
	410
	411	sdma: sdma@63fb0000 {
	412	compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
	413	reg = <0x63fb0000 0x4000>;
	414	interrupts = <6>;
6650d6db LS	415	clocks = <&clks IMX5_CLK_SDMA_GATE>,
6650d6db LS	416	<&clks IMX5_CLK_SDMA_GATE>;
64972acd GU	417	clock-names = "ipg", "ahb";
	418	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
	419	};
	420
	421	cspi: cspi@63fc0000 {
	422	#address-cells = <1>;
	423	#size-cells = <0>;
	424	compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
	425	reg = <0x63fc0000 0x4000>;
	426	interrupts = <38>;
6650d6db LS	427	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
6650d6db LS	428	<&clks IMX5_CLK_CSPI_IPG_GATE>;
64972acd GU	429	clock-names = "ipg", "per";
	430	status = "disabled";
	431	};
	432
	433	i2c2: i2c@63fc4000 {
	434	#address-cells = <1>;
	435	#size-cells = <0>;
	436	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	437	reg = <0x63fc4000 0x4000>;
	438	interrupts = <63>;
6650d6db	439	clocks = <&clks IMX5_CLK_I2C2_GATE>;
64972acd GU	440	status = "disabled";
	441	};
	442
	443	i2c1: i2c@63fc8000 {
	444	#address-cells = <1>;
	445	#size-cells = <0>;
	446	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	447	reg = <0x63fc8000 0x4000>;
	448	interrupts = <62>;
6650d6db	449	clocks = <&clks IMX5_CLK_I2C1_GATE>;
64972acd GU	450	status = "disabled";
	451	};
	452
	453	ssi1: ssi@63fcc000 {
28f93d0b MP	454	compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
28f93d0b MP	455	"fsl,imx21-ssi";
64972acd GU	456	reg = <0x63fcc000 0x4000>;
64972acd GU	457	interrupts = <29>;
6650d6db	458	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
64972acd GU	459	fsl,fifo-depth = <15>;
	460	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	461	status = "disabled";
	462	};
	463
	464	audmux: audmux@63fd0000 {
	465	compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
	466	reg = <0x63fd0000 0x4000>;
	467	status = "disabled";
	468	};
	469
	470	fec: ethernet@63fec000 {
	471	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	472	reg = <0x63fec000 0x4000>;
	473	interrupts = <87>;
6650d6db LS	474	clocks = <&clks IMX5_CLK_FEC_GATE>,
	475	<&clks IMX5_CLK_FEC_GATE>,
	476	<&clks IMX5_CLK_FEC_GATE>;
64972acd GU	477	clock-names = "ipg", "ahb", "ptp";
	478	status = "disabled";
	479	};
	480	};
	481	};
	482	};