[deliverable/linux.git] / arch / arm / boot / dts / imx51-babbage.dts

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx51.dtsi"

/ {
	model = "Freescale i.MX51 Babbage Board";
	compatible = "fsl,imx51-babbage", "fsl,imx51";

	memory {
		reg = <0x90000000 0x20000000>;
	};

	display0: display@di0 {
		compatible = "fsl,imx-parallel-display";
		interface-pix-fmt = "rgb24";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_disp1>;
		display-timings {
			native-mode = <&timing0>;
			timing0: dvi {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};

		port {
			display0_in: endpoint {
				remote-endpoint = <&ipu_di0_disp0>;
			};
		};
	};

	display1: display@di1 {
		compatible = "fsl,imx-parallel-display";
		interface-pix-fmt = "rgb565";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_disp2>;
		status = "disabled";
		display-timings {
			native-mode = <&timing1>;
			timing1: claawvga {
				clock-frequency = <27000000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <40>;
				hfront-porch = <60>;
				vback-porch = <10>;
				vfront-porch = <10>;
				hsync-len = <20>;
				vsync-len = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};

		port {
			display1_in: endpoint {
				remote-endpoint = <&ipu_di1_disp1>;
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		power {
			label = "Power Button";
			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_POWER>;
			gpio-key,wakeup;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-diagnostic {
			label = "diagnostic";
			gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		};
	};

	sound {
		compatible = "fsl,imx51-babbage-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx51-babbage-sgtl5000";
		ssi-controller = <&ssi2>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <2>;
		mux-ext-port = <3>;
	};

	clocks {
		ckih1 {
			clock-frequency = <22579200>;
		};

		clk_26M: codec_clock {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <26000000>;
			gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb_vbus: regulator@0 {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usbreg>;
			reg = <0>;
			regulator-name = "usb_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};

	usbphy {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "simple-bus";

		usbh1phy: usbh1phy@0 {
			compatible = "usb-nop-xceiv";
			reg = <0>;
			clocks = <&clks 0>;
			clock-names = "main_clk";
		};
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	fsl,cd-controller;
	fsl,wp-controller;
	status = "okay";
};

&esdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc2>;
	cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	fsl,spi-num-chipselects = <2>;
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
		   <&gpio4 25 GPIO_ACTIVE_LOW>;
	status = "okay";

	pmic: mc13892@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mc13892";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		spi-max-frequency = <6000000>;
		spi-cs-high;
		reg = <0>;
		interrupt-parent = <&gpio1>;
		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

		regulators {
			sw1_reg: sw1 {
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1375000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vpll_reg: vpll {
				regulator-min-microvolt = <1050000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vdig_reg: vdig {
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
			};

			vsd_reg: vsd {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3150000>;
			};

			vusb2_reg: vusb2 {
				regulator-min-microvolt = <2400000>;
				regulator-max-microvolt = <2775000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vvideo_reg: vvideo {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
			};

			vaudio_reg: vaudio {
				regulator-min-microvolt = <2300000>;
				regulator-max-microvolt = <3000000>;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3000000>;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2900000>;
				regulator-always-on;
			};
		};
	};

	flash: at45db321d@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
		spi-max-frequency = <25000000>;
		reg = <1>;

		partition@0 {
			label = "U-Boot";
			reg = <0x0 0x40000>;
			read-only;
		};

		partition@40000 {
			label = "Kernel";
			reg = <0x40000 0x3c0000>;
		};
	};
};

&ipu_di0_disp0 {
	remote-endpoint = <&display0_in>;
};

&ipu_di1_disp1 {
	remote-endpoint = <&display1_in>;
};

&ssi2 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&iomuxc {
	imx51-babbage {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX51_PAD_AUD3_BB_TXD__AUD3_TXD		0x80000000
				MX51_PAD_AUD3_BB_RXD__AUD3_RXD		0x80000000
				MX51_PAD_AUD3_BB_CK__AUD3_TXC		0x80000000
				MX51_PAD_AUD3_BB_FS__AUD3_TXFS		0x80000000
			>;
		};

		pinctrl_clkcodec: clkcodecgrp {
			fsl,pins = <
				MX51_PAD_CSPI1_RDY__GPIO4_26		0x80000000
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
				MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */
				MX51_PAD_CSPI1_SS1__GPIO4_25		0x85 /* CS1 */
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
				MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
				MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
				MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
				MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
				MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
				MX51_PAD_GPIO1_0__SD1_CD		0x20d5
				MX51_PAD_GPIO1_1__SD1_WP		0x20d5
			>;
		};

		pinctrl_esdhc2: esdhc2grp {
			fsl,pins = <
				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
				MX51_PAD_GPIO1_5__GPIO1_5		0x100 /* WP */
				MX51_PAD_GPIO1_6__GPIO1_6		0x100 /* CD */
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX51_PAD_EIM_EB2__FEC_MDIO		0x80000000
				MX51_PAD_EIM_EB3__FEC_RDATA1		0x80000000
				MX51_PAD_EIM_CS2__FEC_RDATA2		0x80000000
				MX51_PAD_EIM_CS3__FEC_RDATA3		0x80000000
				MX51_PAD_EIM_CS4__FEC_RX_ER		0x80000000
				MX51_PAD_EIM_CS5__FEC_CRS		0x80000000
				MX51_PAD_NANDF_RB2__FEC_COL		0x80000000
				MX51_PAD_NANDF_RB3__FEC_RX_CLK		0x80000000
				MX51_PAD_NANDF_D9__FEC_RDATA0		0x80000000
				MX51_PAD_NANDF_D8__FEC_TDATA0		0x80000000
				MX51_PAD_NANDF_CS2__FEC_TX_ER		0x80000000
				MX51_PAD_NANDF_CS3__FEC_MDC		0x80000000
				MX51_PAD_NANDF_CS4__FEC_TDATA1		0x80000000
				MX51_PAD_NANDF_CS5__FEC_TDATA2		0x80000000
				MX51_PAD_NANDF_CS6__FEC_TDATA3		0x80000000
				MX51_PAD_NANDF_CS7__FEC_TX_EN		0x80000000
				MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	0x80000000
				MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
			>;
		};

		pinctrl_gpio_keys: gpiokeysgrp {
			fsl,pins = <
				MX51_PAD_EIM_A27__GPIO2_21		0x5
			>;
		};

		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
				MX51_PAD_EIM_D22__GPIO2_6		0x80000000
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX51_PAD_KEY_COL4__I2C2_SCL		0x400001ed
				MX51_PAD_KEY_COL5__I2C2_SDA		0x400001ed
			>;
		};

		pinctrl_ipu_disp1: ipudisp1grp {
			fsl,pins = <
				MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
				MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
				MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
				MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
				MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
				MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
				MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
				MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
				MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
				MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
				MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
				MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
				MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
				MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
				MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
				MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
				MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
				MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
				MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
				MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
				MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
				MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
				MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
				MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
				MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
				MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
			>;
		};

		pinctrl_ipu_disp2: ipudisp2grp {
			fsl,pins = <
				MX51_PAD_DISP2_DAT0__DISP2_DAT0		0x5
				MX51_PAD_DISP2_DAT1__DISP2_DAT1		0x5
				MX51_PAD_DISP2_DAT2__DISP2_DAT2		0x5
				MX51_PAD_DISP2_DAT3__DISP2_DAT3		0x5
				MX51_PAD_DISP2_DAT4__DISP2_DAT4		0x5
				MX51_PAD_DISP2_DAT5__DISP2_DAT5		0x5
				MX51_PAD_DISP2_DAT6__DISP2_DAT6		0x5
				MX51_PAD_DISP2_DAT7__DISP2_DAT7		0x5
				MX51_PAD_DISP2_DAT8__DISP2_DAT8		0x5
				MX51_PAD_DISP2_DAT9__DISP2_DAT9		0x5
				MX51_PAD_DISP2_DAT10__DISP2_DAT10	0x5
				MX51_PAD_DISP2_DAT11__DISP2_DAT11	0x5
				MX51_PAD_DISP2_DAT12__DISP2_DAT12	0x5
				MX51_PAD_DISP2_DAT13__DISP2_DAT13	0x5
				MX51_PAD_DISP2_DAT14__DISP2_DAT14	0x5
				MX51_PAD_DISP2_DAT15__DISP2_DAT15	0x5
				MX51_PAD_DI2_PIN2__DI2_PIN2		0x5
				MX51_PAD_DI2_PIN3__DI2_PIN3		0x5
				MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	0x5
				MX51_PAD_DI_GP4__DI2_PIN15		0x5
			>;
		};

		pinctrl_kpp: kppgrp {
			fsl,pins = <
				MX51_PAD_KEY_ROW0__KEY_ROW0		0xe0
				MX51_PAD_KEY_ROW1__KEY_ROW1		0xe0
				MX51_PAD_KEY_ROW2__KEY_ROW2		0xe0
				MX51_PAD_KEY_ROW3__KEY_ROW3		0xe0
				MX51_PAD_KEY_COL0__KEY_COL0		0xe8
				MX51_PAD_KEY_COL1__KEY_COL1		0xe8
				MX51_PAD_KEY_COL2__KEY_COL2		0xe8
				MX51_PAD_KEY_COL3__KEY_COL3		0xe8
			>;
		};

		pinctrl_pmic: pmicgrp {
			fsl,pins = <
				MX51_PAD_GPIO1_8__GPIO1_8		0xe5 /* IRQ */
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
				MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
				MX51_PAD_UART1_RTS__UART1_RTS		0x1c5
				MX51_PAD_UART1_CTS__UART1_CTS		0x1c5
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX51_PAD_UART2_RXD__UART2_RXD		0x1c5
				MX51_PAD_UART2_TXD__UART2_TXD		0x1c5
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX51_PAD_EIM_D25__UART3_RXD		0x1c5
				MX51_PAD_EIM_D26__UART3_TXD		0x1c5
				MX51_PAD_EIM_D27__UART3_RTS		0x1c5
				MX51_PAD_EIM_D24__UART3_CTS		0x1c5
			>;
		};

		pinctrl_usbh1: usbh1grp {
			fsl,pins = <
				MX51_PAD_USBH1_CLK__USBH1_CLK		0x80000000
				MX51_PAD_USBH1_DIR__USBH1_DIR		0x80000000
				MX51_PAD_USBH1_NXT__USBH1_NXT		0x80000000
				MX51_PAD_USBH1_DATA0__USBH1_DATA0	0x80000000
				MX51_PAD_USBH1_DATA1__USBH1_DATA1	0x80000000
				MX51_PAD_USBH1_DATA2__USBH1_DATA2	0x80000000
				MX51_PAD_USBH1_DATA3__USBH1_DATA3	0x80000000
				MX51_PAD_USBH1_DATA4__USBH1_DATA4	0x80000000
				MX51_PAD_USBH1_DATA5__USBH1_DATA5	0x80000000
				MX51_PAD_USBH1_DATA6__USBH1_DATA6	0x80000000
				MX51_PAD_USBH1_DATA7__USBH1_DATA7	0x80000000
			>;
		};

		pinctrl_usbreg: usbreggrp {
			fsl,pins = <
				MX51_PAD_EIM_D21__GPIO2_5		0x85
			>;
		};
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	sgtl5000: codec@0a {
		compatible = "fsl,sgtl5000";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_clkcodec>;
		reg = <0x0a>;
		clocks = <&clk_26M>;
		VDDA-supply = <&vdig_reg>;
		VDDIO-supply = <&vvideo_reg>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	status = "okay";
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	linux,keymap = <
		MATRIX_KEY(0, 0, KEY_UP)
		MATRIX_KEY(0, 1, KEY_DOWN)
		MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
		MATRIX_KEY(0, 3, KEY_HOME)
		MATRIX_KEY(1, 0, KEY_RIGHT)
		MATRIX_KEY(1, 1, KEY_LEFT)
		MATRIX_KEY(1, 2, KEY_ENTER)
		MATRIX_KEY(1, 3, KEY_VOLUMEUP)
		MATRIX_KEY(2, 0, KEY_F6)
		MATRIX_KEY(2, 1, KEY_F8)
		MATRIX_KEY(2, 2, KEY_F9)
		MATRIX_KEY(2, 3, KEY_F10)
		MATRIX_KEY(3, 0, KEY_F1)
		MATRIX_KEY(3, 1, KEY_F2)
		MATRIX_KEY(3, 2, KEY_F3)
		MATRIX_KEY(3, 3, KEY_POWER)
		>;
	status = "okay";
};

&usbh1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1>;
	vbus-supply = <&reg_usb_vbus>;
	fsl,usbphy = <&usbh1phy>;
	phy_type = "ulpi";
	status = "okay";
};

&usbotg {
	dr_mode = "otg";
	disable-over-current;
	phy_type = "utmi_wide";
	status = "okay";
};
Commit	Line	Data
9daaf31a SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/dts-v1/;
36dffd8f	14	#include "imx51.dtsi"
9daaf31a SG	15
	16	/ {
	17	model = "Freescale i.MX51 Babbage Board";
	18	compatible = "fsl,imx51-babbage", "fsl,imx51";
	19
9daaf31a SG	20	memory {
	21	reg = <0x90000000 0x20000000>;
	22	};
	23
17b5001b	24	display0: display@di0 {
be4ccfce	25	compatible = "fsl,imx-parallel-display";
be4ccfce SG	26	interface-pix-fmt = "rgb24";
be4ccfce SG	27	pinctrl-names = "default";
5a2a7d57	28	pinctrl-0 = <&pinctrl_ipu_disp1>;
493a8636 FE	29	display-timings {
	30	native-mode = <&timing0>;
	31	timing0: dvi {
	32	clock-frequency = <65000000>;
	33	hactive = <1024>;
	34	vactive = <768>;
	35	hback-porch = <220>;
	36	hfront-porch = <40>;
	37	vback-porch = <21>;
	38	vfront-porch = <7>;
	39	hsync-len = <60>;
	40	vsync-len = <10>;
	41	};
	42	};
de10e04e PZ	43
	44	port {
	45	display0_in: endpoint {
	46	remote-endpoint = <&ipu_di0_disp0>;
	47	};
	48	};
be4ccfce	49	};
a15d9f89	50
17b5001b	51	display1: display@di1 {
be4ccfce	52	compatible = "fsl,imx-parallel-display";
be4ccfce SG	53	interface-pix-fmt = "rgb565";
be4ccfce SG	54	pinctrl-names = "default";
5a2a7d57	55	pinctrl-0 = <&pinctrl_ipu_disp2>;
493a8636 FE	56	status = "disabled";
	57	display-timings {
	58	native-mode = <&timing1>;
	59	timing1: claawvga {
	60	clock-frequency = <27000000>;
	61	hactive = <800>;
	62	vactive = <480>;
	63	hback-porch = <40>;
	64	hfront-porch = <60>;
	65	vback-porch = <10>;
	66	vfront-porch = <10>;
	67	hsync-len = <20>;
	68	vsync-len = <10>;
	69	hsync-active = <0>;
	70	vsync-active = <0>;
	71	de-active = <1>;
	72	pixelclk-active = <0>;
	73	};
	74	};
de10e04e PZ	75
	76	port {
	77	display1_in: endpoint {
	78	remote-endpoint = <&ipu_di1_disp1>;
	79	};
	80	};
9daaf31a SG	81	};
	82
	83	gpio-keys {
	84	compatible = "gpio-keys";
2ccc447c AS	85	pinctrl-names = "default";
2ccc447c AS	86	pinctrl-0 = <&pinctrl_gpio_keys>;
9daaf31a SG	87
	88	power {
	89	label = "Power Button";
bdb3eec7	90	gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
02134e77	91	linux,code = <KEY_POWER>;
9daaf31a SG	92	gpio-key,wakeup;
	93	};
	94	};
a15d9f89	95
a198af23 LY	96	leds {
	97	compatible = "gpio-leds";
	98	pinctrl-names = "default";
	99	pinctrl-0 = <&pinctrl_gpio_leds>;
	100
	101	led-diagnostic {
	102	label = "diagnostic";
	103	gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
	104	};
	105	};
	106
a15d9f89 SG	107	sound {
	108	compatible = "fsl,imx51-babbage-sgtl5000",
	109	"fsl,imx-audio-sgtl5000";
	110	model = "imx51-babbage-sgtl5000";
	111	ssi-controller = <&ssi2>;
	112	audio-codec = <&sgtl5000>;
	113	audio-routing =
	114	"MIC_IN", "Mic Jack",
	115	"Mic Jack", "Mic Bias",
	116	"Headphone Jack", "HP_OUT";
	117	mux-int-port = <2>;
	118	mux-ext-port = <3>;
	119	};
84bb0847 FE	120
84bb0847 FE	121	clocks {
677e28b1 AS	122	ckih1 {
	123	clock-frequency = <22579200>;
	124	};
	125
84bb0847 FE	126	clk_26M: codec_clock {
	127	compatible = "fixed-clock";
	128	reg=<0>;
	129	#clock-cells = <0>;
	130	clock-frequency = <26000000>;
bdb3eec7	131	gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
84bb0847 FE	132	};
84bb0847 FE	133	};
9bf206a9 FE	134
	135	regulators {
	136	compatible = "simple-bus";
	137	#address-cells = <1>;
	138	#size-cells = <0>;
	139
	140	reg_usb_vbus: regulator@0 {
	141	compatible = "regulator-fixed";
2ccc447c AS	142	pinctrl-names = "default";
2ccc447c AS	143	pinctrl-0 = <&pinctrl_usbreg>;
9bf206a9 FE	144	reg = <0>;
	145	regulator-name = "usb_vbus";
	146	regulator-min-microvolt = <5000000>;
	147	regulator-max-microvolt = <5000000>;
2ccc447c	148	gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
9bf206a9 FE	149	enable-active-high;
	150	};
	151	};
	152
	153	usbphy {
	154	#address-cells = <1>;
	155	#size-cells = <0>;
	156	compatible = "simple-bus";
	157
	158	usbh1phy: usbh1phy@0 {
	159	compatible = "usb-nop-xceiv";
	160	reg = <0>;
	161	clocks = <&clks 0>;
	162	clock-names = "main_clk";
	163	};
	164	};
9daaf31a	165	};
be4ccfce SG	166
	167	&esdhc1 {
	168	pinctrl-names = "default";
5a2a7d57	169	pinctrl-0 = <&pinctrl_esdhc1>;
be4ccfce SG	170	fsl,cd-controller;
	171	fsl,wp-controller;
	172	status = "okay";
	173	};
	174
	175	&esdhc2 {
	176	pinctrl-names = "default";
5a2a7d57	177	pinctrl-0 = <&pinctrl_esdhc2>;
bdb3eec7 AS	178	cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
bdb3eec7 AS	179	wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
be4ccfce SG	180	status = "okay";
	181	};
	182
	183	&uart3 {
	184	pinctrl-names = "default";
5a2a7d57	185	pinctrl-0 = <&pinctrl_uart3>;
be4ccfce SG	186	fsl,uart-has-rtscts;
	187	status = "okay";
	188	};
	189
	190	&ecspi1 {
	191	pinctrl-names = "default";
5a2a7d57	192	pinctrl-0 = <&pinctrl_ecspi1>;
be4ccfce	193	fsl,spi-num-chipselects = <2>;
bdb3eec7	194	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
d2176f29	195	<&gpio4 25 GPIO_ACTIVE_LOW>;
be4ccfce SG	196	status = "okay";
	197
	198	pmic: mc13892@0 {
	199	#address-cells = <1>;
	200	#size-cells = <0>;
	201	compatible = "fsl,mc13892";
1ddcff4b AS	202	pinctrl-names = "default";
1ddcff4b AS	203	pinctrl-0 = <&pinctrl_pmic>;
be4ccfce	204	spi-max-frequency = <6000000>;
dc071436	205	spi-cs-high;
be4ccfce SG	206	reg = <0>;
be4ccfce SG	207	interrupt-parent = <&gpio1>;
1cbb74fd	208	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
be4ccfce SG	209
	210	regulators {
	211	sw1_reg: sw1 {
	212	regulator-min-microvolt = <600000>;
	213	regulator-max-microvolt = <1375000>;
	214	regulator-boot-on;
	215	regulator-always-on;
	216	};
	217
	218	sw2_reg: sw2 {
	219	regulator-min-microvolt = <900000>;
	220	regulator-max-microvolt = <1850000>;
	221	regulator-boot-on;
	222	regulator-always-on;
	223	};
	224
	225	sw3_reg: sw3 {
	226	regulator-min-microvolt = <1100000>;
	227	regulator-max-microvolt = <1850000>;
	228	regulator-boot-on;
	229	regulator-always-on;
	230	};
	231
	232	sw4_reg: sw4 {
	233	regulator-min-microvolt = <1100000>;
	234	regulator-max-microvolt = <1850000>;
	235	regulator-boot-on;
	236	regulator-always-on;
	237	};
	238
	239	vpll_reg: vpll {
	240	regulator-min-microvolt = <1050000>;
	241	regulator-max-microvolt = <1800000>;
	242	regulator-boot-on;
	243	regulator-always-on;
	244	};
	245
	246	vdig_reg: vdig {
	247	regulator-min-microvolt = <1650000>;
	248	regulator-max-microvolt = <1650000>;
	249	regulator-boot-on;
	250	};
	251
	252	vsd_reg: vsd {
	253	regulator-min-microvolt = <1800000>;
	254	regulator-max-microvolt = <3150000>;
	255	};
	256
	257	vusb2_reg: vusb2 {
	258	regulator-min-microvolt = <2400000>;
	259	regulator-max-microvolt = <2775000>;
	260	regulator-boot-on;
	261	regulator-always-on;
	262	};
	263
	264	vvideo_reg: vvideo {
	265	regulator-min-microvolt = <2775000>;
	266	regulator-max-microvolt = <2775000>;
	267	};
	268
	269	vaudio_reg: vaudio {
	270	regulator-min-microvolt = <2300000>;
	271	regulator-max-microvolt = <3000000>;
	272	};
273
274	vcam_reg: vcam {
275	regulator-min-microvolt = <2500000>;
276	regulator-max-microvolt = <3000000>;
277	};
278
279	vgen1_reg: vgen1 {
280	regulator-min-microvolt = <1200000>;
281	regulator-max-microvolt = <1200000>;
282	};
283
284	vgen2_reg: vgen2 {
285	regulator-min-microvolt = <1200000>;
286	regulator-max-microvolt = <3150000>;
287	regulator-always-on;
288	};
289
290	vgen3_reg: vgen3 {
291	regulator-min-microvolt = <1800000>;
292	regulator-max-microvolt = <2900000>;
293	regulator-always-on;
294	};
295	};
296	};
297
298	flash: at45db321d@1 {
299	#address-cells = <1>;
300	#size-cells = <1>;
301	compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
302	spi-max-frequency = <25000000>;
303	reg = <1>;
304
305	partition@0 {
306	label = "U-Boot";
307	reg = <0x0 0x40000>;
308	read-only;
309	};
310
311	partition@40000 {
312	label = "Kernel";
313	reg = <0x40000 0x3c0000>;
314	};
315	};
316	};
317
de10e04e PZ	318	&ipu_di0_disp0 {
	319	remote-endpoint = <&display0_in>;
	320	};
	321
	322	&ipu_di1_disp1 {
	323	remote-endpoint = <&display1_in>;
	324	};
	325
be4ccfce SG	326	&ssi2 {
	327	fsl,mode = "i2s-slave";
	328	status = "okay";
	329	};
	330
	331	&iomuxc {
5a2a7d57	332	imx51-babbage {
5a2a7d57 SG	333	pinctrl_audmux: audmuxgrp {
	334	fsl,pins = <
	335	MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
	336	MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
	337	MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
	338	MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
	339	>;
	340	};
	341
2ccc447c AS	342	pinctrl_clkcodec: clkcodecgrp {
	343	fsl,pins = <
	344	MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
	345	>;
	346	};
	347
5a2a7d57 SG	348	pinctrl_ecspi1: ecspi1grp {
	349	fsl,pins = <
	350	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	351	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	352	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
2ccc447c AS	353	MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
2ccc447c AS	354	MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
5a2a7d57 SG	355	>;
	356	};
	357
	358	pinctrl_esdhc1: esdhc1grp {
	359	fsl,pins = <
	360	MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
	361	MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
	362	MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
	363	MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
	364	MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
	365	MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
2ccc447c AS	366	MX51_PAD_GPIO1_0__SD1_CD 0x20d5
2ccc447c AS	367	MX51_PAD_GPIO1_1__SD1_WP 0x20d5
5a2a7d57 SG	368	>;
	369	};
	370
	371	pinctrl_esdhc2: esdhc2grp {
	372	fsl,pins = <
	373	MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
	374	MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
	375	MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
	376	MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
	377	MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
	378	MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
2ccc447c AS	379	MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
2ccc447c AS	380	MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
5a2a7d57 SG	381	>;
	382	};
	383
	384	pinctrl_fec: fecgrp {
	385	fsl,pins = <
	386	MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
	387	MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
	388	MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
	389	MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
	390	MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
	391	MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
	392	MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
	393	MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
	394	MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
	395	MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
	396	MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
	397	MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
	398	MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
	399	MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
	400	MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
	401	MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
	402	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
0c33f667	403	MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
5a2a7d57 SG	404	>;
	405	};
	406
2ccc447c AS	407	pinctrl_gpio_keys: gpiokeysgrp {
	408	fsl,pins = <
	409	MX51_PAD_EIM_A27__GPIO2_21 0x5
	410	>;
	411	};
	412
a198af23 LY	413	pinctrl_gpio_leds: gpioledsgrp {
	414	fsl,pins = <
	415	MX51_PAD_EIM_D22__GPIO2_6 0x80000000
	416	>;
	417	};
	418
5a2a7d57 SG	419	pinctrl_i2c2: i2c2grp {
	420	fsl,pins = <
	421	MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
	422	MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
	423	>;
	424	};
	425
	426	pinctrl_ipu_disp1: ipudisp1grp {
	427	fsl,pins = <
	428	MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
	429	MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
	430	MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
	431	MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
	432	MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
	433	MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
	434	MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
	435	MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
	436	MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
	437	MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
	438	MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
	439	MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
	440	MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
	441	MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
	442	MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
	443	MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
	444	MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
	445	MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
	446	MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
	447	MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
	448	MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
	449	MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
	450	MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
	451	MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
	452	MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
	453	MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
	454	>;
	455	};
	456
	457	pinctrl_ipu_disp2: ipudisp2grp {
	458	fsl,pins = <
	459	MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
	460	MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
	461	MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
	462	MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
	463	MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
	464	MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
	465	MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
	466	MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
	467	MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
	468	MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
	469	MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
	470	MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
	471	MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
	472	MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
	473	MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
	474	MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
	475	MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
	476	MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
	477	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
	478	MX51_PAD_DI_GP4__DI2_PIN15 0x5
	479	>;
	480	};
	481
	482	pinctrl_kpp: kppgrp {
483	fsl,pins = <
484	MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
485	MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
486	MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
487	MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
488	MX51_PAD_KEY_COL0__KEY_COL0 0xe8
489	MX51_PAD_KEY_COL1__KEY_COL1 0xe8
490	MX51_PAD_KEY_COL2__KEY_COL2 0xe8
491	MX51_PAD_KEY_COL3__KEY_COL3 0xe8
492	>;
493	};
494
1ddcff4b AS	495	pinctrl_pmic: pmicgrp {
	496	fsl,pins = <
	497	MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
	498	>;
	499	};
	500
5a2a7d57 SG	501	pinctrl_uart1: uart1grp {
	502	fsl,pins = <
	503	MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
	504	MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
	505	MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
	506	MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
	507	>;
	508	};
	509
	510	pinctrl_uart2: uart2grp {
	511	fsl,pins = <
	512	MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
	513	MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
	514	>;
	515	};
	516
	517	pinctrl_uart3: uart3grp {
	518	fsl,pins = <
	519	MX51_PAD_EIM_D25__UART3_RXD 0x1c5
	520	MX51_PAD_EIM_D26__UART3_TXD 0x1c5
	521	MX51_PAD_EIM_D27__UART3_RTS 0x1c5
	522	MX51_PAD_EIM_D24__UART3_CTS 0x1c5
	523	>;
	524	};
9bf206a9 FE	525
	526	pinctrl_usbh1: usbh1grp {
	527	fsl,pins = <
	528	MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
	529	MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
	530	MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
	531	MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
	532	MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
	533	MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
	534	MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
	535	MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
	536	MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
	537	MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
	538	MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
2ccc447c AS	539	>;
	540	};
	541
	542	pinctrl_usbreg: usbreggrp {
	543	fsl,pins = <
	544	MX51_PAD_EIM_D21__GPIO2_5 0x85
9bf206a9 FE	545	>;
9bf206a9 FE	546	};
be4ccfce SG	547	};
	548	};
	549
	550	&uart1 {
	551	pinctrl-names = "default";
5a2a7d57	552	pinctrl-0 = <&pinctrl_uart1>;
be4ccfce SG	553	fsl,uart-has-rtscts;
	554	status = "okay";
	555	};
	556
	557	&uart2 {
	558	pinctrl-names = "default";
5a2a7d57	559	pinctrl-0 = <&pinctrl_uart2>;
be4ccfce SG	560	status = "okay";
	561	};
	562
	563	&i2c2 {
	564	pinctrl-names = "default";
5a2a7d57	565	pinctrl-0 = <&pinctrl_i2c2>;
be4ccfce SG	566	status = "okay";
	567
	568	sgtl5000: codec@0a {
	569	compatible = "fsl,sgtl5000";
2ccc447c AS	570	pinctrl-names = "default";
2ccc447c AS	571	pinctrl-0 = <&pinctrl_clkcodec>;
be4ccfce	572	reg = <0x0a>;
84bb0847	573	clocks = <&clk_26M>;
be4ccfce SG	574	VDDA-supply = <&vdig_reg>;
	575	VDDIO-supply = <&vvideo_reg>;
	576	};
	577	};
	578
	579	&audmux {
	580	pinctrl-names = "default";
5a2a7d57	581	pinctrl-0 = <&pinctrl_audmux>;
be4ccfce SG	582	status = "okay";
	583	};
	584
	585	&fec {
	586	pinctrl-names = "default";
5a2a7d57	587	pinctrl-0 = <&pinctrl_fec>;
be4ccfce	588	phy-mode = "mii";
0c33f667 AS	589	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
0c33f667 AS	590	phy-reset-duration = <1>;
be4ccfce SG	591	status = "okay";
be4ccfce SG	592	};
67eb7c0b LY	593
	594	&kpp {
	595	pinctrl-names = "default";
5a2a7d57	596	pinctrl-0 = <&pinctrl_kpp>;
72d86d26 AS	597	linux,keymap = <
	598	MATRIX_KEY(0, 0, KEY_UP)
	599	MATRIX_KEY(0, 1, KEY_DOWN)
	600	MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
	601	MATRIX_KEY(0, 3, KEY_HOME)
	602	MATRIX_KEY(1, 0, KEY_RIGHT)
	603	MATRIX_KEY(1, 1, KEY_LEFT)
	604	MATRIX_KEY(1, 2, KEY_ENTER)
	605	MATRIX_KEY(1, 3, KEY_VOLUMEUP)
	606	MATRIX_KEY(2, 0, KEY_F6)
	607	MATRIX_KEY(2, 1, KEY_F8)
	608	MATRIX_KEY(2, 2, KEY_F9)
	609	MATRIX_KEY(2, 3, KEY_F10)
	610	MATRIX_KEY(3, 0, KEY_F1)
	611	MATRIX_KEY(3, 1, KEY_F2)
	612	MATRIX_KEY(3, 2, KEY_F3)
	613	MATRIX_KEY(3, 3, KEY_POWER)
	614	>;
67eb7c0b LY	615	status = "okay";
67eb7c0b LY	616	};
9bf206a9 FE	617
	618	&usbh1 {
	619	pinctrl-names = "default";
	620	pinctrl-0 = <&pinctrl_usbh1>;
	621	vbus-supply = <&reg_usb_vbus>;
	622	fsl,usbphy = <&usbh1phy>;
	623	phy_type = "ulpi";
	624	status = "okay";
	625	};
7538d4ff FE	626
	627	&usbotg {
	628	dr_mode = "otg";
	629	disable-over-current;
	630	phy_type = "utmi_wide";
	631	status = "okay";
	632	};