[deliverable/linux.git] / arch / arm / boot / dts / imx51-babbage.dts

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx51.dtsi"

/ {
	model = "Freescale i.MX51 Babbage Board";
	compatible = "fsl,imx51-babbage", "fsl,imx51";

	memory {
		reg = <0x90000000 0x20000000>;
	};

	display@di0 {
		compatible = "fsl,imx-parallel-display";
		crtcs = <&ipu 0>;
		interface-pix-fmt = "rgb24";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_disp1>;
		display-timings {
			native-mode = <&timing0>;
			timing0: dvi {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};

	display@di1 {
		compatible = "fsl,imx-parallel-display";
		crtcs = <&ipu 1>;
		interface-pix-fmt = "rgb565";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_disp2>;
		status = "disabled";
		display-timings {
			native-mode = <&timing1>;
			timing1: claawvga {
				clock-frequency = <27000000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <40>;
				hfront-porch = <60>;
				vback-porch = <10>;
				vfront-porch = <10>;
				hsync-len = <20>;
				vsync-len = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		power {
			label = "Power Button";
			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
			linux,code = <116>; /* KEY_POWER */
			gpio-key,wakeup;
		};
	};

	sound {
		compatible = "fsl,imx51-babbage-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx51-babbage-sgtl5000";
		ssi-controller = <&ssi2>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <2>;
		mux-ext-port = <3>;
	};

	clocks {
		ckih1 {
			clock-frequency = <22579200>;
		};

		clk_26M: codec_clock {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <26000000>;
			gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
		};
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	fsl,cd-controller;
	fsl,wp-controller;
	status = "okay";
};

&esdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc2>;
	cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	fsl,spi-num-chipselects = <2>;
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
		   <&gpio4 25 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pmic: mc13892@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mc13892";
		spi-max-frequency = <6000000>;
		spi-cs-high;
		reg = <0>;
		interrupt-parent = <&gpio1>;
		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

		regulators {
			sw1_reg: sw1 {
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1375000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vpll_reg: vpll {
				regulator-min-microvolt = <1050000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vdig_reg: vdig {
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
			};

			vsd_reg: vsd {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3150000>;
			};

			vusb2_reg: vusb2 {
				regulator-min-microvolt = <2400000>;
				regulator-max-microvolt = <2775000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vvideo_reg: vvideo {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
			};

			vaudio_reg: vaudio {
				regulator-min-microvolt = <2300000>;
				regulator-max-microvolt = <3000000>;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3000000>;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2900000>;
				regulator-always-on;
			};
		};
	};

	flash: at45db321d@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
		spi-max-frequency = <25000000>;
		reg = <1>;

		partition@0 {
			label = "U-Boot";
			reg = <0x0 0x40000>;
			read-only;
		};

		partition@40000 {
			label = "Kernel";
			reg = <0x40000 0x3c0000>;
		};
	};
};

&ssi2 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx51-babbage {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX51_PAD_GPIO1_0__SD1_CD     0x20d5
				MX51_PAD_GPIO1_1__SD1_WP     0x20d5
				MX51_PAD_GPIO1_5__GPIO1_5    0x100
				MX51_PAD_GPIO1_6__GPIO1_6    0x100
				MX51_PAD_EIM_A27__GPIO2_21   0x5
				MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
				MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
				MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
			>;
		};

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX51_PAD_AUD3_BB_TXD__AUD3_TXD		0x80000000
				MX51_PAD_AUD3_BB_RXD__AUD3_RXD		0x80000000
				MX51_PAD_AUD3_BB_CK__AUD3_TXC		0x80000000
				MX51_PAD_AUD3_BB_FS__AUD3_TXFS		0x80000000
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
				MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
				MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
				MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
				MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
				MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
			>;
		};

		pinctrl_esdhc2: esdhc2grp {
			fsl,pins = <
				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX51_PAD_EIM_EB2__FEC_MDIO		0x80000000
				MX51_PAD_EIM_EB3__FEC_RDATA1		0x80000000
				MX51_PAD_EIM_CS2__FEC_RDATA2		0x80000000
				MX51_PAD_EIM_CS3__FEC_RDATA3		0x80000000
				MX51_PAD_EIM_CS4__FEC_RX_ER		0x80000000
				MX51_PAD_EIM_CS5__FEC_CRS		0x80000000
				MX51_PAD_NANDF_RB2__FEC_COL		0x80000000
				MX51_PAD_NANDF_RB3__FEC_RX_CLK		0x80000000
				MX51_PAD_NANDF_D9__FEC_RDATA0		0x80000000
				MX51_PAD_NANDF_D8__FEC_TDATA0		0x80000000
				MX51_PAD_NANDF_CS2__FEC_TX_ER		0x80000000
				MX51_PAD_NANDF_CS3__FEC_MDC		0x80000000
				MX51_PAD_NANDF_CS4__FEC_TDATA1		0x80000000
				MX51_PAD_NANDF_CS5__FEC_TDATA2		0x80000000
				MX51_PAD_NANDF_CS6__FEC_TDATA3		0x80000000
				MX51_PAD_NANDF_CS7__FEC_TX_EN		0x80000000
				MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	0x80000000
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX51_PAD_KEY_COL4__I2C2_SCL		0x400001ed
				MX51_PAD_KEY_COL5__I2C2_SDA		0x400001ed
			>;
		};

		pinctrl_ipu_disp1: ipudisp1grp {
			fsl,pins = <
				MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
				MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
				MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
				MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
				MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
				MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
				MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
				MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
				MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
				MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
				MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
				MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
				MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
				MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
				MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
				MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
				MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
				MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
				MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
				MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
				MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
				MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
				MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
				MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
				MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
				MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
			>;
		};

		pinctrl_ipu_disp2: ipudisp2grp {
			fsl,pins = <
				MX51_PAD_DISP2_DAT0__DISP2_DAT0		0x5
				MX51_PAD_DISP2_DAT1__DISP2_DAT1		0x5
				MX51_PAD_DISP2_DAT2__DISP2_DAT2		0x5
				MX51_PAD_DISP2_DAT3__DISP2_DAT3		0x5
				MX51_PAD_DISP2_DAT4__DISP2_DAT4		0x5
				MX51_PAD_DISP2_DAT5__DISP2_DAT5		0x5
				MX51_PAD_DISP2_DAT6__DISP2_DAT6		0x5
				MX51_PAD_DISP2_DAT7__DISP2_DAT7		0x5
				MX51_PAD_DISP2_DAT8__DISP2_DAT8		0x5
				MX51_PAD_DISP2_DAT9__DISP2_DAT9		0x5
				MX51_PAD_DISP2_DAT10__DISP2_DAT10	0x5
				MX51_PAD_DISP2_DAT11__DISP2_DAT11	0x5
				MX51_PAD_DISP2_DAT12__DISP2_DAT12	0x5
				MX51_PAD_DISP2_DAT13__DISP2_DAT13	0x5
				MX51_PAD_DISP2_DAT14__DISP2_DAT14	0x5
				MX51_PAD_DISP2_DAT15__DISP2_DAT15	0x5
				MX51_PAD_DI2_PIN2__DI2_PIN2		0x5
				MX51_PAD_DI2_PIN3__DI2_PIN3		0x5
				MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	0x5
				MX51_PAD_DI_GP4__DI2_PIN15		0x5
			>;
		};

		pinctrl_kpp: kppgrp {
			fsl,pins = <
				MX51_PAD_KEY_ROW0__KEY_ROW0		0xe0
				MX51_PAD_KEY_ROW1__KEY_ROW1		0xe0
				MX51_PAD_KEY_ROW2__KEY_ROW2		0xe0
				MX51_PAD_KEY_ROW3__KEY_ROW3		0xe0
				MX51_PAD_KEY_COL0__KEY_COL0		0xe8
				MX51_PAD_KEY_COL1__KEY_COL1		0xe8
				MX51_PAD_KEY_COL2__KEY_COL2		0xe8
				MX51_PAD_KEY_COL3__KEY_COL3		0xe8
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
				MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
				MX51_PAD_UART1_RTS__UART1_RTS		0x1c5
				MX51_PAD_UART1_CTS__UART1_CTS		0x1c5
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX51_PAD_UART2_RXD__UART2_RXD		0x1c5
				MX51_PAD_UART2_TXD__UART2_TXD		0x1c5
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX51_PAD_EIM_D25__UART3_RXD		0x1c5
				MX51_PAD_EIM_D26__UART3_TXD		0x1c5
				MX51_PAD_EIM_D27__UART3_RTS		0x1c5
				MX51_PAD_EIM_D24__UART3_CTS		0x1c5
			>;
		};
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	sgtl5000: codec@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clk_26M>;
		VDDA-supply = <&vdig_reg>;
		VDDIO-supply = <&vvideo_reg>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	status = "okay";
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	linux,keymap = <0x00000067	/* KEY_UP */
			0x0001006c	/* KEY_DOWN */
			0x00020072	/* KEY_VOLUMEDOWN */
			0x00030066	/* KEY_HOME */
			0x0100006a	/* KEY_RIGHT */
			0x01010069	/* KEY_LEFT */
			0x0102001c	/* KEY_ENTER */
			0x01030073	/* KEY_VOLUMEUP */
			0x02000040	/* KEY_F6 */
			0x02010042	/* KEY_F8 */
			0x02020043	/* KEY_F9 */
			0x02030044	/* KEY_F10 */
			0x0300003b	/* KEY_F1 */
			0x0301003c	/* KEY_F2 */
			0x0302003d	/* KEY_F3 */
			0x03030074>;	/* KEY_POWER */
	status = "okay";
};
Commit	Line	Data
9daaf31a SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/dts-v1/;
36dffd8f	14	#include "imx51.dtsi"
9daaf31a SG	15
	16	/ {
	17	model = "Freescale i.MX51 Babbage Board";
	18	compatible = "fsl,imx51-babbage", "fsl,imx51";
	19
9daaf31a SG	20	memory {
	21	reg = <0x90000000 0x20000000>;
	22	};
	23
be4ccfce SG	24	display@di0 {
	25	compatible = "fsl,imx-parallel-display";
	26	crtcs = <&ipu 0>;
	27	interface-pix-fmt = "rgb24";
	28	pinctrl-names = "default";
5a2a7d57	29	pinctrl-0 = <&pinctrl_ipu_disp1>;
493a8636 FE	30	display-timings {
	31	native-mode = <&timing0>;
	32	timing0: dvi {
	33	clock-frequency = <65000000>;
	34	hactive = <1024>;
	35	vactive = <768>;
	36	hback-porch = <220>;
	37	hfront-porch = <40>;
	38	vback-porch = <21>;
	39	vfront-porch = <7>;
	40	hsync-len = <60>;
	41	vsync-len = <10>;
	42	};
	43	};
be4ccfce	44	};
a15d9f89	45
be4ccfce SG	46	display@di1 {
	47	compatible = "fsl,imx-parallel-display";
	48	crtcs = <&ipu 1>;
	49	interface-pix-fmt = "rgb565";
	50	pinctrl-names = "default";
5a2a7d57	51	pinctrl-0 = <&pinctrl_ipu_disp2>;
493a8636 FE	52	status = "disabled";
	53	display-timings {
	54	native-mode = <&timing1>;
	55	timing1: claawvga {
	56	clock-frequency = <27000000>;
	57	hactive = <800>;
	58	vactive = <480>;
	59	hback-porch = <40>;
	60	hfront-porch = <60>;
	61	vback-porch = <10>;
	62	vfront-porch = <10>;
	63	hsync-len = <20>;
	64	vsync-len = <10>;
	65	hsync-active = <0>;
	66	vsync-active = <0>;
	67	de-active = <1>;
	68	pixelclk-active = <0>;
	69	};
	70	};
9daaf31a SG	71	};
	72
	73	gpio-keys {
	74	compatible = "gpio-keys";
	75
	76	power {
	77	label = "Power Button";
bdb3eec7	78	gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
9daaf31a SG	79	linux,code = <116>; /* KEY_POWER */
	80	gpio-key,wakeup;
	81	};
	82	};
a15d9f89 SG	83
	84	sound {
	85	compatible = "fsl,imx51-babbage-sgtl5000",
	86	"fsl,imx-audio-sgtl5000";
	87	model = "imx51-babbage-sgtl5000";
	88	ssi-controller = <&ssi2>;
	89	audio-codec = <&sgtl5000>;
	90	audio-routing =
	91	"MIC_IN", "Mic Jack",
	92	"Mic Jack", "Mic Bias",
	93	"Headphone Jack", "HP_OUT";
	94	mux-int-port = <2>;
	95	mux-ext-port = <3>;
	96	};
84bb0847 FE	97
84bb0847 FE	98	clocks {
677e28b1 AS	99	ckih1 {
	100	clock-frequency = <22579200>;
	101	};
	102
84bb0847 FE	103	clk_26M: codec_clock {
	104	compatible = "fixed-clock";
	105	reg=<0>;
	106	#clock-cells = <0>;
	107	clock-frequency = <26000000>;
bdb3eec7	108	gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
84bb0847 FE	109	};
84bb0847 FE	110	};
9daaf31a	111	};
be4ccfce SG	112
	113	&esdhc1 {
	114	pinctrl-names = "default";
5a2a7d57	115	pinctrl-0 = <&pinctrl_esdhc1>;
be4ccfce SG	116	fsl,cd-controller;
	117	fsl,wp-controller;
	118	status = "okay";
	119	};
	120
	121	&esdhc2 {
	122	pinctrl-names = "default";
5a2a7d57	123	pinctrl-0 = <&pinctrl_esdhc2>;
bdb3eec7 AS	124	cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
bdb3eec7 AS	125	wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
be4ccfce SG	126	status = "okay";
	127	};
	128
	129	&uart3 {
	130	pinctrl-names = "default";
5a2a7d57	131	pinctrl-0 = <&pinctrl_uart3>;
be4ccfce SG	132	fsl,uart-has-rtscts;
	133	status = "okay";
	134	};
	135
	136	&ecspi1 {
	137	pinctrl-names = "default";
5a2a7d57	138	pinctrl-0 = <&pinctrl_ecspi1>;
be4ccfce	139	fsl,spi-num-chipselects = <2>;
bdb3eec7 AS	140	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
bdb3eec7 AS	141	<&gpio4 25 GPIO_ACTIVE_HIGH>;
be4ccfce SG	142	status = "okay";
	143
	144	pmic: mc13892@0 {
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147	compatible = "fsl,mc13892";
	148	spi-max-frequency = <6000000>;
dc071436	149	spi-cs-high;
be4ccfce SG	150	reg = <0>;
be4ccfce SG	151	interrupt-parent = <&gpio1>;
1cbb74fd	152	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
be4ccfce SG	153
	154	regulators {
	155	sw1_reg: sw1 {
	156	regulator-min-microvolt = <600000>;
	157	regulator-max-microvolt = <1375000>;
	158	regulator-boot-on;
	159	regulator-always-on;
	160	};
	161
	162	sw2_reg: sw2 {
	163	regulator-min-microvolt = <900000>;
	164	regulator-max-microvolt = <1850000>;
	165	regulator-boot-on;
	166	regulator-always-on;
	167	};
	168
	169	sw3_reg: sw3 {
	170	regulator-min-microvolt = <1100000>;
	171	regulator-max-microvolt = <1850000>;
	172	regulator-boot-on;
	173	regulator-always-on;
	174	};
	175
	176	sw4_reg: sw4 {
	177	regulator-min-microvolt = <1100000>;
	178	regulator-max-microvolt = <1850000>;
	179	regulator-boot-on;
	180	regulator-always-on;
	181	};
	182
	183	vpll_reg: vpll {
	184	regulator-min-microvolt = <1050000>;
	185	regulator-max-microvolt = <1800000>;
	186	regulator-boot-on;
	187	regulator-always-on;
	188	};
	189
	190	vdig_reg: vdig {
	191	regulator-min-microvolt = <1650000>;
	192	regulator-max-microvolt = <1650000>;
	193	regulator-boot-on;
	194	};
	195
	196	vsd_reg: vsd {
	197	regulator-min-microvolt = <1800000>;
	198	regulator-max-microvolt = <3150000>;
	199	};
	200
	201	vusb2_reg: vusb2 {
	202	regulator-min-microvolt = <2400000>;
	203	regulator-max-microvolt = <2775000>;
	204	regulator-boot-on;
	205	regulator-always-on;
	206	};
	207
	208	vvideo_reg: vvideo {
	209	regulator-min-microvolt = <2775000>;
	210	regulator-max-microvolt = <2775000>;
	211	};
	212
	213	vaudio_reg: vaudio {
	214	regulator-min-microvolt = <2300000>;
	215	regulator-max-microvolt = <3000000>;
	216	};
217
218	vcam_reg: vcam {
219	regulator-min-microvolt = <2500000>;
220	regulator-max-microvolt = <3000000>;
221	};
222
223	vgen1_reg: vgen1 {
224	regulator-min-microvolt = <1200000>;
225	regulator-max-microvolt = <1200000>;
226	};
227
228	vgen2_reg: vgen2 {
229	regulator-min-microvolt = <1200000>;
230	regulator-max-microvolt = <3150000>;
231	regulator-always-on;
232	};
233
234	vgen3_reg: vgen3 {
235	regulator-min-microvolt = <1800000>;
236	regulator-max-microvolt = <2900000>;
237	regulator-always-on;
238	};
239	};
240	};
241
242	flash: at45db321d@1 {
243	#address-cells = <1>;
244	#size-cells = <1>;
245	compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
246	spi-max-frequency = <25000000>;
247	reg = <1>;
248
249	partition@0 {
250	label = "U-Boot";
251	reg = <0x0 0x40000>;
252	read-only;
253	};
254
255	partition@40000 {
256	label = "Kernel";
257	reg = <0x40000 0x3c0000>;
258	};
259	};
260	};
261
262	&ssi2 {
263	fsl,mode = "i2s-slave";
264	status = "okay";
265	};
266
267	&iomuxc {
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_hog>;
270
5a2a7d57	271	imx51-babbage {
be4ccfce SG	272	pinctrl_hog: hoggrp {
be4ccfce SG	273	fsl,pins = <
e1641531 SG	274	MX51_PAD_GPIO1_0__SD1_CD 0x20d5
	275	MX51_PAD_GPIO1_1__SD1_WP 0x20d5
	276	MX51_PAD_GPIO1_5__GPIO1_5 0x100
	277	MX51_PAD_GPIO1_6__GPIO1_6 0x100
	278	MX51_PAD_EIM_A27__GPIO2_21 0x5
	279	MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
	280	MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
84bb0847	281	MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
be4ccfce SG	282	>;
be4ccfce SG	283	};
5a2a7d57 SG	284
	285	pinctrl_audmux: audmuxgrp {
	286	fsl,pins = <
	287	MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
	288	MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
	289	MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
	290	MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
	291	>;
	292	};
	293
	294	pinctrl_ecspi1: ecspi1grp {
	295	fsl,pins = <
	296	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	297	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	298	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
	299	>;
	300	};
	301
	302	pinctrl_esdhc1: esdhc1grp {
	303	fsl,pins = <
	304	MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
	305	MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
	306	MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
	307	MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
	308	MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
	309	MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
	310	>;
	311	};
	312
	313	pinctrl_esdhc2: esdhc2grp {
	314	fsl,pins = <
	315	MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
	316	MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
	317	MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
	318	MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
	319	MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
	320	MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
	321	>;
	322	};
	323
	324	pinctrl_fec: fecgrp {
	325	fsl,pins = <
	326	MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
	327	MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
	328	MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
	329	MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
	330	MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
	331	MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
	332	MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
	333	MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
	334	MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
	335	MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
	336	MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
	337	MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
	338	MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
	339	MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
	340	MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
	341	MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
	342	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
	343	>;
	344	};
	345
	346	pinctrl_i2c2: i2c2grp {
	347	fsl,pins = <
348	MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
349	MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
350	>;
351	};
352
353	pinctrl_ipu_disp1: ipudisp1grp {
354	fsl,pins = <
355	MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
356	MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
357	MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
358	MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
359	MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
360	MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
361	MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
362	MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
363	MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
364	MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
365	MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
366	MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
367	MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
368	MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
369	MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
370	MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
371	MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
372	MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
373	MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
374	MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
375	MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
376	MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
377	MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
378	MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
379	MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
380	MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
381	>;
382	};
383
384	pinctrl_ipu_disp2: ipudisp2grp {
385	fsl,pins = <
386	MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
387	MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
388	MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
389	MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
390	MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
391	MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
392	MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
393	MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
394	MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
395	MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
396	MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
397	MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
398	MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
399	MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
400	MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
401	MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
402	MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
403	MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
404	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
405	MX51_PAD_DI_GP4__DI2_PIN15 0x5
406	>;
407	};
408
409	pinctrl_kpp: kppgrp {
410	fsl,pins = <
411	MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
412	MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
413	MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
414	MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
415	MX51_PAD_KEY_COL0__KEY_COL0 0xe8
416	MX51_PAD_KEY_COL1__KEY_COL1 0xe8
417	MX51_PAD_KEY_COL2__KEY_COL2 0xe8
418	MX51_PAD_KEY_COL3__KEY_COL3 0xe8
419	>;
420	};
421
422	pinctrl_uart1: uart1grp {
423	fsl,pins = <
424	MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
425	MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
426	MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
427	MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
428	>;
429	};
430
431	pinctrl_uart2: uart2grp {
432	fsl,pins = <
433	MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
434	MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
435	>;
436	};
437
438	pinctrl_uart3: uart3grp {
439	fsl,pins = <
440	MX51_PAD_EIM_D25__UART3_RXD 0x1c5
441	MX51_PAD_EIM_D26__UART3_TXD 0x1c5
442	MX51_PAD_EIM_D27__UART3_RTS 0x1c5
443	MX51_PAD_EIM_D24__UART3_CTS 0x1c5
444	>;
445	};
be4ccfce SG	446	};
	447	};
	448
	449	&uart1 {
	450	pinctrl-names = "default";
5a2a7d57	451	pinctrl-0 = <&pinctrl_uart1>;
be4ccfce SG	452	fsl,uart-has-rtscts;
	453	status = "okay";
	454	};
	455
	456	&uart2 {
	457	pinctrl-names = "default";
5a2a7d57	458	pinctrl-0 = <&pinctrl_uart2>;
be4ccfce SG	459	status = "okay";
	460	};
	461
	462	&i2c2 {
	463	pinctrl-names = "default";
5a2a7d57	464	pinctrl-0 = <&pinctrl_i2c2>;
be4ccfce SG	465	status = "okay";
	466
	467	sgtl5000: codec@0a {
	468	compatible = "fsl,sgtl5000";
	469	reg = <0x0a>;
84bb0847	470	clocks = <&clk_26M>;
be4ccfce SG	471	VDDA-supply = <&vdig_reg>;
	472	VDDIO-supply = <&vvideo_reg>;
	473	};
	474	};
	475
	476	&audmux {
	477	pinctrl-names = "default";
5a2a7d57	478	pinctrl-0 = <&pinctrl_audmux>;
be4ccfce SG	479	status = "okay";
	480	};
	481
	482	&fec {
	483	pinctrl-names = "default";
5a2a7d57	484	pinctrl-0 = <&pinctrl_fec>;
be4ccfce SG	485	phy-mode = "mii";
	486	status = "okay";
	487	};
67eb7c0b LY	488
	489	&kpp {
	490	pinctrl-names = "default";
5a2a7d57	491	pinctrl-0 = <&pinctrl_kpp>;
67eb7c0b LY	492	linux,keymap = <0x00000067 /* KEY_UP */
	493	0x0001006c /* KEY_DOWN */
	494	0x00020072 /* KEY_VOLUMEDOWN */
	495	0x00030066 /* KEY_HOME */
	496	0x0100006a /* KEY_RIGHT */
	497	0x01010069 /* KEY_LEFT */
	498	0x0102001c /* KEY_ENTER */
	499	0x01030073 /* KEY_VOLUMEUP */
	500	0x02000040 /* KEY_F6 */
	501	0x02010042 /* KEY_F8 */
	502	0x02020043 /* KEY_F9 */
	503	0x02030044 /* KEY_F10 */
	504	0x0300003b /* KEY_F1 */
	505	0x0301003c /* KEY_F2 */
	506	0x0302003d /* KEY_F3 */
	507	0x03030074>; /* KEY_POWER */
	508	status = "okay";
	509	};