Commit | Line | Data |
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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
36dffd8f | 14 | #include "imx51.dtsi" |
9daaf31a SG |
15 | |
16 | / { | |
17 | model = "Freescale i.MX51 Babbage Board"; | |
18 | compatible = "fsl,imx51-babbage", "fsl,imx51"; | |
19 | ||
48f51963 SH |
20 | chosen { |
21 | stdout-path = &uart1; | |
22 | }; | |
23 | ||
9daaf31a SG |
24 | memory { |
25 | reg = <0x90000000 0x20000000>; | |
26 | }; | |
27 | ||
1c0daab7 AS |
28 | clocks { |
29 | ckih1 { | |
30 | clock-frequency = <22579200>; | |
31 | }; | |
32 | ||
33 | clk_26M: codec_clock { | |
34 | compatible = "fixed-clock"; | |
35 | reg=<0>; | |
36 | #clock-cells = <0>; | |
37 | clock-frequency = <26000000>; | |
38 | gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; | |
39 | }; | |
40 | }; | |
41 | ||
17b5001b | 42 | display0: display@di0 { |
be4ccfce | 43 | compatible = "fsl,imx-parallel-display"; |
be4ccfce SG |
44 | interface-pix-fmt = "rgb24"; |
45 | pinctrl-names = "default"; | |
5a2a7d57 | 46 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
493a8636 FE |
47 | display-timings { |
48 | native-mode = <&timing0>; | |
49 | timing0: dvi { | |
50 | clock-frequency = <65000000>; | |
51 | hactive = <1024>; | |
52 | vactive = <768>; | |
53 | hback-porch = <220>; | |
54 | hfront-porch = <40>; | |
55 | vback-porch = <21>; | |
56 | vfront-porch = <7>; | |
57 | hsync-len = <60>; | |
58 | vsync-len = <10>; | |
59 | }; | |
60 | }; | |
de10e04e PZ |
61 | |
62 | port { | |
63 | display0_in: endpoint { | |
64 | remote-endpoint = <&ipu_di0_disp0>; | |
65 | }; | |
66 | }; | |
be4ccfce | 67 | }; |
a15d9f89 | 68 | |
17b5001b | 69 | display1: display@di1 { |
be4ccfce | 70 | compatible = "fsl,imx-parallel-display"; |
be4ccfce SG |
71 | interface-pix-fmt = "rgb565"; |
72 | pinctrl-names = "default"; | |
5a2a7d57 | 73 | pinctrl-0 = <&pinctrl_ipu_disp2>; |
493a8636 FE |
74 | status = "disabled"; |
75 | display-timings { | |
76 | native-mode = <&timing1>; | |
77 | timing1: claawvga { | |
78 | clock-frequency = <27000000>; | |
79 | hactive = <800>; | |
80 | vactive = <480>; | |
81 | hback-porch = <40>; | |
82 | hfront-porch = <60>; | |
83 | vback-porch = <10>; | |
84 | vfront-porch = <10>; | |
85 | hsync-len = <20>; | |
86 | vsync-len = <10>; | |
87 | hsync-active = <0>; | |
88 | vsync-active = <0>; | |
89 | de-active = <1>; | |
90 | pixelclk-active = <0>; | |
91 | }; | |
92 | }; | |
de10e04e PZ |
93 | |
94 | port { | |
95 | display1_in: endpoint { | |
96 | remote-endpoint = <&ipu_di1_disp1>; | |
97 | }; | |
98 | }; | |
9daaf31a SG |
99 | }; |
100 | ||
101 | gpio-keys { | |
102 | compatible = "gpio-keys"; | |
2ccc447c AS |
103 | pinctrl-names = "default"; |
104 | pinctrl-0 = <&pinctrl_gpio_keys>; | |
9daaf31a SG |
105 | |
106 | power { | |
107 | label = "Power Button"; | |
bdb3eec7 | 108 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; |
02134e77 | 109 | linux,code = <KEY_POWER>; |
9daaf31a SG |
110 | gpio-key,wakeup; |
111 | }; | |
112 | }; | |
a15d9f89 | 113 | |
a198af23 LY |
114 | leds { |
115 | compatible = "gpio-leds"; | |
116 | pinctrl-names = "default"; | |
117 | pinctrl-0 = <&pinctrl_gpio_leds>; | |
118 | ||
119 | led-diagnostic { | |
120 | label = "diagnostic"; | |
121 | gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; | |
122 | }; | |
123 | }; | |
124 | ||
9bf206a9 FE |
125 | regulators { |
126 | compatible = "simple-bus"; | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | ||
db8235ec | 130 | reg_usbh1_vbus: regulator@0 { |
9bf206a9 | 131 | compatible = "regulator-fixed"; |
2ccc447c | 132 | pinctrl-names = "default"; |
db8235ec | 133 | pinctrl-0 = <&pinctrl_usbh1reg>; |
9bf206a9 | 134 | reg = <0>; |
db8235ec | 135 | regulator-name = "usbh1_vbus"; |
9bf206a9 FE |
136 | regulator-min-microvolt = <5000000>; |
137 | regulator-max-microvolt = <5000000>; | |
2ccc447c | 138 | gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
9bf206a9 FE |
139 | enable-active-high; |
140 | }; | |
db8235ec AS |
141 | |
142 | reg_usbotg_vbus: regulator@1 { | |
143 | compatible = "regulator-fixed"; | |
144 | pinctrl-names = "default"; | |
145 | pinctrl-0 = <&pinctrl_usbotgreg>; | |
146 | reg = <1>; | |
147 | regulator-name = "usbotg_vbus"; | |
148 | regulator-min-microvolt = <5000000>; | |
149 | regulator-max-microvolt = <5000000>; | |
150 | gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
151 | enable-active-high; | |
152 | }; | |
9bf206a9 FE |
153 | }; |
154 | ||
1c0daab7 AS |
155 | sound { |
156 | compatible = "fsl,imx51-babbage-sgtl5000", | |
157 | "fsl,imx-audio-sgtl5000"; | |
158 | model = "imx51-babbage-sgtl5000"; | |
159 | ssi-controller = <&ssi2>; | |
160 | audio-codec = <&sgtl5000>; | |
161 | audio-routing = | |
162 | "MIC_IN", "Mic Jack", | |
163 | "Mic Jack", "Mic Bias", | |
164 | "Headphone Jack", "HP_OUT"; | |
165 | mux-int-port = <2>; | |
166 | mux-ext-port = <3>; | |
167 | }; | |
168 | ||
9bf206a9 FE |
169 | usbphy { |
170 | #address-cells = <1>; | |
171 | #size-cells = <0>; | |
172 | compatible = "simple-bus"; | |
173 | ||
174 | usbh1phy: usbh1phy@0 { | |
175 | compatible = "usb-nop-xceiv"; | |
176 | reg = <0>; | |
6b273284 | 177 | clocks = <&clks IMX5_CLK_DUMMY>; |
9bf206a9 FE |
178 | clock-names = "main_clk"; |
179 | }; | |
180 | }; | |
9daaf31a | 181 | }; |
be4ccfce | 182 | |
1c0daab7 | 183 | &audmux { |
be4ccfce | 184 | pinctrl-names = "default"; |
1c0daab7 | 185 | pinctrl-0 = <&pinctrl_audmux>; |
be4ccfce SG |
186 | status = "okay"; |
187 | }; | |
188 | ||
189 | &ecspi1 { | |
190 | pinctrl-names = "default"; | |
5a2a7d57 | 191 | pinctrl-0 = <&pinctrl_ecspi1>; |
be4ccfce | 192 | fsl,spi-num-chipselects = <2>; |
bdb3eec7 | 193 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, |
d2176f29 | 194 | <&gpio4 25 GPIO_ACTIVE_LOW>; |
be4ccfce SG |
195 | status = "okay"; |
196 | ||
197 | pmic: mc13892@0 { | |
be4ccfce | 198 | compatible = "fsl,mc13892"; |
1ddcff4b AS |
199 | pinctrl-names = "default"; |
200 | pinctrl-0 = <&pinctrl_pmic>; | |
be4ccfce | 201 | spi-max-frequency = <6000000>; |
dc071436 | 202 | spi-cs-high; |
be4ccfce SG |
203 | reg = <0>; |
204 | interrupt-parent = <&gpio1>; | |
1cbb74fd | 205 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
f4511417 | 206 | fsl,mc13xxx-uses-rtc; |
be4ccfce SG |
207 | |
208 | regulators { | |
209 | sw1_reg: sw1 { | |
210 | regulator-min-microvolt = <600000>; | |
211 | regulator-max-microvolt = <1375000>; | |
212 | regulator-boot-on; | |
213 | regulator-always-on; | |
214 | }; | |
215 | ||
216 | sw2_reg: sw2 { | |
217 | regulator-min-microvolt = <900000>; | |
218 | regulator-max-microvolt = <1850000>; | |
219 | regulator-boot-on; | |
220 | regulator-always-on; | |
221 | }; | |
222 | ||
223 | sw3_reg: sw3 { | |
224 | regulator-min-microvolt = <1100000>; | |
225 | regulator-max-microvolt = <1850000>; | |
226 | regulator-boot-on; | |
227 | regulator-always-on; | |
228 | }; | |
229 | ||
230 | sw4_reg: sw4 { | |
231 | regulator-min-microvolt = <1100000>; | |
232 | regulator-max-microvolt = <1850000>; | |
233 | regulator-boot-on; | |
234 | regulator-always-on; | |
235 | }; | |
236 | ||
237 | vpll_reg: vpll { | |
238 | regulator-min-microvolt = <1050000>; | |
239 | regulator-max-microvolt = <1800000>; | |
240 | regulator-boot-on; | |
241 | regulator-always-on; | |
242 | }; | |
243 | ||
244 | vdig_reg: vdig { | |
245 | regulator-min-microvolt = <1650000>; | |
246 | regulator-max-microvolt = <1650000>; | |
247 | regulator-boot-on; | |
248 | }; | |
249 | ||
250 | vsd_reg: vsd { | |
251 | regulator-min-microvolt = <1800000>; | |
252 | regulator-max-microvolt = <3150000>; | |
253 | }; | |
254 | ||
255 | vusb2_reg: vusb2 { | |
256 | regulator-min-microvolt = <2400000>; | |
257 | regulator-max-microvolt = <2775000>; | |
258 | regulator-boot-on; | |
259 | regulator-always-on; | |
260 | }; | |
261 | ||
262 | vvideo_reg: vvideo { | |
263 | regulator-min-microvolt = <2775000>; | |
264 | regulator-max-microvolt = <2775000>; | |
265 | }; | |
266 | ||
267 | vaudio_reg: vaudio { | |
268 | regulator-min-microvolt = <2300000>; | |
269 | regulator-max-microvolt = <3000000>; | |
270 | }; | |
271 | ||
272 | vcam_reg: vcam { | |
273 | regulator-min-microvolt = <2500000>; | |
274 | regulator-max-microvolt = <3000000>; | |
275 | }; | |
276 | ||
277 | vgen1_reg: vgen1 { | |
278 | regulator-min-microvolt = <1200000>; | |
279 | regulator-max-microvolt = <1200000>; | |
280 | }; | |
281 | ||
282 | vgen2_reg: vgen2 { | |
283 | regulator-min-microvolt = <1200000>; | |
284 | regulator-max-microvolt = <3150000>; | |
285 | regulator-always-on; | |
286 | }; | |
287 | ||
288 | vgen3_reg: vgen3 { | |
289 | regulator-min-microvolt = <1800000>; | |
290 | regulator-max-microvolt = <2900000>; | |
291 | regulator-always-on; | |
292 | }; | |
293 | }; | |
294 | }; | |
295 | ||
296 | flash: at45db321d@1 { | |
297 | #address-cells = <1>; | |
298 | #size-cells = <1>; | |
299 | compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; | |
300 | spi-max-frequency = <25000000>; | |
301 | reg = <1>; | |
302 | ||
303 | partition@0 { | |
304 | label = "U-Boot"; | |
305 | reg = <0x0 0x40000>; | |
306 | read-only; | |
307 | }; | |
308 | ||
309 | partition@40000 { | |
310 | label = "Kernel"; | |
311 | reg = <0x40000 0x3c0000>; | |
312 | }; | |
313 | }; | |
314 | }; | |
315 | ||
1c0daab7 AS |
316 | &esdhc1 { |
317 | pinctrl-names = "default"; | |
318 | pinctrl-0 = <&pinctrl_esdhc1>; | |
dacf4922 SH |
319 | cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; |
320 | wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; | |
1c0daab7 AS |
321 | status = "okay"; |
322 | }; | |
323 | ||
324 | &esdhc2 { | |
325 | pinctrl-names = "default"; | |
326 | pinctrl-0 = <&pinctrl_esdhc2>; | |
dacf4922 | 327 | cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; |
1c0daab7 AS |
328 | wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
329 | status = "okay"; | |
330 | }; | |
331 | ||
332 | &fec { | |
333 | pinctrl-names = "default"; | |
334 | pinctrl-0 = <&pinctrl_fec>; | |
335 | phy-mode = "mii"; | |
336 | phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; | |
337 | phy-reset-duration = <1>; | |
338 | status = "okay"; | |
339 | }; | |
340 | ||
dd0c672a AS |
341 | &i2c1 { |
342 | pinctrl-names = "default"; | |
343 | pinctrl-0 = <&pinctrl_i2c1>; | |
344 | status = "okay"; | |
345 | }; | |
346 | ||
1c0daab7 AS |
347 | &i2c2 { |
348 | pinctrl-names = "default"; | |
349 | pinctrl-0 = <&pinctrl_i2c2>; | |
350 | status = "okay"; | |
351 | ||
352 | sgtl5000: codec@0a { | |
353 | compatible = "fsl,sgtl5000"; | |
354 | pinctrl-names = "default"; | |
355 | pinctrl-0 = <&pinctrl_clkcodec>; | |
356 | reg = <0x0a>; | |
357 | clocks = <&clk_26M>; | |
358 | VDDA-supply = <&vdig_reg>; | |
359 | VDDIO-supply = <&vvideo_reg>; | |
360 | }; | |
361 | }; | |
362 | ||
de10e04e PZ |
363 | &ipu_di0_disp0 { |
364 | remote-endpoint = <&display0_in>; | |
365 | }; | |
366 | ||
367 | &ipu_di1_disp1 { | |
368 | remote-endpoint = <&display1_in>; | |
369 | }; | |
370 | ||
1c0daab7 AS |
371 | &kpp { |
372 | pinctrl-names = "default"; | |
373 | pinctrl-0 = <&pinctrl_kpp>; | |
374 | linux,keymap = < | |
375 | MATRIX_KEY(0, 0, KEY_UP) | |
376 | MATRIX_KEY(0, 1, KEY_DOWN) | |
377 | MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) | |
378 | MATRIX_KEY(0, 3, KEY_HOME) | |
379 | MATRIX_KEY(1, 0, KEY_RIGHT) | |
380 | MATRIX_KEY(1, 1, KEY_LEFT) | |
381 | MATRIX_KEY(1, 2, KEY_ENTER) | |
382 | MATRIX_KEY(1, 3, KEY_VOLUMEUP) | |
383 | MATRIX_KEY(2, 0, KEY_F6) | |
384 | MATRIX_KEY(2, 1, KEY_F8) | |
385 | MATRIX_KEY(2, 2, KEY_F9) | |
386 | MATRIX_KEY(2, 3, KEY_F10) | |
387 | MATRIX_KEY(3, 0, KEY_F1) | |
388 | MATRIX_KEY(3, 1, KEY_F2) | |
389 | MATRIX_KEY(3, 2, KEY_F3) | |
390 | MATRIX_KEY(3, 3, KEY_POWER) | |
391 | >; | |
392 | status = "okay"; | |
393 | }; | |
394 | ||
be4ccfce | 395 | &ssi2 { |
be4ccfce SG |
396 | status = "okay"; |
397 | }; | |
398 | ||
1c0daab7 AS |
399 | &uart1 { |
400 | pinctrl-names = "default"; | |
401 | pinctrl-0 = <&pinctrl_uart1>; | |
402 | fsl,uart-has-rtscts; | |
403 | status = "okay"; | |
404 | }; | |
405 | ||
406 | &uart2 { | |
407 | pinctrl-names = "default"; | |
408 | pinctrl-0 = <&pinctrl_uart2>; | |
409 | status = "okay"; | |
410 | }; | |
411 | ||
412 | &uart3 { | |
413 | pinctrl-names = "default"; | |
414 | pinctrl-0 = <&pinctrl_uart3>; | |
415 | fsl,uart-has-rtscts; | |
416 | status = "okay"; | |
417 | }; | |
418 | ||
419 | &usbh1 { | |
420 | pinctrl-names = "default"; | |
421 | pinctrl-0 = <&pinctrl_usbh1>; | |
422 | vbus-supply = <®_usbh1_vbus>; | |
423 | fsl,usbphy = <&usbh1phy>; | |
424 | phy_type = "ulpi"; | |
425 | status = "okay"; | |
426 | }; | |
427 | ||
428 | &usbotg { | |
429 | dr_mode = "otg"; | |
430 | disable-over-current; | |
431 | phy_type = "utmi_wide"; | |
432 | vbus-supply = <®_usbotg_vbus>; | |
433 | status = "okay"; | |
434 | }; | |
435 | ||
be4ccfce | 436 | &iomuxc { |
5a2a7d57 | 437 | imx51-babbage { |
5a2a7d57 SG |
438 | pinctrl_audmux: audmuxgrp { |
439 | fsl,pins = < | |
440 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | |
441 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | |
442 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | |
443 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | |
444 | >; | |
445 | }; | |
446 | ||
2ccc447c AS |
447 | pinctrl_clkcodec: clkcodecgrp { |
448 | fsl,pins = < | |
449 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 | |
450 | >; | |
451 | }; | |
452 | ||
5a2a7d57 SG |
453 | pinctrl_ecspi1: ecspi1grp { |
454 | fsl,pins = < | |
455 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | |
456 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | |
457 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | |
2ccc447c AS |
458 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ |
459 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ | |
5a2a7d57 SG |
460 | >; |
461 | }; | |
462 | ||
463 | pinctrl_esdhc1: esdhc1grp { | |
464 | fsl,pins = < | |
465 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | |
466 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | |
467 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | |
468 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | |
469 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | |
470 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | |
dacf4922 SH |
471 | MX51_PAD_GPIO1_0__GPIO1_0 0x100 |
472 | MX51_PAD_GPIO1_1__GPIO1_1 0x100 | |
5a2a7d57 SG |
473 | >; |
474 | }; | |
475 | ||
476 | pinctrl_esdhc2: esdhc2grp { | |
477 | fsl,pins = < | |
478 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | |
479 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | |
480 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | |
481 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | |
482 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | |
483 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | |
2ccc447c AS |
484 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ |
485 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ | |
5a2a7d57 SG |
486 | >; |
487 | }; | |
488 | ||
489 | pinctrl_fec: fecgrp { | |
490 | fsl,pins = < | |
c73dbd71 SH |
491 | MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 |
492 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 | |
493 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 | |
494 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 | |
495 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 | |
496 | MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 | |
497 | MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 | |
498 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 | |
499 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 | |
500 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 | |
501 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 | |
502 | MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 | |
503 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 | |
504 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 | |
505 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 | |
506 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 | |
507 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 | |
508 | MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 | |
509 | MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ | |
5a2a7d57 SG |
510 | >; |
511 | }; | |
512 | ||
2ccc447c AS |
513 | pinctrl_gpio_keys: gpiokeysgrp { |
514 | fsl,pins = < | |
515 | MX51_PAD_EIM_A27__GPIO2_21 0x5 | |
516 | >; | |
517 | }; | |
518 | ||
a198af23 LY |
519 | pinctrl_gpio_leds: gpioledsgrp { |
520 | fsl,pins = < | |
521 | MX51_PAD_EIM_D22__GPIO2_6 0x80000000 | |
522 | >; | |
523 | }; | |
524 | ||
dd0c672a AS |
525 | pinctrl_i2c1: i2c1grp { |
526 | fsl,pins = < | |
527 | MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed | |
528 | MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed | |
529 | >; | |
530 | }; | |
531 | ||
5a2a7d57 SG |
532 | pinctrl_i2c2: i2c2grp { |
533 | fsl,pins = < | |
534 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | |
535 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | |
536 | >; | |
537 | }; | |
538 | ||
539 | pinctrl_ipu_disp1: ipudisp1grp { | |
540 | fsl,pins = < | |
541 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | |
542 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | |
543 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | |
544 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | |
545 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | |
546 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | |
547 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | |
548 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | |
549 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | |
550 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | |
551 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | |
552 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | |
553 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | |
554 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | |
555 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | |
556 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | |
557 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | |
558 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | |
559 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | |
560 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | |
561 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | |
562 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | |
563 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | |
564 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | |
565 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 | |
566 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 | |
567 | >; | |
568 | }; | |
569 | ||
570 | pinctrl_ipu_disp2: ipudisp2grp { | |
571 | fsl,pins = < | |
572 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | |
573 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | |
574 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | |
575 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | |
576 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | |
577 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | |
578 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | |
579 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | |
580 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | |
581 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | |
582 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | |
583 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | |
584 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | |
585 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | |
586 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | |
587 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | |
588 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 | |
589 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 | |
590 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | |
591 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | |
592 | >; | |
593 | }; | |
594 | ||
595 | pinctrl_kpp: kppgrp { | |
596 | fsl,pins = < | |
597 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | |
598 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | |
599 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | |
600 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | |
601 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | |
602 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | |
603 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | |
604 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | |
605 | >; | |
606 | }; | |
607 | ||
1ddcff4b AS |
608 | pinctrl_pmic: pmicgrp { |
609 | fsl,pins = < | |
610 | MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ | |
611 | >; | |
612 | }; | |
613 | ||
5a2a7d57 SG |
614 | pinctrl_uart1: uart1grp { |
615 | fsl,pins = < | |
616 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | |
617 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | |
618 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | |
619 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | |
620 | >; | |
621 | }; | |
622 | ||
623 | pinctrl_uart2: uart2grp { | |
624 | fsl,pins = < | |
625 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | |
626 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | |
627 | >; | |
628 | }; | |
629 | ||
630 | pinctrl_uart3: uart3grp { | |
631 | fsl,pins = < | |
632 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | |
633 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | |
634 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | |
635 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | |
636 | >; | |
637 | }; | |
9bf206a9 FE |
638 | |
639 | pinctrl_usbh1: usbh1grp { | |
640 | fsl,pins = < | |
641 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 | |
642 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 | |
643 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 | |
644 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 | |
645 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 | |
646 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 | |
647 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 | |
648 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 | |
649 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 | |
650 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 | |
651 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 | |
2ccc447c AS |
652 | >; |
653 | }; | |
654 | ||
db8235ec | 655 | pinctrl_usbh1reg: usbh1reggrp { |
2ccc447c AS |
656 | fsl,pins = < |
657 | MX51_PAD_EIM_D21__GPIO2_5 0x85 | |
9bf206a9 FE |
658 | >; |
659 | }; | |
db8235ec AS |
660 | |
661 | pinctrl_usbotgreg: usbotgreggrp { | |
662 | fsl,pins = < | |
663 | MX51_PAD_GPIO1_7__GPIO1_7 0x85 | |
664 | >; | |
665 | }; | |
be4ccfce SG |
666 | }; |
667 | }; |