[deliverable/linux.git] / arch / arm / boot / dts / imx51-babbage.dts

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx51.dtsi"

/ {
	model = "Freescale i.MX51 Babbage Board";
	compatible = "fsl,imx51-babbage", "fsl,imx51";

	memory {
		reg = <0x90000000 0x20000000>;
	};

	clocks {
		ckih1 {
			clock-frequency = <22579200>;
		};

		clk_26M: codec_clock {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <26000000>;
			gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
		};
	};

	display0: display@di0 {
		compatible = "fsl,imx-parallel-display";
		interface-pix-fmt = "rgb24";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_disp1>;
		display-timings {
			native-mode = <&timing0>;
			timing0: dvi {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};

		port {
			display0_in: endpoint {
				remote-endpoint = <&ipu_di0_disp0>;
			};
		};
	};

	display1: display@di1 {
		compatible = "fsl,imx-parallel-display";
		interface-pix-fmt = "rgb565";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_disp2>;
		status = "disabled";
		display-timings {
			native-mode = <&timing1>;
			timing1: claawvga {
				clock-frequency = <27000000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <40>;
				hfront-porch = <60>;
				vback-porch = <10>;
				vfront-porch = <10>;
				hsync-len = <20>;
				vsync-len = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};

		port {
			display1_in: endpoint {
				remote-endpoint = <&ipu_di1_disp1>;
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		power {
			label = "Power Button";
			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_POWER>;
			gpio-key,wakeup;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-diagnostic {
			label = "diagnostic";
			gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usbh1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usbh1reg>;
			reg = <0>;
			regulator-name = "usbh1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usbotg_vbus: regulator@1 {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usbotgreg>;
			reg = <1>;
			regulator-name = "usbotg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};

	sound {
		compatible = "fsl,imx51-babbage-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx51-babbage-sgtl5000";
		ssi-controller = <&ssi2>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <2>;
		mux-ext-port = <3>;
	};

	usbphy {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "simple-bus";

		usbh1phy: usbh1phy@0 {
			compatible = "usb-nop-xceiv";
			reg = <0>;
			clocks = <&clks 0>;
			clock-names = "main_clk";
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	fsl,spi-num-chipselects = <2>;
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
		   <&gpio4 25 GPIO_ACTIVE_LOW>;
	status = "okay";

	pmic: mc13892@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mc13892";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		spi-max-frequency = <6000000>;
		spi-cs-high;
		reg = <0>;
		interrupt-parent = <&gpio1>;
		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

		regulators {
			sw1_reg: sw1 {
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1375000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vpll_reg: vpll {
				regulator-min-microvolt = <1050000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vdig_reg: vdig {
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
			};

			vsd_reg: vsd {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3150000>;
			};

			vusb2_reg: vusb2 {
				regulator-min-microvolt = <2400000>;
				regulator-max-microvolt = <2775000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vvideo_reg: vvideo {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
			};

			vaudio_reg: vaudio {
				regulator-min-microvolt = <2300000>;
				regulator-max-microvolt = <3000000>;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3000000>;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2900000>;
				regulator-always-on;
			};
		};
	};

	flash: at45db321d@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
		spi-max-frequency = <25000000>;
		reg = <1>;

		partition@0 {
			label = "U-Boot";
			reg = <0x0 0x40000>;
			read-only;
		};

		partition@40000 {
			label = "Kernel";
			reg = <0x40000 0x3c0000>;
		};
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	fsl,cd-controller;
	fsl,wp-controller;
	status = "okay";
};

&esdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc2>;
	cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	sgtl5000: codec@0a {
		compatible = "fsl,sgtl5000";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_clkcodec>;
		reg = <0x0a>;
		clocks = <&clk_26M>;
		VDDA-supply = <&vdig_reg>;
		VDDIO-supply = <&vvideo_reg>;
	};
};

&ipu_di0_disp0 {
	remote-endpoint = <&display0_in>;
};

&ipu_di1_disp1 {
	remote-endpoint = <&display1_in>;
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	linux,keymap = <
		MATRIX_KEY(0, 0, KEY_UP)
		MATRIX_KEY(0, 1, KEY_DOWN)
		MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
		MATRIX_KEY(0, 3, KEY_HOME)
		MATRIX_KEY(1, 0, KEY_RIGHT)
		MATRIX_KEY(1, 1, KEY_LEFT)
		MATRIX_KEY(1, 2, KEY_ENTER)
		MATRIX_KEY(1, 3, KEY_VOLUMEUP)
		MATRIX_KEY(2, 0, KEY_F6)
		MATRIX_KEY(2, 1, KEY_F8)
		MATRIX_KEY(2, 2, KEY_F9)
		MATRIX_KEY(2, 3, KEY_F10)
		MATRIX_KEY(3, 0, KEY_F1)
		MATRIX_KEY(3, 1, KEY_F2)
		MATRIX_KEY(3, 2, KEY_F3)
		MATRIX_KEY(3, 3, KEY_POWER)
	>;
	status = "okay";
};

&ssi2 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbh1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1>;
	vbus-supply = <&reg_usbh1_vbus>;
	fsl,usbphy = <&usbh1phy>;
	phy_type = "ulpi";
	status = "okay";
};

&usbotg {
	dr_mode = "otg";
	disable-over-current;
	phy_type = "utmi_wide";
	vbus-supply = <&reg_usbotg_vbus>;
	status = "okay";
};

&iomuxc {
	imx51-babbage {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX51_PAD_AUD3_BB_TXD__AUD3_TXD		0x80000000
				MX51_PAD_AUD3_BB_RXD__AUD3_RXD		0x80000000
				MX51_PAD_AUD3_BB_CK__AUD3_TXC		0x80000000
				MX51_PAD_AUD3_BB_FS__AUD3_TXFS		0x80000000
			>;
		};

		pinctrl_clkcodec: clkcodecgrp {
			fsl,pins = <
				MX51_PAD_CSPI1_RDY__GPIO4_26		0x80000000
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
				MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */
				MX51_PAD_CSPI1_SS1__GPIO4_25		0x85 /* CS1 */
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
				MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
				MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
				MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
				MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
				MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
				MX51_PAD_GPIO1_0__SD1_CD		0x20d5
				MX51_PAD_GPIO1_1__SD1_WP		0x20d5
			>;
		};

		pinctrl_esdhc2: esdhc2grp {
			fsl,pins = <
				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
				MX51_PAD_GPIO1_5__GPIO1_5		0x100 /* WP */
				MX51_PAD_GPIO1_6__GPIO1_6		0x100 /* CD */
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX51_PAD_EIM_EB2__FEC_MDIO		0x80000000
				MX51_PAD_EIM_EB3__FEC_RDATA1		0x80000000
				MX51_PAD_EIM_CS2__FEC_RDATA2		0x80000000
				MX51_PAD_EIM_CS3__FEC_RDATA3		0x80000000
				MX51_PAD_EIM_CS4__FEC_RX_ER		0x80000000
				MX51_PAD_EIM_CS5__FEC_CRS		0x80000000
				MX51_PAD_NANDF_RB2__FEC_COL		0x80000000
				MX51_PAD_NANDF_RB3__FEC_RX_CLK		0x80000000
				MX51_PAD_NANDF_D9__FEC_RDATA0		0x80000000
				MX51_PAD_NANDF_D8__FEC_TDATA0		0x80000000
				MX51_PAD_NANDF_CS2__FEC_TX_ER		0x80000000
				MX51_PAD_NANDF_CS3__FEC_MDC		0x80000000
				MX51_PAD_NANDF_CS4__FEC_TDATA1		0x80000000
				MX51_PAD_NANDF_CS5__FEC_TDATA2		0x80000000
				MX51_PAD_NANDF_CS6__FEC_TDATA3		0x80000000
				MX51_PAD_NANDF_CS7__FEC_TX_EN		0x80000000
				MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	0x80000000
				MX51_PAD_EIM_A20__GPIO2_14		0x85 /* Reset */
			>;
		};

		pinctrl_gpio_keys: gpiokeysgrp {
			fsl,pins = <
				MX51_PAD_EIM_A27__GPIO2_21		0x5
			>;
		};

		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
				MX51_PAD_EIM_D22__GPIO2_6		0x80000000
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX51_PAD_EIM_D19__I2C1_SCL		0x400001ed
				MX51_PAD_EIM_D16__I2C1_SDA		0x400001ed
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX51_PAD_KEY_COL4__I2C2_SCL		0x400001ed
				MX51_PAD_KEY_COL5__I2C2_SDA		0x400001ed
			>;
		};

		pinctrl_ipu_disp1: ipudisp1grp {
			fsl,pins = <
				MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
				MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
				MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
				MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
				MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
				MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
				MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
				MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
				MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
				MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
				MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
				MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
				MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
				MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
				MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
				MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
				MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
				MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
				MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
				MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
				MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
				MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
				MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
				MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
				MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
				MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
			>;
		};

		pinctrl_ipu_disp2: ipudisp2grp {
			fsl,pins = <
				MX51_PAD_DISP2_DAT0__DISP2_DAT0		0x5
				MX51_PAD_DISP2_DAT1__DISP2_DAT1		0x5
				MX51_PAD_DISP2_DAT2__DISP2_DAT2		0x5
				MX51_PAD_DISP2_DAT3__DISP2_DAT3		0x5
				MX51_PAD_DISP2_DAT4__DISP2_DAT4		0x5
				MX51_PAD_DISP2_DAT5__DISP2_DAT5		0x5
				MX51_PAD_DISP2_DAT6__DISP2_DAT6		0x5
				MX51_PAD_DISP2_DAT7__DISP2_DAT7		0x5
				MX51_PAD_DISP2_DAT8__DISP2_DAT8		0x5
				MX51_PAD_DISP2_DAT9__DISP2_DAT9		0x5
				MX51_PAD_DISP2_DAT10__DISP2_DAT10	0x5
				MX51_PAD_DISP2_DAT11__DISP2_DAT11	0x5
				MX51_PAD_DISP2_DAT12__DISP2_DAT12	0x5
				MX51_PAD_DISP2_DAT13__DISP2_DAT13	0x5
				MX51_PAD_DISP2_DAT14__DISP2_DAT14	0x5
				MX51_PAD_DISP2_DAT15__DISP2_DAT15	0x5
				MX51_PAD_DI2_PIN2__DI2_PIN2		0x5
				MX51_PAD_DI2_PIN3__DI2_PIN3		0x5
				MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	0x5
				MX51_PAD_DI_GP4__DI2_PIN15		0x5
			>;
		};

		pinctrl_kpp: kppgrp {
			fsl,pins = <
				MX51_PAD_KEY_ROW0__KEY_ROW0		0xe0
				MX51_PAD_KEY_ROW1__KEY_ROW1		0xe0
				MX51_PAD_KEY_ROW2__KEY_ROW2		0xe0
				MX51_PAD_KEY_ROW3__KEY_ROW3		0xe0
				MX51_PAD_KEY_COL0__KEY_COL0		0xe8
				MX51_PAD_KEY_COL1__KEY_COL1		0xe8
				MX51_PAD_KEY_COL2__KEY_COL2		0xe8
				MX51_PAD_KEY_COL3__KEY_COL3		0xe8
			>;
		};

		pinctrl_pmic: pmicgrp {
			fsl,pins = <
				MX51_PAD_GPIO1_8__GPIO1_8		0xe5 /* IRQ */
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
				MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
				MX51_PAD_UART1_RTS__UART1_RTS		0x1c5
				MX51_PAD_UART1_CTS__UART1_CTS		0x1c5
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX51_PAD_UART2_RXD__UART2_RXD		0x1c5
				MX51_PAD_UART2_TXD__UART2_TXD		0x1c5
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX51_PAD_EIM_D25__UART3_RXD		0x1c5
				MX51_PAD_EIM_D26__UART3_TXD		0x1c5
				MX51_PAD_EIM_D27__UART3_RTS		0x1c5
				MX51_PAD_EIM_D24__UART3_CTS		0x1c5
			>;
		};

		pinctrl_usbh1: usbh1grp {
			fsl,pins = <
				MX51_PAD_USBH1_CLK__USBH1_CLK		0x80000000
				MX51_PAD_USBH1_DIR__USBH1_DIR		0x80000000
				MX51_PAD_USBH1_NXT__USBH1_NXT		0x80000000
				MX51_PAD_USBH1_DATA0__USBH1_DATA0	0x80000000
				MX51_PAD_USBH1_DATA1__USBH1_DATA1	0x80000000
				MX51_PAD_USBH1_DATA2__USBH1_DATA2	0x80000000
				MX51_PAD_USBH1_DATA3__USBH1_DATA3	0x80000000
				MX51_PAD_USBH1_DATA4__USBH1_DATA4	0x80000000
				MX51_PAD_USBH1_DATA5__USBH1_DATA5	0x80000000
				MX51_PAD_USBH1_DATA6__USBH1_DATA6	0x80000000
				MX51_PAD_USBH1_DATA7__USBH1_DATA7	0x80000000
			>;
		};

		pinctrl_usbh1reg: usbh1reggrp {
			fsl,pins = <
				MX51_PAD_EIM_D21__GPIO2_5		0x85
			>;
		};

		pinctrl_usbotgreg: usbotgreggrp {
			fsl,pins = <
				MX51_PAD_GPIO1_7__GPIO1_7		0x85
			>;
		};
	};
};
Commit	Line	Data
9daaf31a SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/dts-v1/;
36dffd8f	14	#include "imx51.dtsi"
9daaf31a SG	15
	16	/ {
	17	model = "Freescale i.MX51 Babbage Board";
	18	compatible = "fsl,imx51-babbage", "fsl,imx51";
	19
9daaf31a SG	20	memory {
	21	reg = <0x90000000 0x20000000>;
	22	};
	23
1c0daab7 AS	24	clocks {
	25	ckih1 {
	26	clock-frequency = <22579200>;
	27	};
	28
	29	clk_26M: codec_clock {
	30	compatible = "fixed-clock";
	31	reg=<0>;
	32	#clock-cells = <0>;
	33	clock-frequency = <26000000>;
	34	gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
	35	};
	36	};
	37
17b5001b	38	display0: display@di0 {
be4ccfce	39	compatible = "fsl,imx-parallel-display";
be4ccfce SG	40	interface-pix-fmt = "rgb24";
be4ccfce SG	41	pinctrl-names = "default";
5a2a7d57	42	pinctrl-0 = <&pinctrl_ipu_disp1>;
493a8636 FE	43	display-timings {
	44	native-mode = <&timing0>;
	45	timing0: dvi {
	46	clock-frequency = <65000000>;
	47	hactive = <1024>;
	48	vactive = <768>;
	49	hback-porch = <220>;
	50	hfront-porch = <40>;
	51	vback-porch = <21>;
	52	vfront-porch = <7>;
	53	hsync-len = <60>;
	54	vsync-len = <10>;
	55	};
	56	};
de10e04e PZ	57
	58	port {
	59	display0_in: endpoint {
	60	remote-endpoint = <&ipu_di0_disp0>;
	61	};
	62	};
be4ccfce	63	};
a15d9f89	64
17b5001b	65	display1: display@di1 {
be4ccfce	66	compatible = "fsl,imx-parallel-display";
be4ccfce SG	67	interface-pix-fmt = "rgb565";
be4ccfce SG	68	pinctrl-names = "default";
5a2a7d57	69	pinctrl-0 = <&pinctrl_ipu_disp2>;
493a8636 FE	70	status = "disabled";
	71	display-timings {
	72	native-mode = <&timing1>;
	73	timing1: claawvga {
	74	clock-frequency = <27000000>;
	75	hactive = <800>;
	76	vactive = <480>;
	77	hback-porch = <40>;
	78	hfront-porch = <60>;
	79	vback-porch = <10>;
	80	vfront-porch = <10>;
	81	hsync-len = <20>;
	82	vsync-len = <10>;
	83	hsync-active = <0>;
	84	vsync-active = <0>;
	85	de-active = <1>;
	86	pixelclk-active = <0>;
	87	};
	88	};
de10e04e PZ	89
	90	port {
	91	display1_in: endpoint {
	92	remote-endpoint = <&ipu_di1_disp1>;
	93	};
	94	};
9daaf31a SG	95	};
	96
	97	gpio-keys {
	98	compatible = "gpio-keys";
2ccc447c AS	99	pinctrl-names = "default";
2ccc447c AS	100	pinctrl-0 = <&pinctrl_gpio_keys>;
9daaf31a SG	101
	102	power {
	103	label = "Power Button";
bdb3eec7	104	gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
02134e77	105	linux,code = <KEY_POWER>;
9daaf31a SG	106	gpio-key,wakeup;
	107	};
	108	};
a15d9f89	109
a198af23 LY	110	leds {
	111	compatible = "gpio-leds";
	112	pinctrl-names = "default";
	113	pinctrl-0 = <&pinctrl_gpio_leds>;
	114
	115	led-diagnostic {
	116	label = "diagnostic";
	117	gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
	118	};
	119	};
	120
9bf206a9 FE	121	regulators {
	122	compatible = "simple-bus";
	123	#address-cells = <1>;
	124	#size-cells = <0>;
	125
db8235ec	126	reg_usbh1_vbus: regulator@0 {
9bf206a9	127	compatible = "regulator-fixed";
2ccc447c	128	pinctrl-names = "default";
db8235ec	129	pinctrl-0 = <&pinctrl_usbh1reg>;
9bf206a9	130	reg = <0>;
db8235ec	131	regulator-name = "usbh1_vbus";
9bf206a9 FE	132	regulator-min-microvolt = <5000000>;
9bf206a9 FE	133	regulator-max-microvolt = <5000000>;
2ccc447c	134	gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
9bf206a9 FE	135	enable-active-high;
9bf206a9 FE	136	};
db8235ec AS	137
	138	reg_usbotg_vbus: regulator@1 {
	139	compatible = "regulator-fixed";
	140	pinctrl-names = "default";
	141	pinctrl-0 = <&pinctrl_usbotgreg>;
	142	reg = <1>;
	143	regulator-name = "usbotg_vbus";
	144	regulator-min-microvolt = <5000000>;
	145	regulator-max-microvolt = <5000000>;
	146	gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
	147	enable-active-high;
	148	};
9bf206a9 FE	149	};
9bf206a9 FE	150
1c0daab7 AS	151	sound {
	152	compatible = "fsl,imx51-babbage-sgtl5000",
	153	"fsl,imx-audio-sgtl5000";
	154	model = "imx51-babbage-sgtl5000";
	155	ssi-controller = <&ssi2>;
	156	audio-codec = <&sgtl5000>;
	157	audio-routing =
	158	"MIC_IN", "Mic Jack",
	159	"Mic Jack", "Mic Bias",
	160	"Headphone Jack", "HP_OUT";
	161	mux-int-port = <2>;
	162	mux-ext-port = <3>;
	163	};
	164
9bf206a9 FE	165	usbphy {
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168	compatible = "simple-bus";
	169
	170	usbh1phy: usbh1phy@0 {
	171	compatible = "usb-nop-xceiv";
	172	reg = <0>;
	173	clocks = <&clks 0>;
	174	clock-names = "main_clk";
	175	};
	176	};
9daaf31a	177	};
be4ccfce	178
1c0daab7	179	&audmux {
be4ccfce	180	pinctrl-names = "default";
1c0daab7	181	pinctrl-0 = <&pinctrl_audmux>;
be4ccfce SG	182	status = "okay";
	183	};
	184
	185	&ecspi1 {
	186	pinctrl-names = "default";
5a2a7d57	187	pinctrl-0 = <&pinctrl_ecspi1>;
be4ccfce	188	fsl,spi-num-chipselects = <2>;
bdb3eec7	189	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
d2176f29	190	<&gpio4 25 GPIO_ACTIVE_LOW>;
be4ccfce SG	191	status = "okay";
	192
	193	pmic: mc13892@0 {
	194	#address-cells = <1>;
	195	#size-cells = <0>;
	196	compatible = "fsl,mc13892";
1ddcff4b AS	197	pinctrl-names = "default";
1ddcff4b AS	198	pinctrl-0 = <&pinctrl_pmic>;
be4ccfce	199	spi-max-frequency = <6000000>;
dc071436	200	spi-cs-high;
be4ccfce SG	201	reg = <0>;
be4ccfce SG	202	interrupt-parent = <&gpio1>;
1cbb74fd	203	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
be4ccfce SG	204
	205	regulators {
	206	sw1_reg: sw1 {
	207	regulator-min-microvolt = <600000>;
	208	regulator-max-microvolt = <1375000>;
	209	regulator-boot-on;
	210	regulator-always-on;
	211	};
	212
	213	sw2_reg: sw2 {
	214	regulator-min-microvolt = <900000>;
	215	regulator-max-microvolt = <1850000>;
	216	regulator-boot-on;
	217	regulator-always-on;
	218	};
	219
	220	sw3_reg: sw3 {
	221	regulator-min-microvolt = <1100000>;
	222	regulator-max-microvolt = <1850000>;
	223	regulator-boot-on;
	224	regulator-always-on;
	225	};
	226
	227	sw4_reg: sw4 {
	228	regulator-min-microvolt = <1100000>;
	229	regulator-max-microvolt = <1850000>;
	230	regulator-boot-on;
	231	regulator-always-on;
	232	};
	233
	234	vpll_reg: vpll {
	235	regulator-min-microvolt = <1050000>;
	236	regulator-max-microvolt = <1800000>;
	237	regulator-boot-on;
	238	regulator-always-on;
	239	};
	240
	241	vdig_reg: vdig {
	242	regulator-min-microvolt = <1650000>;
	243	regulator-max-microvolt = <1650000>;
	244	regulator-boot-on;
	245	};
	246
	247	vsd_reg: vsd {
	248	regulator-min-microvolt = <1800000>;
	249	regulator-max-microvolt = <3150000>;
	250	};
	251
	252	vusb2_reg: vusb2 {
	253	regulator-min-microvolt = <2400000>;
	254	regulator-max-microvolt = <2775000>;
	255	regulator-boot-on;
	256	regulator-always-on;
	257	};
	258
	259	vvideo_reg: vvideo {
	260	regulator-min-microvolt = <2775000>;
	261	regulator-max-microvolt = <2775000>;
	262	};
	263
	264	vaudio_reg: vaudio {
	265	regulator-min-microvolt = <2300000>;
	266	regulator-max-microvolt = <3000000>;
	267	};
268
269	vcam_reg: vcam {
270	regulator-min-microvolt = <2500000>;
271	regulator-max-microvolt = <3000000>;
272	};
273
274	vgen1_reg: vgen1 {
275	regulator-min-microvolt = <1200000>;
276	regulator-max-microvolt = <1200000>;
277	};
278
279	vgen2_reg: vgen2 {
280	regulator-min-microvolt = <1200000>;
281	regulator-max-microvolt = <3150000>;
282	regulator-always-on;
283	};
284
285	vgen3_reg: vgen3 {
286	regulator-min-microvolt = <1800000>;
287	regulator-max-microvolt = <2900000>;
288	regulator-always-on;
289	};
290	};
291	};
292
293	flash: at45db321d@1 {
294	#address-cells = <1>;
295	#size-cells = <1>;
296	compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
297	spi-max-frequency = <25000000>;
298	reg = <1>;
299
300	partition@0 {
301	label = "U-Boot";
302	reg = <0x0 0x40000>;
303	read-only;
304	};
305
306	partition@40000 {
307	label = "Kernel";
308	reg = <0x40000 0x3c0000>;
309	};
310	};
311	};
312
1c0daab7 AS	313	&esdhc1 {
	314	pinctrl-names = "default";
	315	pinctrl-0 = <&pinctrl_esdhc1>;
	316	fsl,cd-controller;
	317	fsl,wp-controller;
	318	status = "okay";
	319	};
	320
	321	&esdhc2 {
	322	pinctrl-names = "default";
	323	pinctrl-0 = <&pinctrl_esdhc2>;
	324	cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	325	wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	326	status = "okay";
	327	};
	328
	329	&fec {
	330	pinctrl-names = "default";
	331	pinctrl-0 = <&pinctrl_fec>;
	332	phy-mode = "mii";
	333	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	334	phy-reset-duration = <1>;
	335	status = "okay";
	336	};
	337
dd0c672a AS	338	&i2c1 {
	339	pinctrl-names = "default";
	340	pinctrl-0 = <&pinctrl_i2c1>;
	341	status = "okay";
	342	};
	343
1c0daab7 AS	344	&i2c2 {
	345	pinctrl-names = "default";
	346	pinctrl-0 = <&pinctrl_i2c2>;
	347	status = "okay";
	348
	349	sgtl5000: codec@0a {
	350	compatible = "fsl,sgtl5000";
	351	pinctrl-names = "default";
	352	pinctrl-0 = <&pinctrl_clkcodec>;
	353	reg = <0x0a>;
	354	clocks = <&clk_26M>;
	355	VDDA-supply = <&vdig_reg>;
	356	VDDIO-supply = <&vvideo_reg>;
	357	};
	358	};
	359
de10e04e PZ	360	&ipu_di0_disp0 {
	361	remote-endpoint = <&display0_in>;
	362	};
	363
	364	&ipu_di1_disp1 {
	365	remote-endpoint = <&display1_in>;
	366	};
	367
1c0daab7 AS	368	&kpp {
	369	pinctrl-names = "default";
	370	pinctrl-0 = <&pinctrl_kpp>;
	371	linux,keymap = <
	372	MATRIX_KEY(0, 0, KEY_UP)
	373	MATRIX_KEY(0, 1, KEY_DOWN)
	374	MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
	375	MATRIX_KEY(0, 3, KEY_HOME)
	376	MATRIX_KEY(1, 0, KEY_RIGHT)
	377	MATRIX_KEY(1, 1, KEY_LEFT)
	378	MATRIX_KEY(1, 2, KEY_ENTER)
	379	MATRIX_KEY(1, 3, KEY_VOLUMEUP)
	380	MATRIX_KEY(2, 0, KEY_F6)
	381	MATRIX_KEY(2, 1, KEY_F8)
	382	MATRIX_KEY(2, 2, KEY_F9)
	383	MATRIX_KEY(2, 3, KEY_F10)
	384	MATRIX_KEY(3, 0, KEY_F1)
	385	MATRIX_KEY(3, 1, KEY_F2)
	386	MATRIX_KEY(3, 2, KEY_F3)
	387	MATRIX_KEY(3, 3, KEY_POWER)
	388	>;
	389	status = "okay";
	390	};
	391
be4ccfce SG	392	&ssi2 {
	393	fsl,mode = "i2s-slave";
	394	status = "okay";
	395	};
	396
1c0daab7 AS	397	&uart1 {
	398	pinctrl-names = "default";
	399	pinctrl-0 = <&pinctrl_uart1>;
	400	fsl,uart-has-rtscts;
	401	status = "okay";
	402	};
	403
	404	&uart2 {
	405	pinctrl-names = "default";
	406	pinctrl-0 = <&pinctrl_uart2>;
	407	status = "okay";
	408	};
	409
	410	&uart3 {
	411	pinctrl-names = "default";
	412	pinctrl-0 = <&pinctrl_uart3>;
	413	fsl,uart-has-rtscts;
	414	status = "okay";
	415	};
	416
	417	&usbh1 {
	418	pinctrl-names = "default";
	419	pinctrl-0 = <&pinctrl_usbh1>;
	420	vbus-supply = <&reg_usbh1_vbus>;
	421	fsl,usbphy = <&usbh1phy>;
	422	phy_type = "ulpi";
	423	status = "okay";
	424	};
	425
	426	&usbotg {
	427	dr_mode = "otg";
	428	disable-over-current;
	429	phy_type = "utmi_wide";
	430	vbus-supply = <&reg_usbotg_vbus>;
	431	status = "okay";
	432	};
	433
be4ccfce	434	&iomuxc {
5a2a7d57	435	imx51-babbage {
5a2a7d57 SG	436	pinctrl_audmux: audmuxgrp {
	437	fsl,pins = <
	438	MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
	439	MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
	440	MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
	441	MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
	442	>;
	443	};
	444
2ccc447c AS	445	pinctrl_clkcodec: clkcodecgrp {
	446	fsl,pins = <
	447	MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
	448	>;
	449	};
	450
5a2a7d57 SG	451	pinctrl_ecspi1: ecspi1grp {
	452	fsl,pins = <
	453	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	454	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	455	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
2ccc447c AS	456	MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
2ccc447c AS	457	MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
5a2a7d57 SG	458	>;
	459	};
	460
	461	pinctrl_esdhc1: esdhc1grp {
	462	fsl,pins = <
	463	MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
	464	MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
	465	MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
	466	MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
	467	MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
	468	MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
2ccc447c AS	469	MX51_PAD_GPIO1_0__SD1_CD 0x20d5
2ccc447c AS	470	MX51_PAD_GPIO1_1__SD1_WP 0x20d5
5a2a7d57 SG	471	>;
	472	};
	473
	474	pinctrl_esdhc2: esdhc2grp {
	475	fsl,pins = <
	476	MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
	477	MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
	478	MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
	479	MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
	480	MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
	481	MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
2ccc447c AS	482	MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
2ccc447c AS	483	MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
5a2a7d57 SG	484	>;
	485	};
	486
	487	pinctrl_fec: fecgrp {
	488	fsl,pins = <
	489	MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
	490	MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
	491	MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
	492	MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
	493	MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
	494	MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
	495	MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
	496	MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
	497	MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
	498	MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
	499	MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
	500	MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
	501	MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
	502	MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
	503	MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
	504	MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
	505	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
1c0daab7	506	MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
5a2a7d57 SG	507	>;
	508	};
	509
2ccc447c AS	510	pinctrl_gpio_keys: gpiokeysgrp {
	511	fsl,pins = <
	512	MX51_PAD_EIM_A27__GPIO2_21 0x5
	513	>;
	514	};
	515
a198af23 LY	516	pinctrl_gpio_leds: gpioledsgrp {
	517	fsl,pins = <
	518	MX51_PAD_EIM_D22__GPIO2_6 0x80000000
	519	>;
	520	};
	521
dd0c672a AS	522	pinctrl_i2c1: i2c1grp {
	523	fsl,pins = <
	524	MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
	525	MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
	526	>;
	527	};
	528
5a2a7d57 SG	529	pinctrl_i2c2: i2c2grp {
	530	fsl,pins = <
	531	MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
	532	MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
	533	>;
	534	};
	535
	536	pinctrl_ipu_disp1: ipudisp1grp {
	537	fsl,pins = <
	538	MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
	539	MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
	540	MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
	541	MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
	542	MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
	543	MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
	544	MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
	545	MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
	546	MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
	547	MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
	548	MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
	549	MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
	550	MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
	551	MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
	552	MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
	553	MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
	554	MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
	555	MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
	556	MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
	557	MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
	558	MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
	559	MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
	560	MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
	561	MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
	562	MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
	563	MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
	564	>;
	565	};
	566
	567	pinctrl_ipu_disp2: ipudisp2grp {
	568	fsl,pins = <
	569	MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
	570	MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
	571	MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
	572	MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
	573	MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
	574	MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
	575	MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
	576	MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
	577	MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
	578	MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
	579	MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
	580	MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
	581	MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
	582	MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
	583	MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
	584	MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
	585	MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
	586	MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
	587	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
	588	MX51_PAD_DI_GP4__DI2_PIN15 0x5
	589	>;
	590	};
	591
	592	pinctrl_kpp: kppgrp {
593	fsl,pins = <
594	MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
595	MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
596	MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
597	MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
598	MX51_PAD_KEY_COL0__KEY_COL0 0xe8
599	MX51_PAD_KEY_COL1__KEY_COL1 0xe8
600	MX51_PAD_KEY_COL2__KEY_COL2 0xe8
601	MX51_PAD_KEY_COL3__KEY_COL3 0xe8
602	>;
603	};
604
1ddcff4b AS	605	pinctrl_pmic: pmicgrp {
	606	fsl,pins = <
	607	MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
	608	>;
	609	};
	610
5a2a7d57 SG	611	pinctrl_uart1: uart1grp {
	612	fsl,pins = <
	613	MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
	614	MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
	615	MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
	616	MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
	617	>;
	618	};
	619
	620	pinctrl_uart2: uart2grp {
	621	fsl,pins = <
	622	MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
	623	MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
	624	>;
	625	};
	626
	627	pinctrl_uart3: uart3grp {
	628	fsl,pins = <
	629	MX51_PAD_EIM_D25__UART3_RXD 0x1c5
	630	MX51_PAD_EIM_D26__UART3_TXD 0x1c5
	631	MX51_PAD_EIM_D27__UART3_RTS 0x1c5
	632	MX51_PAD_EIM_D24__UART3_CTS 0x1c5
	633	>;
	634	};
9bf206a9 FE	635
	636	pinctrl_usbh1: usbh1grp {
	637	fsl,pins = <
	638	MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
	639	MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
	640	MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
	641	MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
	642	MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
	643	MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
	644	MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
	645	MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
	646	MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
	647	MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
	648	MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
2ccc447c AS	649	>;
	650	};
	651
db8235ec	652	pinctrl_usbh1reg: usbh1reggrp {
2ccc447c AS	653	fsl,pins = <
2ccc447c AS	654	MX51_PAD_EIM_D21__GPIO2_5 0x85
9bf206a9 FE	655	>;
9bf206a9 FE	656	};
db8235ec AS	657
	658	pinctrl_usbotgreg: usbotgreggrp {
	659	fsl,pins = <
	660	MX51_PAD_GPIO1_7__GPIO1_7 0x85
	661	>;
	662	};
be4ccfce SG	663	};
be4ccfce SG	664	};