Commit | Line | Data |
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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
36dffd8f | 14 | #include "imx51.dtsi" |
9daaf31a SG |
15 | |
16 | / { | |
17 | model = "Freescale i.MX51 Babbage Board"; | |
18 | compatible = "fsl,imx51-babbage", "fsl,imx51"; | |
19 | ||
9daaf31a SG |
20 | memory { |
21 | reg = <0x90000000 0x20000000>; | |
22 | }; | |
23 | ||
be4ccfce SG |
24 | display@di0 { |
25 | compatible = "fsl,imx-parallel-display"; | |
26 | crtcs = <&ipu 0>; | |
27 | interface-pix-fmt = "rgb24"; | |
28 | pinctrl-names = "default"; | |
5a2a7d57 | 29 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
493a8636 FE |
30 | display-timings { |
31 | native-mode = <&timing0>; | |
32 | timing0: dvi { | |
33 | clock-frequency = <65000000>; | |
34 | hactive = <1024>; | |
35 | vactive = <768>; | |
36 | hback-porch = <220>; | |
37 | hfront-porch = <40>; | |
38 | vback-porch = <21>; | |
39 | vfront-porch = <7>; | |
40 | hsync-len = <60>; | |
41 | vsync-len = <10>; | |
42 | }; | |
43 | }; | |
be4ccfce | 44 | }; |
a15d9f89 | 45 | |
be4ccfce SG |
46 | display@di1 { |
47 | compatible = "fsl,imx-parallel-display"; | |
48 | crtcs = <&ipu 1>; | |
49 | interface-pix-fmt = "rgb565"; | |
50 | pinctrl-names = "default"; | |
5a2a7d57 | 51 | pinctrl-0 = <&pinctrl_ipu_disp2>; |
493a8636 FE |
52 | status = "disabled"; |
53 | display-timings { | |
54 | native-mode = <&timing1>; | |
55 | timing1: claawvga { | |
56 | clock-frequency = <27000000>; | |
57 | hactive = <800>; | |
58 | vactive = <480>; | |
59 | hback-porch = <40>; | |
60 | hfront-porch = <60>; | |
61 | vback-porch = <10>; | |
62 | vfront-porch = <10>; | |
63 | hsync-len = <20>; | |
64 | vsync-len = <10>; | |
65 | hsync-active = <0>; | |
66 | vsync-active = <0>; | |
67 | de-active = <1>; | |
68 | pixelclk-active = <0>; | |
69 | }; | |
70 | }; | |
9daaf31a SG |
71 | }; |
72 | ||
73 | gpio-keys { | |
74 | compatible = "gpio-keys"; | |
75 | ||
76 | power { | |
77 | label = "Power Button"; | |
4d191868 | 78 | gpios = <&gpio2 21 0>; |
9daaf31a SG |
79 | linux,code = <116>; /* KEY_POWER */ |
80 | gpio-key,wakeup; | |
81 | }; | |
82 | }; | |
a15d9f89 SG |
83 | |
84 | sound { | |
85 | compatible = "fsl,imx51-babbage-sgtl5000", | |
86 | "fsl,imx-audio-sgtl5000"; | |
87 | model = "imx51-babbage-sgtl5000"; | |
88 | ssi-controller = <&ssi2>; | |
89 | audio-codec = <&sgtl5000>; | |
90 | audio-routing = | |
91 | "MIC_IN", "Mic Jack", | |
92 | "Mic Jack", "Mic Bias", | |
93 | "Headphone Jack", "HP_OUT"; | |
94 | mux-int-port = <2>; | |
95 | mux-ext-port = <3>; | |
96 | }; | |
84bb0847 FE |
97 | |
98 | clocks { | |
677e28b1 AS |
99 | ckih1 { |
100 | clock-frequency = <22579200>; | |
101 | }; | |
102 | ||
84bb0847 FE |
103 | clk_26M: codec_clock { |
104 | compatible = "fixed-clock"; | |
105 | reg=<0>; | |
106 | #clock-cells = <0>; | |
107 | clock-frequency = <26000000>; | |
108 | gpios = <&gpio4 26 1>; | |
109 | }; | |
110 | }; | |
9daaf31a | 111 | }; |
be4ccfce SG |
112 | |
113 | &esdhc1 { | |
114 | pinctrl-names = "default"; | |
5a2a7d57 | 115 | pinctrl-0 = <&pinctrl_esdhc1>; |
be4ccfce SG |
116 | fsl,cd-controller; |
117 | fsl,wp-controller; | |
118 | status = "okay"; | |
119 | }; | |
120 | ||
121 | &esdhc2 { | |
122 | pinctrl-names = "default"; | |
5a2a7d57 | 123 | pinctrl-0 = <&pinctrl_esdhc2>; |
be4ccfce SG |
124 | cd-gpios = <&gpio1 6 0>; |
125 | wp-gpios = <&gpio1 5 0>; | |
126 | status = "okay"; | |
127 | }; | |
128 | ||
129 | &uart3 { | |
130 | pinctrl-names = "default"; | |
5a2a7d57 | 131 | pinctrl-0 = <&pinctrl_uart3>; |
be4ccfce SG |
132 | fsl,uart-has-rtscts; |
133 | status = "okay"; | |
134 | }; | |
135 | ||
136 | &ecspi1 { | |
137 | pinctrl-names = "default"; | |
5a2a7d57 | 138 | pinctrl-0 = <&pinctrl_ecspi1>; |
be4ccfce SG |
139 | fsl,spi-num-chipselects = <2>; |
140 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; | |
141 | status = "okay"; | |
142 | ||
143 | pmic: mc13892@0 { | |
144 | #address-cells = <1>; | |
145 | #size-cells = <0>; | |
146 | compatible = "fsl,mc13892"; | |
147 | spi-max-frequency = <6000000>; | |
dc071436 | 148 | spi-cs-high; |
be4ccfce SG |
149 | reg = <0>; |
150 | interrupt-parent = <&gpio1>; | |
151 | interrupts = <8 0x4>; | |
152 | ||
153 | regulators { | |
154 | sw1_reg: sw1 { | |
155 | regulator-min-microvolt = <600000>; | |
156 | regulator-max-microvolt = <1375000>; | |
157 | regulator-boot-on; | |
158 | regulator-always-on; | |
159 | }; | |
160 | ||
161 | sw2_reg: sw2 { | |
162 | regulator-min-microvolt = <900000>; | |
163 | regulator-max-microvolt = <1850000>; | |
164 | regulator-boot-on; | |
165 | regulator-always-on; | |
166 | }; | |
167 | ||
168 | sw3_reg: sw3 { | |
169 | regulator-min-microvolt = <1100000>; | |
170 | regulator-max-microvolt = <1850000>; | |
171 | regulator-boot-on; | |
172 | regulator-always-on; | |
173 | }; | |
174 | ||
175 | sw4_reg: sw4 { | |
176 | regulator-min-microvolt = <1100000>; | |
177 | regulator-max-microvolt = <1850000>; | |
178 | regulator-boot-on; | |
179 | regulator-always-on; | |
180 | }; | |
181 | ||
182 | vpll_reg: vpll { | |
183 | regulator-min-microvolt = <1050000>; | |
184 | regulator-max-microvolt = <1800000>; | |
185 | regulator-boot-on; | |
186 | regulator-always-on; | |
187 | }; | |
188 | ||
189 | vdig_reg: vdig { | |
190 | regulator-min-microvolt = <1650000>; | |
191 | regulator-max-microvolt = <1650000>; | |
192 | regulator-boot-on; | |
193 | }; | |
194 | ||
195 | vsd_reg: vsd { | |
196 | regulator-min-microvolt = <1800000>; | |
197 | regulator-max-microvolt = <3150000>; | |
198 | }; | |
199 | ||
200 | vusb2_reg: vusb2 { | |
201 | regulator-min-microvolt = <2400000>; | |
202 | regulator-max-microvolt = <2775000>; | |
203 | regulator-boot-on; | |
204 | regulator-always-on; | |
205 | }; | |
206 | ||
207 | vvideo_reg: vvideo { | |
208 | regulator-min-microvolt = <2775000>; | |
209 | regulator-max-microvolt = <2775000>; | |
210 | }; | |
211 | ||
212 | vaudio_reg: vaudio { | |
213 | regulator-min-microvolt = <2300000>; | |
214 | regulator-max-microvolt = <3000000>; | |
215 | }; | |
216 | ||
217 | vcam_reg: vcam { | |
218 | regulator-min-microvolt = <2500000>; | |
219 | regulator-max-microvolt = <3000000>; | |
220 | }; | |
221 | ||
222 | vgen1_reg: vgen1 { | |
223 | regulator-min-microvolt = <1200000>; | |
224 | regulator-max-microvolt = <1200000>; | |
225 | }; | |
226 | ||
227 | vgen2_reg: vgen2 { | |
228 | regulator-min-microvolt = <1200000>; | |
229 | regulator-max-microvolt = <3150000>; | |
230 | regulator-always-on; | |
231 | }; | |
232 | ||
233 | vgen3_reg: vgen3 { | |
234 | regulator-min-microvolt = <1800000>; | |
235 | regulator-max-microvolt = <2900000>; | |
236 | regulator-always-on; | |
237 | }; | |
238 | }; | |
239 | }; | |
240 | ||
241 | flash: at45db321d@1 { | |
242 | #address-cells = <1>; | |
243 | #size-cells = <1>; | |
244 | compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; | |
245 | spi-max-frequency = <25000000>; | |
246 | reg = <1>; | |
247 | ||
248 | partition@0 { | |
249 | label = "U-Boot"; | |
250 | reg = <0x0 0x40000>; | |
251 | read-only; | |
252 | }; | |
253 | ||
254 | partition@40000 { | |
255 | label = "Kernel"; | |
256 | reg = <0x40000 0x3c0000>; | |
257 | }; | |
258 | }; | |
259 | }; | |
260 | ||
261 | &ssi2 { | |
262 | fsl,mode = "i2s-slave"; | |
263 | status = "okay"; | |
264 | }; | |
265 | ||
266 | &iomuxc { | |
267 | pinctrl-names = "default"; | |
268 | pinctrl-0 = <&pinctrl_hog>; | |
269 | ||
5a2a7d57 | 270 | imx51-babbage { |
be4ccfce SG |
271 | pinctrl_hog: hoggrp { |
272 | fsl,pins = < | |
e1641531 SG |
273 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 |
274 | MX51_PAD_GPIO1_1__SD1_WP 0x20d5 | |
275 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 | |
276 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 | |
277 | MX51_PAD_EIM_A27__GPIO2_21 0x5 | |
278 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 | |
279 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 | |
84bb0847 | 280 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 |
be4ccfce SG |
281 | >; |
282 | }; | |
5a2a7d57 SG |
283 | |
284 | pinctrl_audmux: audmuxgrp { | |
285 | fsl,pins = < | |
286 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | |
287 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | |
288 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | |
289 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | |
290 | >; | |
291 | }; | |
292 | ||
293 | pinctrl_ecspi1: ecspi1grp { | |
294 | fsl,pins = < | |
295 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | |
296 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | |
297 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | |
298 | >; | |
299 | }; | |
300 | ||
301 | pinctrl_esdhc1: esdhc1grp { | |
302 | fsl,pins = < | |
303 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | |
304 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | |
305 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | |
306 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | |
307 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | |
308 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | |
309 | >; | |
310 | }; | |
311 | ||
312 | pinctrl_esdhc2: esdhc2grp { | |
313 | fsl,pins = < | |
314 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | |
315 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | |
316 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | |
317 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | |
318 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | |
319 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | |
320 | >; | |
321 | }; | |
322 | ||
323 | pinctrl_fec: fecgrp { | |
324 | fsl,pins = < | |
325 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | |
326 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | |
327 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | |
328 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | |
329 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | |
330 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | |
331 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | |
332 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | |
333 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | |
334 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | |
335 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | |
336 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | |
337 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | |
338 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | |
339 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | |
340 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | |
341 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | |
342 | >; | |
343 | }; | |
344 | ||
345 | pinctrl_i2c2: i2c2grp { | |
346 | fsl,pins = < | |
347 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | |
348 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | |
349 | >; | |
350 | }; | |
351 | ||
352 | pinctrl_ipu_disp1: ipudisp1grp { | |
353 | fsl,pins = < | |
354 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | |
355 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | |
356 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | |
357 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | |
358 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | |
359 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | |
360 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | |
361 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | |
362 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | |
363 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | |
364 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | |
365 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | |
366 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | |
367 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | |
368 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | |
369 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | |
370 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | |
371 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | |
372 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | |
373 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | |
374 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | |
375 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | |
376 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | |
377 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | |
378 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 | |
379 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 | |
380 | >; | |
381 | }; | |
382 | ||
383 | pinctrl_ipu_disp2: ipudisp2grp { | |
384 | fsl,pins = < | |
385 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | |
386 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | |
387 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | |
388 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | |
389 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | |
390 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | |
391 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | |
392 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | |
393 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | |
394 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | |
395 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | |
396 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | |
397 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | |
398 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | |
399 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | |
400 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | |
401 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 | |
402 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 | |
403 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | |
404 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | |
405 | >; | |
406 | }; | |
407 | ||
408 | pinctrl_kpp: kppgrp { | |
409 | fsl,pins = < | |
410 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | |
411 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | |
412 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | |
413 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | |
414 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | |
415 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | |
416 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | |
417 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | |
418 | >; | |
419 | }; | |
420 | ||
421 | pinctrl_uart1: uart1grp { | |
422 | fsl,pins = < | |
423 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | |
424 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | |
425 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | |
426 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | |
427 | >; | |
428 | }; | |
429 | ||
430 | pinctrl_uart2: uart2grp { | |
431 | fsl,pins = < | |
432 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | |
433 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | |
434 | >; | |
435 | }; | |
436 | ||
437 | pinctrl_uart3: uart3grp { | |
438 | fsl,pins = < | |
439 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | |
440 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | |
441 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | |
442 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | |
443 | >; | |
444 | }; | |
be4ccfce SG |
445 | }; |
446 | }; | |
447 | ||
448 | &uart1 { | |
449 | pinctrl-names = "default"; | |
5a2a7d57 | 450 | pinctrl-0 = <&pinctrl_uart1>; |
be4ccfce SG |
451 | fsl,uart-has-rtscts; |
452 | status = "okay"; | |
453 | }; | |
454 | ||
455 | &uart2 { | |
456 | pinctrl-names = "default"; | |
5a2a7d57 | 457 | pinctrl-0 = <&pinctrl_uart2>; |
be4ccfce SG |
458 | status = "okay"; |
459 | }; | |
460 | ||
461 | &i2c2 { | |
462 | pinctrl-names = "default"; | |
5a2a7d57 | 463 | pinctrl-0 = <&pinctrl_i2c2>; |
be4ccfce SG |
464 | status = "okay"; |
465 | ||
466 | sgtl5000: codec@0a { | |
467 | compatible = "fsl,sgtl5000"; | |
468 | reg = <0x0a>; | |
84bb0847 | 469 | clocks = <&clk_26M>; |
be4ccfce SG |
470 | VDDA-supply = <&vdig_reg>; |
471 | VDDIO-supply = <&vvideo_reg>; | |
472 | }; | |
473 | }; | |
474 | ||
475 | &audmux { | |
476 | pinctrl-names = "default"; | |
5a2a7d57 | 477 | pinctrl-0 = <&pinctrl_audmux>; |
be4ccfce SG |
478 | status = "okay"; |
479 | }; | |
480 | ||
481 | &fec { | |
482 | pinctrl-names = "default"; | |
5a2a7d57 | 483 | pinctrl-0 = <&pinctrl_fec>; |
be4ccfce SG |
484 | phy-mode = "mii"; |
485 | status = "okay"; | |
486 | }; | |
67eb7c0b LY |
487 | |
488 | &kpp { | |
489 | pinctrl-names = "default"; | |
5a2a7d57 | 490 | pinctrl-0 = <&pinctrl_kpp>; |
67eb7c0b LY |
491 | linux,keymap = <0x00000067 /* KEY_UP */ |
492 | 0x0001006c /* KEY_DOWN */ | |
493 | 0x00020072 /* KEY_VOLUMEDOWN */ | |
494 | 0x00030066 /* KEY_HOME */ | |
495 | 0x0100006a /* KEY_RIGHT */ | |
496 | 0x01010069 /* KEY_LEFT */ | |
497 | 0x0102001c /* KEY_ENTER */ | |
498 | 0x01030073 /* KEY_VOLUMEUP */ | |
499 | 0x02000040 /* KEY_F6 */ | |
500 | 0x02010042 /* KEY_F8 */ | |
501 | 0x02020043 /* KEY_F9 */ | |
502 | 0x02030044 /* KEY_F10 */ | |
503 | 0x0300003b /* KEY_F1 */ | |
504 | 0x0301003c /* KEY_F2 */ | |
505 | 0x0302003d /* KEY_F3 */ | |
506 | 0x03030074>; /* KEY_POWER */ | |
507 | status = "okay"; | |
508 | }; |