[deliverable/linux.git] / arch / arm / boot / dts / imx51.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx51-pinfunc.h"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
	};

	tzic: tz-interrupt-controller@e0000000 {
		compatible = "fsl,imx51-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xe0000000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		ipu: ipu@40000000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx51-ipu";
			reg = <0x40000000 0x20000000>;
			interrupts = <11 10>;
			clocks = <&clks 59>, <&clks 110>, <&clks 61>;
			clock-names = "bus", "di0", "di1";
		};

		aips@70000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x70000000 0x10000000>;
			ranges;

			spba@70000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x70000000 0x40000>;
				ranges;

				esdhc1: esdhc@70004000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks 44>, <&clks 0>, <&clks 71>;
					clock-names = "ipg", "ahb", "per";
					status = "disabled";
				};

				esdhc2: esdhc@70008000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks 45>, <&clks 0>, <&clks 72>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@7000c000 {
					compatible = "fsl,imx51-uart", "fsl,imx21-uart";
					reg = <0x7000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks 32>, <&clks 33>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@70010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx51-ecspi";
					reg = <0x70010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks 51>, <&clks 52>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@70014000 {
					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
					reg = <0x70014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks 49>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@70020000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks 46>, <&clks 0>, <&clks 73>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@70024000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks 47>, <&clks 0>, <&clks 74>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@73f80000 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80000 0x0200>;
				interrupts = <18>;
				status = "disabled";
			};

			usbh1: usb@73f80200 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80200 0x0200>;
				interrupts = <14>;
				status = "disabled";
			};

			usbh2: usb@73f80400 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80400 0x0200>;
				interrupts = <16>;
				status = "disabled";
			};

			usbh3: usb@73f80600 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80600 0x0200>;
				interrupts = <17>;
				status = "disabled";
			};

			gpio1: gpio@73f84000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@73f88000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@73f8c000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@73f90000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			kpp: kpp@73f94000 {
				compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
				reg = <0x73f94000 0x4000>;
				interrupts = <60>;
				clocks = <&clks 0>;
				status = "disabled";
			};

			wdog1: wdog@73f98000 {
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
				reg = <0x73f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks 0>;
			};

			wdog2: wdog@73f9c000 {
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
				reg = <0x73f9c000 0x4000>;
				interrupts = <59>;
				clocks = <&clks 0>;
				status = "disabled";
			};

			gpt: timer@73fa0000 {
				compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
				reg = <0x73fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks 36>, <&clks 41>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@73fa8000 {
				compatible = "fsl,imx51-iomuxc";
				reg = <0x73fa8000 0x4000>;

				audmux {
					pinctrl_audmux_1: audmuxgrp-1 {
						fsl,pins = <
							MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
							MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
							MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
							MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
						>;
					};
				};

				fec {
					pinctrl_fec_1: fecgrp-1 {
						fsl,pins = <
							MX51_PAD_EIM_EB2__FEC_MDIO	   0x80000000
							MX51_PAD_EIM_EB3__FEC_RDATA1	   0x80000000
							MX51_PAD_EIM_CS2__FEC_RDATA2	   0x80000000
							MX51_PAD_EIM_CS3__FEC_RDATA3	   0x80000000
							MX51_PAD_EIM_CS4__FEC_RX_ER	   0x80000000
							MX51_PAD_EIM_CS5__FEC_CRS	   0x80000000
							MX51_PAD_NANDF_RB2__FEC_COL	   0x80000000
							MX51_PAD_NANDF_RB3__FEC_RX_CLK	   0x80000000
							MX51_PAD_NANDF_D9__FEC_RDATA0	   0x80000000
							MX51_PAD_NANDF_D8__FEC_TDATA0	   0x80000000
							MX51_PAD_NANDF_CS2__FEC_TX_ER	   0x80000000
							MX51_PAD_NANDF_CS3__FEC_MDC	   0x80000000
							MX51_PAD_NANDF_CS4__FEC_TDATA1	   0x80000000
							MX51_PAD_NANDF_CS5__FEC_TDATA2	   0x80000000
							MX51_PAD_NANDF_CS6__FEC_TDATA3	   0x80000000
							MX51_PAD_NANDF_CS7__FEC_TX_EN	   0x80000000
							MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
						>;
					};

					pinctrl_fec_2: fecgrp-2 {
						fsl,pins = <
							MX51_PAD_DI_GP3__FEC_TX_ER	  0x80000000
							MX51_PAD_DI2_PIN4__FEC_CRS	  0x80000000
							MX51_PAD_DI2_PIN2__FEC_MDC	  0x80000000
							MX51_PAD_DI2_PIN3__FEC_MDIO	  0x80000000
							MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
							MX51_PAD_DI_GP4__FEC_RDATA2	  0x80000000
							MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
							MX51_PAD_DISP2_DAT1__FEC_RX_ER	  0x80000000
							MX51_PAD_DISP2_DAT6__FEC_TDATA1	  0x80000000
							MX51_PAD_DISP2_DAT7__FEC_TDATA2	  0x80000000
							MX51_PAD_DISP2_DAT8__FEC_TDATA3	  0x80000000
							MX51_PAD_DISP2_DAT9__FEC_TX_EN	  0x80000000
							MX51_PAD_DISP2_DAT10__FEC_COL	  0x80000000
							MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
							MX51_PAD_DISP2_DAT12__FEC_RX_DV	  0x80000000
							MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
							MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
							MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
						>;
					};
				};

				ecspi1 {
					pinctrl_ecspi1_1: ecspi1grp-1 {
						fsl,pins = <
							MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
							MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
							MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
						>;
					};
				};

				ecspi2 {
					pinctrl_ecspi2_1: ecspi2grp-1 {
						fsl,pins = <
							MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
							MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
							MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
						>;
					};
				};

				esdhc1 {
					pinctrl_esdhc1_1: esdhc1grp-1 {
						fsl,pins = <
							MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
							MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
							MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
							MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
							MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
							MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
						>;
					};
				};

				esdhc2 {
					pinctrl_esdhc2_1: esdhc2grp-1 {
						fsl,pins = <
							MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
							MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
							MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
							MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
							MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
							MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
						>;
					};
				};

				i2c2 {
					pinctrl_i2c2_1: i2c2grp-1 {
						fsl,pins = <
							MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
							MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
						>;
					};

					pinctrl_i2c2_2: i2c2grp-2 {
						fsl,pins = <
							MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
							MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
						>;
					};
				};

				ipu_disp1 {
					pinctrl_ipu_disp1_1: ipudisp1grp-1 {
						fsl,pins = <
							MX51_PAD_DISP1_DAT0__DISP1_DAT0	  0x5
							MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
							MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
							MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
							MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
							MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
							MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
							MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
							MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
							MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
							MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
							MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
							MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
							MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
							MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
							MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
							MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
							MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
							MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
							MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
							MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
							MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
							MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
							MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
							MX51_PAD_DI1_PIN2__DI1_PIN2	  0x5 /* hsync */
							MX51_PAD_DI1_PIN3__DI1_PIN3	  0x5 /* vsync */
						>;
					};
				};

				ipu_disp2 {
					pinctrl_ipu_disp2_1: ipudisp2grp-1 {
						fsl,pins = <
							MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
							MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
							MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
							MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
							MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
							MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
							MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
							MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
							MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
							MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
							MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
							MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
							MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
							MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
							MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
							MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
							MX51_PAD_DI2_PIN2__DI2_PIN2	    0x5 /* hsync */
							MX51_PAD_DI2_PIN3__DI2_PIN3	    0x5 /* vsync */
							MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
							MX51_PAD_DI_GP4__DI2_PIN15	    0x5
						>;
					};
				};

				uart1 {
					pinctrl_uart1_1: uart1grp-1 {
						fsl,pins = <
							MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
							MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
							MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
							MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
						>;
					};
				};

				uart2 {
					pinctrl_uart2_1: uart2grp-1 {
						fsl,pins = <
							MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
							MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
						>;
					};
				};

				uart3 {
					pinctrl_uart3_1: uart3grp-1 {
						fsl,pins = <
							MX51_PAD_EIM_D25__UART3_RXD 0x1c5
							MX51_PAD_EIM_D26__UART3_TXD 0x1c5
							MX51_PAD_EIM_D27__UART3_RTS 0x1c5
							MX51_PAD_EIM_D24__UART3_CTS 0x1c5
						>;
					};

					pinctrl_uart3_2: uart3grp-2 {
						fsl,pins = <
							MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
							MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
						>;
					};
				};

				kpp {
					pinctrl_kpp_1: kppgrp-1 {
						fsl,pins = <
							MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
							MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
							MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
							MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
							MX51_PAD_KEY_COL0__KEY_COL0 0xe8
							MX51_PAD_KEY_COL1__KEY_COL1 0xe8
							MX51_PAD_KEY_COL2__KEY_COL2 0xe8
							MX51_PAD_KEY_COL3__KEY_COL3 0xe8
						>;
					};
				};
			};

			pwm1: pwm@73fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
				reg = <0x73fb4000 0x4000>;
				clocks = <&clks 37>, <&clks 38>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@73fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
				reg = <0x73fb8000 0x4000>;
				clocks = <&clks 39>, <&clks 40>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@73fbc000 {
				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
				reg = <0x73fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks 28>, <&clks 29>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@73fc0000 {
				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
				reg = <0x73fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks 30>, <&clks 31>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			clks: ccm@73fd4000{
				compatible = "fsl,imx51-ccm";
				reg = <0x73fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};
		};

		aips@80000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80000000 0x10000000>;
			ranges;

			ecspi2: ecspi@83fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-ecspi";
				reg = <0x83fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks 53>, <&clks 54>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@83fb0000 {
				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
				reg = <0x83fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks 56>, <&clks 56>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
			};

			cspi: cspi@83fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
				reg = <0x83fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks 55>, <&clks 0>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@83fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
				reg = <0x83fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks 35>;
				status = "disabled";
			};

			i2c1: i2c@83fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
				reg = <0x83fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks 34>;
				status = "disabled";
			};

			ssi1: ssi@83fcc000 {
				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
				reg = <0x83fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks 48>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@83fd0000 {
				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
				reg = <0x83fd0000 0x4000>;
				status = "disabled";
			};

			nfc: nand@83fdb000 {
				compatible = "fsl,imx51-nand";
				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
				interrupts = <8>;
				clocks = <&clks 60>;
				status = "disabled";
			};

			ssi3: ssi@83fe8000 {
				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
				reg = <0x83fe8000 0x4000>;
				interrupts = <96>;
				clocks = <&clks 50>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			fec: ethernet@83fec000 {
				compatible = "fsl,imx51-fec", "fsl,imx27-fec";
				reg = <0x83fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks 42>, <&clks 42>, <&clks 42>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
9daaf31a SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
36dffd8f	13	#include "skeleton.dtsi"
e1641531	14	#include "imx51-pinfunc.h"
9daaf31a SG	15
	16	/ {
	17	aliases {
8f9ffecf RZ	18	serial0 = &uart1;
	19	serial1 = &uart2;
	20	serial2 = &uart3;
5230f8fe SG	21	gpio0 = &gpio1;
	22	gpio1 = &gpio2;
	23	gpio2 = &gpio3;
	24	gpio3 = &gpio4;
9daaf31a SG	25	};
	26
	27	tzic: tz-interrupt-controller@e0000000 {
	28	compatible = "fsl,imx51-tzic", "fsl,tzic";
	29	interrupt-controller;
	30	#interrupt-cells = <1>;
	31	reg = <0xe0000000 0x4000>;
	32	};
	33
	34	clocks {
	35	#address-cells = <1>;
	36	#size-cells = <0>;
	37
	38	ckil {
	39	compatible = "fsl,imx-ckil", "fixed-clock";
	40	clock-frequency = <32768>;
	41	};
	42
	43	ckih1 {
	44	compatible = "fsl,imx-ckih1", "fixed-clock";
	45	clock-frequency = <22579200>;
	46	};
	47
	48	ckih2 {
	49	compatible = "fsl,imx-ckih2", "fixed-clock";
	50	clock-frequency = <0>;
	51	};
	52
	53	osc {
	54	compatible = "fsl,imx-osc", "fixed-clock";
	55	clock-frequency = <24000000>;
	56	};
	57	};
	58
	59	soc {
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62	compatible = "simple-bus";
	63	interrupt-parent = <&tzic>;
	64	ranges;
	65
b5af6b10 SH	66	ipu: ipu@40000000 {
	67	#crtc-cells = <1>;
	68	compatible = "fsl,imx51-ipu";
	69	reg = <0x40000000 0x20000000>;
	70	interrupts = <11 10>;
4438a6a1 PZ	71	clocks = <&clks 59>, <&clks 110>, <&clks 61>;
4438a6a1 PZ	72	clock-names = "bus", "di0", "di1";
b5af6b10 SH	73	};
b5af6b10 SH	74
9daaf31a SG	75	aips@70000000 { /* AIPS1 */
	76	compatible = "fsl,aips-bus", "simple-bus";
	77	#address-cells = <1>;
	78	#size-cells = <1>;
	79	reg = <0x70000000 0x10000000>;
	80	ranges;
	81
	82	spba@70000000 {
	83	compatible = "fsl,spba-bus", "simple-bus";
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	reg = <0x70000000 0x40000>;
	87	ranges;
	88
7b7d6727	89	esdhc1: esdhc@70004000 {
9daaf31a SG	90	compatible = "fsl,imx51-esdhc";
	91	reg = <0x70004000 0x4000>;
	92	interrupts = <1>;
f40f38d1 FE	93	clocks = <&clks 44>, <&clks 0>, <&clks 71>;
f40f38d1 FE	94	clock-names = "ipg", "ahb", "per";
9daaf31a SG	95	status = "disabled";
	96	};
	97
7b7d6727	98	esdhc2: esdhc@70008000 {
9daaf31a SG	99	compatible = "fsl,imx51-esdhc";
	100	reg = <0x70008000 0x4000>;
	101	interrupts = <2>;
f40f38d1 FE	102	clocks = <&clks 45>, <&clks 0>, <&clks 72>;
f40f38d1 FE	103	clock-names = "ipg", "ahb", "per";
c104b6a2	104	bus-width = <4>;
9daaf31a SG	105	status = "disabled";
	106	};
	107
0c456cfa	108	uart3: serial@7000c000 {
9daaf31a SG	109	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	110	reg = <0x7000c000 0x4000>;
	111	interrupts = <33>;
f40f38d1 FE	112	clocks = <&clks 32>, <&clks 33>;
f40f38d1 FE	113	clock-names = "ipg", "per";
9daaf31a SG	114	status = "disabled";
	115	};
	116
7b7d6727	117	ecspi1: ecspi@70010000 {
9daaf31a SG	118	#address-cells = <1>;
	119	#size-cells = <0>;
	120	compatible = "fsl,imx51-ecspi";
	121	reg = <0x70010000 0x4000>;
	122	interrupts = <36>;
f40f38d1 FE	123	clocks = <&clks 51>, <&clks 52>;
f40f38d1 FE	124	clock-names = "ipg", "per";
9daaf31a SG	125	status = "disabled";
	126	};
	127
a15d9f89 SG	128	ssi2: ssi@70014000 {
	129	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	130	reg = <0x70014000 0x4000>;
	131	interrupts = <30>;
f40f38d1	132	clocks = <&clks 49>;
a15d9f89 SG	133	fsl,fifo-depth = <15>;
	134	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	135	status = "disabled";
	136	};
	137
7b7d6727	138	esdhc3: esdhc@70020000 {
9daaf31a SG	139	compatible = "fsl,imx51-esdhc";
	140	reg = <0x70020000 0x4000>;
	141	interrupts = <3>;
f40f38d1 FE	142	clocks = <&clks 46>, <&clks 0>, <&clks 73>;
f40f38d1 FE	143	clock-names = "ipg", "ahb", "per";
c104b6a2	144	bus-width = <4>;
9daaf31a SG	145	status = "disabled";
	146	};
	147
7b7d6727	148	esdhc4: esdhc@70024000 {
9daaf31a SG	149	compatible = "fsl,imx51-esdhc";
	150	reg = <0x70024000 0x4000>;
	151	interrupts = <4>;
f40f38d1 FE	152	clocks = <&clks 47>, <&clks 0>, <&clks 74>;
f40f38d1 FE	153	clock-names = "ipg", "ahb", "per";
c104b6a2	154	bus-width = <4>;
9daaf31a SG	155	status = "disabled";
	156	};
	157	};
	158
7b7d6727	159	usbotg: usb@73f80000 {
212d0b83 MG	160	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	161	reg = <0x73f80000 0x0200>;
	162	interrupts = <18>;
	163	status = "disabled";
	164	};
	165
7b7d6727	166	usbh1: usb@73f80200 {
212d0b83 MG	167	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	168	reg = <0x73f80200 0x0200>;
	169	interrupts = <14>;
	170	status = "disabled";
	171	};
	172
7b7d6727	173	usbh2: usb@73f80400 {
212d0b83 MG	174	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	175	reg = <0x73f80400 0x0200>;
	176	interrupts = <16>;
	177	status = "disabled";
	178	};
	179
7b7d6727	180	usbh3: usb@73f80600 {
212d0b83 MG	181	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	182	reg = <0x73f80600 0x0200>;
	183	interrupts = <17>;
	184	status = "disabled";
	185	};
	186
4d191868	187	gpio1: gpio@73f84000 {
aeb27748	188	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	189	reg = <0x73f84000 0x4000>;
	190	interrupts = <50 51>;
	191	gpio-controller;
	192	#gpio-cells = <2>;
	193	interrupt-controller;
88cde8b7	194	#interrupt-cells = <2>;
9daaf31a SG	195	};
9daaf31a SG	196
4d191868	197	gpio2: gpio@73f88000 {
aeb27748	198	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	199	reg = <0x73f88000 0x4000>;
	200	interrupts = <52 53>;
	201	gpio-controller;
	202	#gpio-cells = <2>;
	203	interrupt-controller;
88cde8b7	204	#interrupt-cells = <2>;
9daaf31a SG	205	};
9daaf31a SG	206
4d191868	207	gpio3: gpio@73f8c000 {
aeb27748	208	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	209	reg = <0x73f8c000 0x4000>;
	210	interrupts = <54 55>;
	211	gpio-controller;
	212	#gpio-cells = <2>;
	213	interrupt-controller;
88cde8b7	214	#interrupt-cells = <2>;
9daaf31a SG	215	};
9daaf31a SG	216
4d191868	217	gpio4: gpio@73f90000 {
aeb27748	218	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	219	reg = <0x73f90000 0x4000>;
	220	interrupts = <56 57>;
	221	gpio-controller;
	222	#gpio-cells = <2>;
	223	interrupt-controller;
88cde8b7	224	#interrupt-cells = <2>;
9daaf31a SG	225	};
9daaf31a SG	226
6012555c LY	227	kpp: kpp@73f94000 {
	228	compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
	229	reg = <0x73f94000 0x4000>;
	230	interrupts = <60>;
	231	clocks = <&clks 0>;
	232	status = "disabled";
	233	};
	234
7b7d6727	235	wdog1: wdog@73f98000 {
9daaf31a SG	236	compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
	237	reg = <0x73f98000 0x4000>;
	238	interrupts = <58>;
f40f38d1	239	clocks = <&clks 0>;
9daaf31a SG	240	};
9daaf31a SG	241
7b7d6727	242	wdog2: wdog@73f9c000 {
9daaf31a SG	243	compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
	244	reg = <0x73f9c000 0x4000>;
	245	interrupts = <59>;
f40f38d1	246	clocks = <&clks 0>;
9daaf31a SG	247	status = "disabled";
	248	};
	249
ed73c63a SH	250	gpt: timer@73fa0000 {
	251	compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
	252	reg = <0x73fa0000 0x4000>;
	253	interrupts = <39>;
	254	clocks = <&clks 36>, <&clks 41>;
	255	clock-names = "ipg", "per";
	256	};
	257
7b7d6727	258	iomuxc: iomuxc@73fa8000 {
b72cf105 SG	259	compatible = "fsl,imx51-iomuxc";
	260	reg = <0x73fa8000 0x4000>;
	261
	262	audmux {
	263	pinctrl_audmux_1: audmuxgrp-1 {
	264	fsl,pins = <
e1641531 SG	265	MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
	266	MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
	267	MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
	268	MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
b72cf105 SG	269	>;
	270	};
	271	};
	272
	273	fec {
	274	pinctrl_fec_1: fecgrp-1 {
	275	fsl,pins = <
e1641531 SG	276	MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
	277	MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
	278	MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
	279	MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
	280	MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
	281	MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
	282	MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
	283	MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
	284	MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
	285	MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
	286	MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
	287	MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
	288	MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
	289	MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
	290	MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
	291	MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
	292	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
b72cf105 SG	293	>;
b72cf105 SG	294	};
1982d5b6 LC	295
	296	pinctrl_fec_2: fecgrp-2 {
	297	fsl,pins = <
e1641531 SG	298	MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
	299	MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
	300	MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
	301	MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
	302	MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
	303	MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
	304	MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
	305	MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
	306	MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
	307	MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
	308	MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
	309	MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
	310	MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
	311	MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
	312	MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
	313	MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
	314	MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
	315	MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
1982d5b6 LC	316	>;
1982d5b6 LC	317	};
b72cf105 SG	318	};
	319
	320	ecspi1 {
	321	pinctrl_ecspi1_1: ecspi1grp-1 {
	322	fsl,pins = <
e1641531 SG	323	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	324	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	325	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
b72cf105 SG	326	>;
	327	};
	328	};
	329
a15ac4a6 GGM	330	ecspi2 {
	331	pinctrl_ecspi2_1: ecspi2grp-1 {
	332	fsl,pins = <
	333	MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
	334	MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
	335	MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
	336	>;
	337	};
	338	};
	339
b72cf105 SG	340	esdhc1 {
	341	pinctrl_esdhc1_1: esdhc1grp-1 {
	342	fsl,pins = <
e1641531 SG	343	MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
	344	MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
	345	MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
	346	MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
	347	MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
	348	MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
b72cf105 SG	349	>;
	350	};
	351	};
	352
	353	esdhc2 {
	354	pinctrl_esdhc2_1: esdhc2grp-1 {
	355	fsl,pins = <
e1641531 SG	356	MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
	357	MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
	358	MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
	359	MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
	360	MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
	361	MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
b72cf105 SG	362	>;
	363	};
	364	};
	365
	366	i2c2 {
	367	pinctrl_i2c2_1: i2c2grp-1 {
	368	fsl,pins = <
e1641531 SG	369	MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
e1641531 SG	370	MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
b72cf105 SG	371	>;
b72cf105 SG	372	};
52c9aa94 GGM	373
	374	pinctrl_i2c2_2: i2c2grp-2 {
	375	fsl,pins = <
	376	MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
	377	MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
	378	>;
	379	};
b72cf105 SG	380	};
b72cf105 SG	381
b5af6b10 SH	382	ipu_disp1 {
	383	pinctrl_ipu_disp1_1: ipudisp1grp-1 {
	384	fsl,pins = <
e1641531 SG	385	MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
	386	MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
	387	MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
	388	MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
	389	MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
	390	MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
	391	MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
	392	MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
	393	MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
	394	MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
	395	MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
	396	MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
	397	MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
	398	MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
	399	MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
	400	MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
	401	MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
	402	MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
	403	MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
	404	MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
	405	MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
	406	MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
	407	MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
	408	MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
	409	MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
	410	MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
b5af6b10 SH	411	>;
	412	};
	413	};
	414
	415	ipu_disp2 {
	416	pinctrl_ipu_disp2_1: ipudisp2grp-1 {
	417	fsl,pins = <
e1641531 SG	418	MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
	419	MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
	420	MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
	421	MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
	422	MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
	423	MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
	424	MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
	425	MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
	426	MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
	427	MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
	428	MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
	429	MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
	430	MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
	431	MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
	432	MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
	433	MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
	434	MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
	435	MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
	436	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
	437	MX51_PAD_DI_GP4__DI2_PIN15 0x5
b5af6b10 SH	438	>;
	439	};
	440	};
	441
b72cf105 SG	442	uart1 {
	443	pinctrl_uart1_1: uart1grp-1 {
	444	fsl,pins = <
e1641531 SG	445	MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
	446	MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
	447	MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
	448	MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
b72cf105 SG	449	>;
	450	};
	451	};
	452
	453	uart2 {
	454	pinctrl_uart2_1: uart2grp-1 {
	455	fsl,pins = <
e1641531 SG	456	MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
e1641531 SG	457	MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
b72cf105 SG	458	>;
	459	};
	460	};
	461
	462	uart3 {
	463	pinctrl_uart3_1: uart3grp-1 {
	464	fsl,pins = <
e1641531 SG	465	MX51_PAD_EIM_D25__UART3_RXD 0x1c5
	466	MX51_PAD_EIM_D26__UART3_TXD 0x1c5
	467	MX51_PAD_EIM_D27__UART3_RTS 0x1c5
	468	MX51_PAD_EIM_D24__UART3_CTS 0x1c5
b72cf105 SG	469	>;
b72cf105 SG	470	};
1982d5b6 LC	471
	472	pinctrl_uart3_2: uart3grp-2 {
	473	fsl,pins = <
e1641531 SG	474	MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
e1641531 SG	475	MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
1982d5b6 LC	476	>;
1982d5b6 LC	477	};
b72cf105	478	};
6012555c LY	479
	480	kpp {
	481	pinctrl_kpp_1: kppgrp-1 {
	482	fsl,pins = <
e1641531 SG	483	MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
	484	MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
	485	MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
	486	MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
	487	MX51_PAD_KEY_COL0__KEY_COL0 0xe8
	488	MX51_PAD_KEY_COL1__KEY_COL1 0xe8
	489	MX51_PAD_KEY_COL2__KEY_COL2 0xe8
	490	MX51_PAD_KEY_COL3__KEY_COL3 0xe8
6012555c LY	491	>;
	492	};
	493	};
b72cf105 SG	494	};
b72cf105 SG	495
82a618da SH	496	pwm1: pwm@73fb4000 {
	497	#pwm-cells = <2>;
	498	compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
	499	reg = <0x73fb4000 0x4000>;
	500	clocks = <&clks 37>, <&clks 38>;
	501	clock-names = "ipg", "per";
	502	interrupts = <61>;
	503	};
	504
	505	pwm2: pwm@73fb8000 {
	506	#pwm-cells = <2>;
	507	compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
	508	reg = <0x73fb8000 0x4000>;
	509	clocks = <&clks 39>, <&clks 40>;
	510	clock-names = "ipg", "per";
	511	interrupts = <94>;
	512	};
	513
0c456cfa	514	uart1: serial@73fbc000 {
9daaf31a SG	515	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	516	reg = <0x73fbc000 0x4000>;
	517	interrupts = <31>;
f40f38d1 FE	518	clocks = <&clks 28>, <&clks 29>;
f40f38d1 FE	519	clock-names = "ipg", "per";
9daaf31a SG	520	status = "disabled";
	521	};
	522
0c456cfa	523	uart2: serial@73fc0000 {
9daaf31a SG	524	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	525	reg = <0x73fc0000 0x4000>;
	526	interrupts = <32>;
f40f38d1 FE	527	clocks = <&clks 30>, <&clks 31>;
f40f38d1 FE	528	clock-names = "ipg", "per";
9daaf31a SG	529	status = "disabled";
9daaf31a SG	530	};
f40f38d1 FE	531
	532	clks: ccm@73fd4000{
	533	compatible = "fsl,imx51-ccm";
	534	reg = <0x73fd4000 0x4000>;
	535	interrupts = <0 71 0x04 0 72 0x04>;
	536	#clock-cells = <1>;
	537	};
9daaf31a SG	538	};
	539
	540	aips@80000000 { /* AIPS2 */
	541	compatible = "fsl,aips-bus", "simple-bus";
	542	#address-cells = <1>;
	543	#size-cells = <1>;
	544	reg = <0x80000000 0x10000000>;
	545	ranges;
	546
7b7d6727	547	ecspi2: ecspi@83fac000 {
9daaf31a SG	548	#address-cells = <1>;
	549	#size-cells = <0>;
	550	compatible = "fsl,imx51-ecspi";
	551	reg = <0x83fac000 0x4000>;
	552	interrupts = <37>;
f40f38d1 FE	553	clocks = <&clks 53>, <&clks 54>;
f40f38d1 FE	554	clock-names = "ipg", "per";
9daaf31a SG	555	status = "disabled";
	556	};
	557
7b7d6727	558	sdma: sdma@83fb0000 {
9daaf31a SG	559	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	560	reg = <0x83fb0000 0x4000>;
	561	interrupts = <6>;
f40f38d1 FE	562	clocks = <&clks 56>, <&clks 56>;
f40f38d1 FE	563	clock-names = "ipg", "ahb";
7e4f0365	564	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
9daaf31a SG	565	};
9daaf31a SG	566
7b7d6727	567	cspi: cspi@83fc0000 {
9daaf31a SG	568	#address-cells = <1>;
	569	#size-cells = <0>;
	570	compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
	571	reg = <0x83fc0000 0x4000>;
	572	interrupts = <38>;
f40f38d1 FE	573	clocks = <&clks 55>, <&clks 0>;
f40f38d1 FE	574	clock-names = "ipg", "per";
9daaf31a SG	575	status = "disabled";
	576	};
	577
7b7d6727	578	i2c2: i2c@83fc4000 {
9daaf31a SG	579	#address-cells = <1>;
9daaf31a SG	580	#size-cells = <0>;
5bdfba29	581	compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
9daaf31a SG	582	reg = <0x83fc4000 0x4000>;
9daaf31a SG	583	interrupts = <63>;
f40f38d1	584	clocks = <&clks 35>;
9daaf31a SG	585	status = "disabled";
	586	};
	587
7b7d6727	588	i2c1: i2c@83fc8000 {
9daaf31a SG	589	#address-cells = <1>;
9daaf31a SG	590	#size-cells = <0>;
5bdfba29	591	compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
9daaf31a SG	592	reg = <0x83fc8000 0x4000>;
9daaf31a SG	593	interrupts = <62>;
f40f38d1	594	clocks = <&clks 34>;
9daaf31a SG	595	status = "disabled";
	596	};
	597
a15d9f89 SG	598	ssi1: ssi@83fcc000 {
	599	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	600	reg = <0x83fcc000 0x4000>;
	601	interrupts = <29>;
f40f38d1	602	clocks = <&clks 48>;
a15d9f89 SG	603	fsl,fifo-depth = <15>;
	604	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	605	status = "disabled";
	606	};
	607
7b7d6727	608	audmux: audmux@83fd0000 {
a15d9f89 SG	609	compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
	610	reg = <0x83fd0000 0x4000>;
	611	status = "disabled";
	612	};
	613
7b7d6727	614	nfc: nand@83fdb000 {
75453a08 SH	615	compatible = "fsl,imx51-nand";
	616	reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
	617	interrupts = <8>;
f40f38d1	618	clocks = <&clks 60>;
75453a08 SH	619	status = "disabled";
	620	};
	621
a15d9f89 SG	622	ssi3: ssi@83fe8000 {
	623	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	624	reg = <0x83fe8000 0x4000>;
	625	interrupts = <96>;
f40f38d1	626	clocks = <&clks 50>;
a15d9f89 SG	627	fsl,fifo-depth = <15>;
	628	fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
	629	status = "disabled";
	630	};
	631
7b7d6727	632	fec: ethernet@83fec000 {
9daaf31a SG	633	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	634	reg = <0x83fec000 0x4000>;
	635	interrupts = <87>;
f40f38d1 FE	636	clocks = <&clks 42>, <&clks 42>, <&clks 42>;
f40f38d1 FE	637	clock-names = "ipg", "ahb", "ptp";
9daaf31a SG	638	status = "disabled";
	639	};
	640	};
	641	};
	642	};