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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /include/ "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
8f9ffecf RZ |
17 | serial0 = &uart1; |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
5230f8fe SG |
20 | gpio0 = &gpio1; |
21 | gpio1 = &gpio2; | |
22 | gpio2 = &gpio3; | |
23 | gpio3 = &gpio4; | |
9daaf31a SG |
24 | }; |
25 | ||
26 | tzic: tz-interrupt-controller@e0000000 { | |
27 | compatible = "fsl,imx51-tzic", "fsl,tzic"; | |
28 | interrupt-controller; | |
29 | #interrupt-cells = <1>; | |
30 | reg = <0xe0000000 0x4000>; | |
31 | }; | |
32 | ||
33 | clocks { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | ckil { | |
38 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
39 | clock-frequency = <32768>; | |
40 | }; | |
41 | ||
42 | ckih1 { | |
43 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
44 | clock-frequency = <22579200>; | |
45 | }; | |
46 | ||
47 | ckih2 { | |
48 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
49 | clock-frequency = <0>; | |
50 | }; | |
51 | ||
52 | osc { | |
53 | compatible = "fsl,imx-osc", "fixed-clock"; | |
54 | clock-frequency = <24000000>; | |
55 | }; | |
56 | }; | |
57 | ||
58 | soc { | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | compatible = "simple-bus"; | |
62 | interrupt-parent = <&tzic>; | |
63 | ranges; | |
64 | ||
65 | aips@70000000 { /* AIPS1 */ | |
66 | compatible = "fsl,aips-bus", "simple-bus"; | |
67 | #address-cells = <1>; | |
68 | #size-cells = <1>; | |
69 | reg = <0x70000000 0x10000000>; | |
70 | ranges; | |
71 | ||
72 | spba@70000000 { | |
73 | compatible = "fsl,spba-bus", "simple-bus"; | |
74 | #address-cells = <1>; | |
75 | #size-cells = <1>; | |
76 | reg = <0x70000000 0x40000>; | |
77 | ranges; | |
78 | ||
79 | esdhc@70004000 { /* ESDHC1 */ | |
80 | compatible = "fsl,imx51-esdhc"; | |
81 | reg = <0x70004000 0x4000>; | |
82 | interrupts = <1>; | |
83 | status = "disabled"; | |
84 | }; | |
85 | ||
86 | esdhc@70008000 { /* ESDHC2 */ | |
87 | compatible = "fsl,imx51-esdhc"; | |
88 | reg = <0x70008000 0x4000>; | |
89 | interrupts = <2>; | |
90 | status = "disabled"; | |
91 | }; | |
92 | ||
0c456cfa | 93 | uart3: serial@7000c000 { |
9daaf31a SG |
94 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
95 | reg = <0x7000c000 0x4000>; | |
96 | interrupts = <33>; | |
97 | status = "disabled"; | |
98 | }; | |
99 | ||
100 | ecspi@70010000 { /* ECSPI1 */ | |
101 | #address-cells = <1>; | |
102 | #size-cells = <0>; | |
103 | compatible = "fsl,imx51-ecspi"; | |
104 | reg = <0x70010000 0x4000>; | |
105 | interrupts = <36>; | |
106 | status = "disabled"; | |
107 | }; | |
108 | ||
a15d9f89 SG |
109 | ssi2: ssi@70014000 { |
110 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
111 | reg = <0x70014000 0x4000>; | |
112 | interrupts = <30>; | |
113 | fsl,fifo-depth = <15>; | |
114 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
115 | status = "disabled"; | |
116 | }; | |
117 | ||
9daaf31a SG |
118 | esdhc@70020000 { /* ESDHC3 */ |
119 | compatible = "fsl,imx51-esdhc"; | |
120 | reg = <0x70020000 0x4000>; | |
121 | interrupts = <3>; | |
122 | status = "disabled"; | |
123 | }; | |
124 | ||
125 | esdhc@70024000 { /* ESDHC4 */ | |
126 | compatible = "fsl,imx51-esdhc"; | |
127 | reg = <0x70024000 0x4000>; | |
128 | interrupts = <4>; | |
129 | status = "disabled"; | |
130 | }; | |
131 | }; | |
132 | ||
4d191868 | 133 | gpio1: gpio@73f84000 { |
aeb27748 | 134 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
135 | reg = <0x73f84000 0x4000>; |
136 | interrupts = <50 51>; | |
137 | gpio-controller; | |
138 | #gpio-cells = <2>; | |
139 | interrupt-controller; | |
88cde8b7 | 140 | #interrupt-cells = <2>; |
9daaf31a SG |
141 | }; |
142 | ||
4d191868 | 143 | gpio2: gpio@73f88000 { |
aeb27748 | 144 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
145 | reg = <0x73f88000 0x4000>; |
146 | interrupts = <52 53>; | |
147 | gpio-controller; | |
148 | #gpio-cells = <2>; | |
149 | interrupt-controller; | |
88cde8b7 | 150 | #interrupt-cells = <2>; |
9daaf31a SG |
151 | }; |
152 | ||
4d191868 | 153 | gpio3: gpio@73f8c000 { |
aeb27748 | 154 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
155 | reg = <0x73f8c000 0x4000>; |
156 | interrupts = <54 55>; | |
157 | gpio-controller; | |
158 | #gpio-cells = <2>; | |
159 | interrupt-controller; | |
88cde8b7 | 160 | #interrupt-cells = <2>; |
9daaf31a SG |
161 | }; |
162 | ||
4d191868 | 163 | gpio4: gpio@73f90000 { |
aeb27748 | 164 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
165 | reg = <0x73f90000 0x4000>; |
166 | interrupts = <56 57>; | |
167 | gpio-controller; | |
168 | #gpio-cells = <2>; | |
169 | interrupt-controller; | |
88cde8b7 | 170 | #interrupt-cells = <2>; |
9daaf31a SG |
171 | }; |
172 | ||
173 | wdog@73f98000 { /* WDOG1 */ | |
174 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; | |
175 | reg = <0x73f98000 0x4000>; | |
176 | interrupts = <58>; | |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
180 | wdog@73f9c000 { /* WDOG2 */ | |
181 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; | |
182 | reg = <0x73f9c000 0x4000>; | |
183 | interrupts = <59>; | |
184 | status = "disabled"; | |
185 | }; | |
186 | ||
0c456cfa | 187 | uart1: serial@73fbc000 { |
9daaf31a SG |
188 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
189 | reg = <0x73fbc000 0x4000>; | |
190 | interrupts = <31>; | |
191 | status = "disabled"; | |
192 | }; | |
193 | ||
0c456cfa | 194 | uart2: serial@73fc0000 { |
9daaf31a SG |
195 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
196 | reg = <0x73fc0000 0x4000>; | |
197 | interrupts = <32>; | |
198 | status = "disabled"; | |
199 | }; | |
200 | }; | |
201 | ||
202 | aips@80000000 { /* AIPS2 */ | |
203 | compatible = "fsl,aips-bus", "simple-bus"; | |
204 | #address-cells = <1>; | |
205 | #size-cells = <1>; | |
206 | reg = <0x80000000 0x10000000>; | |
207 | ranges; | |
208 | ||
209 | ecspi@83fac000 { /* ECSPI2 */ | |
210 | #address-cells = <1>; | |
211 | #size-cells = <0>; | |
212 | compatible = "fsl,imx51-ecspi"; | |
213 | reg = <0x83fac000 0x4000>; | |
214 | interrupts = <37>; | |
215 | status = "disabled"; | |
216 | }; | |
217 | ||
218 | sdma@83fb0000 { | |
219 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; | |
220 | reg = <0x83fb0000 0x4000>; | |
221 | interrupts = <6>; | |
222 | }; | |
223 | ||
224 | cspi@83fc0000 { | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; | |
228 | reg = <0x83fc0000 0x4000>; | |
229 | interrupts = <38>; | |
230 | status = "disabled"; | |
231 | }; | |
232 | ||
233 | i2c@83fc4000 { /* I2C2 */ | |
234 | #address-cells = <1>; | |
235 | #size-cells = <0>; | |
236 | compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; | |
237 | reg = <0x83fc4000 0x4000>; | |
238 | interrupts = <63>; | |
239 | status = "disabled"; | |
240 | }; | |
241 | ||
242 | i2c@83fc8000 { /* I2C1 */ | |
243 | #address-cells = <1>; | |
244 | #size-cells = <0>; | |
245 | compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; | |
246 | reg = <0x83fc8000 0x4000>; | |
247 | interrupts = <62>; | |
248 | status = "disabled"; | |
249 | }; | |
250 | ||
a15d9f89 SG |
251 | ssi1: ssi@83fcc000 { |
252 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
253 | reg = <0x83fcc000 0x4000>; | |
254 | interrupts = <29>; | |
255 | fsl,fifo-depth = <15>; | |
256 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
260 | audmux@83fd0000 { | |
261 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; | |
262 | reg = <0x83fd0000 0x4000>; | |
263 | status = "disabled"; | |
264 | }; | |
265 | ||
266 | ssi3: ssi@83fe8000 { | |
267 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
268 | reg = <0x83fe8000 0x4000>; | |
269 | interrupts = <96>; | |
270 | fsl,fifo-depth = <15>; | |
271 | fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ | |
272 | status = "disabled"; | |
273 | }; | |
274 | ||
0c456cfa | 275 | ethernet@83fec000 { |
9daaf31a SG |
276 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
277 | reg = <0x83fec000 0x4000>; | |
278 | interrupts = <87>; | |
279 | status = "disabled"; | |
280 | }; | |
281 | }; | |
282 | }; | |
283 | }; |