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ARM: dts: imx27 pin functions
[deliverable/linux.git] / arch / arm / boot / dts / imx53-m53evk.dts
CommitLineData
051124e5
MV		 1/*
2 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx53.dtsi"
14
15/ {
16 model = "DENX M53EVK";
17 compatible = "denx,imx53-m53evk", "fsl,imx53";
18
19 memory {
20 reg = <0x70000000 0x20000000>;
21 };
22
23 soc {
24 display@di1 {
25 compatible = "fsl,imx-parallel-display";
26 crtcs = <&ipu 1>;
27 interface-pix-fmt = "bgr666";
28 pinctrl-names = "default";
7ac0f700 29 pinctrl-0 = <&pinctrl_ipu_disp2>;
051124e5
MV		 30
31 display-timings {
32 800x480p60 {
33 native-mode;
34 clock-frequency = <31500000>;
35 hactive = <800>;
36 vactive = <480>;
37 hfront-porch = <40>;
38 hback-porch = <88>;
39 hsync-len = <128>;
40 vback-porch = <33>;
41 vfront-porch = <9>;
42 vsync-len = <3>;
43 vsync-active = <1>;
44 };
45 };
46 };
47 };
48
49 backlight {
50 compatible = "pwm-backlight";
51 pwms = <&pwm1 0 3000>;
52 brightness-levels = <0 4 8 16 32 64 128 255>;
53 default-brightness-level = <6>;
54 };
55
56 leds {
57 compatible = "gpio-leds";
58 pinctrl-names = "default";
59 pinctrl-0 = <&led_pin_gpio>;
60
61 user1 {
62 label = "user1";
63 gpios = <&gpio2 8 0>;
64 linux,default-trigger = "heartbeat";
65 };
66
67 user2 {
68 label = "user2";
69 gpios = <&gpio2 9 0>;
70 linux,default-trigger = "heartbeat";
71 };
72 };
73
74 regulators {
75 compatible = "simple-bus";
352d318c
SG		 76 #address-cells = <1>;
77 #size-cells = <0>;
051124e5 78
352d318c 79 reg_3p2v: regulator@0 {
051124e5 80 compatible = "regulator-fixed";
352d318c 81 reg = <0>;
051124e5
MV		 82 regulator-name = "3P2V";
83 regulator-min-microvolt = <3200000>;
84 regulator-max-microvolt = <3200000>;
85 regulator-always-on;
86 };
87 };
88
89 sound {
90 compatible = "fsl,imx53-m53evk-sgtl5000",
91 "fsl,imx-audio-sgtl5000";
92 model = "imx53-m53evk-sgtl5000";
93 ssi-controller = <&ssi2>;
94 audio-codec = <&sgtl5000>;
95 audio-routing =
96 "MIC_IN", "Mic Jack",
97 "Mic Jack", "Mic Bias",
98 "LINE_IN", "Line In Jack",
99 "Headphone Jack", "HP_OUT",
100 "Ext Spk", "LINE_OUT";
101 mux-int-port = <2>;
102 mux-ext-port = <4>;
103 };
104};
105
106&audmux {
107 pinctrl-names = "default";
7ac0f700 108 pinctrl-0 = <&pinctrl_audmux>;
051124e5
MV		 109 status = "okay";
110};
111
112&can1 {
113 pinctrl-names = "default";
7ac0f700 114 pinctrl-0 = <&pinctrl_can1>;
051124e5
MV		 115 status = "okay";
116};
117
118&can2 {
119 pinctrl-names = "default";
7ac0f700 120 pinctrl-0 = <&pinctrl_can2>;
051124e5
MV		 121 status = "okay";
122};
123
124&esdhc1 {
125 pinctrl-names = "default";
7ac0f700 126 pinctrl-0 = <&pinctrl_esdhc1>;
051124e5
MV		 127 cd-gpios = <&gpio1 1 0>;
128 wp-gpios = <&gpio1 9 0>;
129 status = "okay";
130};
131
132&fec {
133 pinctrl-names = "default";
7ac0f700 134 pinctrl-0 = <&pinctrl_fec>;
051124e5
MV		 135 phy-mode = "rmii";
136 status = "okay";
137};
138
139&i2c1 {
140 pinctrl-names = "default";
7ac0f700 141 pinctrl-0 = <&pinctrl_i2c1>;
051124e5
MV		 142 status = "okay";
143
144 sgtl5000: codec@0a {
145 compatible = "fsl,sgtl5000";
146 reg = <0x0a>;
147 VDDA-supply = <&reg_3p2v>;
148 VDDIO-supply = <&reg_3p2v>;
149 clocks = <&clks 150>;
150 };
151};
152
153&i2c2 {
154 pinctrl-names = "default";
7ac0f700 155 pinctrl-0 = <&pinctrl_i2c2>;
051124e5
MV		 156 clock-frequency = <400000>;
157 status = "okay";
158
159 stmpe610@41 {
160 compatible = "st,stmpe610";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg = <0x41>;
164 id = <0>;
165 blocks = <0x5>;
166 interrupts = <6 0x0>;
167 interrupt-parent = <&gpio7>;
168 irq-trigger = <0x1>;
169
170 stmpe_touchscreen {
171 compatible = "stmpe,ts";
172 reg = <0>;
173 ts,sample-time = <4>;
174 ts,mod-12b = <1>;
175 ts,ref-sel = <0>;
176 ts,adc-freq = <1>;
177 ts,ave-ctrl = <3>;
178 ts,touch-det-delay = <3>;
179 ts,settling = <4>;
180 ts,fraction-z = <7>;
181 ts,i-drive = <1>;
182 };
183 };
184
185 eeprom: eeprom@50 {
186 compatible = "atmel,24c128";
187 reg = <0x50>;
188 pagesize = <32>;
189 };
190
191 rtc: rtc@68 {
192 compatible = "stm,m41t62";
193 reg = <0x68>;
194 };
195};
196
197&i2c3 {
198 pinctrl-names = "default";
7ac0f700 199 pinctrl-0 = <&pinctrl_i2c3>;
051124e5
MV		 200 status = "okay";
201};
202
203&iomuxc {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_hog>;
206
7ac0f700 207 imx53-m53evk {
051124e5
MV		 208 pinctrl_hog: hoggrp {
209 fsl,pins = <
210 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
211 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
212 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
213 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
214
215 >;
216 };
217
218 led_pin_gpio: led_gpio@0 {
219 fsl,pins = <
220 MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
221 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
222 >;
223 };
7ac0f700
SG		 224
225 pinctrl_audmux: audmuxgrp {
226 fsl,pins = <
227 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
228 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
229 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
230 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
231 >;
232 };
233
234 pinctrl_can1: can1grp {
235 fsl,pins = <
236 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
237 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
238 >;
239 };
240
241 pinctrl_can2: can2grp {
242 fsl,pins = <
243 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
244 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
245 >;
246 };
247
248 pinctrl_esdhc1: esdhc1grp {
249 fsl,pins = <
250 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
251 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
252 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
253 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
254 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
255 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
256 >;
257 };
258
259 pinctrl_fec: fecgrp {
260 fsl,pins = <
261 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
262 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
263 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
264 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
265 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
266 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
267 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
268 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
269 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
270 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
271 >;
272 };
273
274 pinctrl_i2c1: i2c1grp {
275 fsl,pins = <
276 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
277 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
278 >;
279 };
280
281 pinctrl_i2c2: i2c2grp {
282 fsl,pins = <
283 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
284 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
285 >;
286 };
287
288 pinctrl_i2c3: i2c3grp {
289 fsl,pins = <
290 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
291 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
292 >;
293 };
294
295 pinctrl_ipu_disp2: ipudisp2grp {
296 fsl,pins = <
297 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
298 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
299 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
300 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
301 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
302 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
303 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
304 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
305 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
306 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
307 >;
308 };
309
310 pinctrl_nand: nandgrp {
311 fsl,pins = <
312 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
313 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
314 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
315 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
316 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
317 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
318 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
319 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
320 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
321 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
322 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
323 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
324 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
325 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
326 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
327 >;
328 };
329
330 pinctrl_pwm1: pwm1grp {
331 fsl,pins = <
332 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
333 >;
334 };
335
336 pinctrl_uart1: uart1grp {
337 fsl,pins = <
338 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
339 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
340 >;
341 };
342
343 pinctrl_uart2: uart2grp {
344 fsl,pins = <
345 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
346 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
347 >;
348 };
349
350 pinctrl_uart3: uart3grp {
351 fsl,pins = <
352 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
353 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
354 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
355 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
356 >;
357 };
051124e5
MV		 358 };
359};
360
361&nfc {
362 pinctrl-names = "default";
7ac0f700 363 pinctrl-0 = <&pinctrl_nand>;
051124e5
MV		 364 nand-bus-width = <8>;
365 nand-ecc-mode = "hw";
366 status = "okay";
367};
368
369&pwm1 {
370 pinctrl-names = "default";
7ac0f700 371 pinctrl-0 = <&pinctrl_pwm1>;
051124e5
MV		 372 status = "okay";
373};
374
375&ssi2 {
376 fsl,mode = "i2s-slave";
377 status = "okay";
378};
379
380&uart1 {
381 pinctrl-names = "default";
7ac0f700 382 pinctrl-0 = <&pinctrl_uart1>;
051124e5
MV		 383 status = "okay";
384};
385
386&uart2 {
387 pinctrl-names = "default";
7ac0f700 388 pinctrl-0 = <&pinctrl_uart2>;
051124e5
MV		 389 status = "okay";
390};
391
392&uart3 {
393 pinctrl-names = "default";
7ac0f700 394 pinctrl-0 = <&pinctrl_uart3>;
051124e5
MV		 395 status = "okay";
396};
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