Commit | Line | Data |
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73d2b4cd SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
36dffd8f | 13 | #include "skeleton.dtsi" |
e1641531 | 14 | #include "imx53-pinfunc.h" |
73d2b4cd SG |
15 | |
16 | / { | |
17 | aliases { | |
8f9ffecf RZ |
18 | serial0 = &uart1; |
19 | serial1 = &uart2; | |
20 | serial2 = &uart3; | |
21 | serial3 = &uart4; | |
22 | serial4 = &uart5; | |
5230f8fe SG |
23 | gpio0 = &gpio1; |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | gpio5 = &gpio6; | |
29 | gpio6 = &gpio7; | |
c60dc1d1 PZ |
30 | i2c0 = &i2c1; |
31 | i2c1 = &i2c2; | |
32 | i2c2 = &i2c3; | |
73d2b4cd SG |
33 | }; |
34 | ||
35 | tzic: tz-interrupt-controller@0fffc000 { | |
36 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
37 | interrupt-controller; | |
38 | #interrupt-cells = <1>; | |
39 | reg = <0x0fffc000 0x4000>; | |
40 | }; | |
41 | ||
42 | clocks { | |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | ckil { | |
47 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
48 | clock-frequency = <32768>; | |
49 | }; | |
50 | ||
51 | ckih1 { | |
52 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
53 | clock-frequency = <22579200>; | |
54 | }; | |
55 | ||
56 | ckih2 { | |
57 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
58 | clock-frequency = <0>; | |
59 | }; | |
60 | ||
61 | osc { | |
62 | compatible = "fsl,imx-osc", "fixed-clock"; | |
63 | clock-frequency = <24000000>; | |
64 | }; | |
65 | }; | |
66 | ||
67 | soc { | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | compatible = "simple-bus"; | |
71 | interrupt-parent = <&tzic>; | |
72 | ranges; | |
73 | ||
abed9a6b SH |
74 | ipu: ipu@18000000 { |
75 | #crtc-cells = <1>; | |
76 | compatible = "fsl,imx53-ipu"; | |
77 | reg = <0x18000000 0x080000000>; | |
78 | interrupts = <11 10>; | |
4438a6a1 PZ |
79 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; |
80 | clock-names = "bus", "di0", "di1"; | |
8d84c374 | 81 | resets = <&src 2>; |
abed9a6b SH |
82 | }; |
83 | ||
73d2b4cd SG |
84 | aips@50000000 { /* AIPS1 */ |
85 | compatible = "fsl,aips-bus", "simple-bus"; | |
86 | #address-cells = <1>; | |
87 | #size-cells = <1>; | |
88 | reg = <0x50000000 0x10000000>; | |
89 | ranges; | |
90 | ||
91 | spba@50000000 { | |
92 | compatible = "fsl,spba-bus", "simple-bus"; | |
93 | #address-cells = <1>; | |
94 | #size-cells = <1>; | |
95 | reg = <0x50000000 0x40000>; | |
96 | ranges; | |
97 | ||
7b7d6727 | 98 | esdhc1: esdhc@50004000 { |
73d2b4cd SG |
99 | compatible = "fsl,imx53-esdhc"; |
100 | reg = <0x50004000 0x4000>; | |
101 | interrupts = <1>; | |
f40f38d1 FE |
102 | clocks = <&clks 44>, <&clks 0>, <&clks 71>; |
103 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 104 | bus-width = <4>; |
73d2b4cd SG |
105 | status = "disabled"; |
106 | }; | |
107 | ||
7b7d6727 | 108 | esdhc2: esdhc@50008000 { |
73d2b4cd SG |
109 | compatible = "fsl,imx53-esdhc"; |
110 | reg = <0x50008000 0x4000>; | |
111 | interrupts = <2>; | |
f40f38d1 FE |
112 | clocks = <&clks 45>, <&clks 0>, <&clks 72>; |
113 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 114 | bus-width = <4>; |
73d2b4cd SG |
115 | status = "disabled"; |
116 | }; | |
117 | ||
0c456cfa | 118 | uart3: serial@5000c000 { |
73d2b4cd SG |
119 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
120 | reg = <0x5000c000 0x4000>; | |
121 | interrupts = <33>; | |
f40f38d1 FE |
122 | clocks = <&clks 32>, <&clks 33>; |
123 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
124 | status = "disabled"; |
125 | }; | |
126 | ||
7b7d6727 | 127 | ecspi1: ecspi@50010000 { |
73d2b4cd SG |
128 | #address-cells = <1>; |
129 | #size-cells = <0>; | |
130 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
131 | reg = <0x50010000 0x4000>; | |
132 | interrupts = <36>; | |
f40f38d1 FE |
133 | clocks = <&clks 51>, <&clks 52>; |
134 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
135 | status = "disabled"; |
136 | }; | |
137 | ||
ffc505c0 SG |
138 | ssi2: ssi@50014000 { |
139 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
140 | reg = <0x50014000 0x4000>; | |
141 | interrupts = <30>; | |
f40f38d1 | 142 | clocks = <&clks 49>; |
ffc505c0 SG |
143 | fsl,fifo-depth = <15>; |
144 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
145 | status = "disabled"; | |
146 | }; | |
147 | ||
7b7d6727 | 148 | esdhc3: esdhc@50020000 { |
73d2b4cd SG |
149 | compatible = "fsl,imx53-esdhc"; |
150 | reg = <0x50020000 0x4000>; | |
151 | interrupts = <3>; | |
f40f38d1 FE |
152 | clocks = <&clks 46>, <&clks 0>, <&clks 73>; |
153 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 154 | bus-width = <4>; |
73d2b4cd SG |
155 | status = "disabled"; |
156 | }; | |
157 | ||
7b7d6727 | 158 | esdhc4: esdhc@50024000 { |
73d2b4cd SG |
159 | compatible = "fsl,imx53-esdhc"; |
160 | reg = <0x50024000 0x4000>; | |
161 | interrupts = <4>; | |
f40f38d1 FE |
162 | clocks = <&clks 47>, <&clks 0>, <&clks 74>; |
163 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 164 | bus-width = <4>; |
73d2b4cd SG |
165 | status = "disabled"; |
166 | }; | |
167 | }; | |
168 | ||
a79025c4 MG |
169 | usbphy0: usbphy@0 { |
170 | compatible = "usb-nop-xceiv"; | |
171 | clocks = <&clks 124>; | |
172 | clock-names = "main_clk"; | |
173 | status = "okay"; | |
174 | }; | |
175 | ||
176 | usbphy1: usbphy@1 { | |
177 | compatible = "usb-nop-xceiv"; | |
178 | clocks = <&clks 125>; | |
179 | clock-names = "main_clk"; | |
180 | status = "okay"; | |
181 | }; | |
182 | ||
7b7d6727 | 183 | usbotg: usb@53f80000 { |
212d0b83 MG |
184 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
185 | reg = <0x53f80000 0x0200>; | |
186 | interrupts = <18>; | |
8e388908 | 187 | clocks = <&clks 108>; |
a5735021 | 188 | fsl,usbmisc = <&usbmisc 0>; |
a79025c4 | 189 | fsl,usbphy = <&usbphy0>; |
212d0b83 MG |
190 | status = "disabled"; |
191 | }; | |
192 | ||
7b7d6727 | 193 | usbh1: usb@53f80200 { |
212d0b83 MG |
194 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
195 | reg = <0x53f80200 0x0200>; | |
196 | interrupts = <14>; | |
8e388908 | 197 | clocks = <&clks 108>; |
a5735021 | 198 | fsl,usbmisc = <&usbmisc 1>; |
a79025c4 | 199 | fsl,usbphy = <&usbphy1>; |
212d0b83 MG |
200 | status = "disabled"; |
201 | }; | |
202 | ||
7b7d6727 | 203 | usbh2: usb@53f80400 { |
212d0b83 MG |
204 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
205 | reg = <0x53f80400 0x0200>; | |
206 | interrupts = <16>; | |
8e388908 | 207 | clocks = <&clks 108>; |
a5735021 | 208 | fsl,usbmisc = <&usbmisc 2>; |
212d0b83 MG |
209 | status = "disabled"; |
210 | }; | |
211 | ||
7b7d6727 | 212 | usbh3: usb@53f80600 { |
212d0b83 MG |
213 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
214 | reg = <0x53f80600 0x0200>; | |
215 | interrupts = <17>; | |
8e388908 | 216 | clocks = <&clks 108>; |
a5735021 | 217 | fsl,usbmisc = <&usbmisc 3>; |
212d0b83 MG |
218 | status = "disabled"; |
219 | }; | |
220 | ||
a5735021 MG |
221 | usbmisc: usbmisc@53f80800 { |
222 | #index-cells = <1>; | |
223 | compatible = "fsl,imx53-usbmisc"; | |
224 | reg = <0x53f80800 0x200>; | |
8e388908 | 225 | clocks = <&clks 108>; |
a5735021 MG |
226 | }; |
227 | ||
4d191868 | 228 | gpio1: gpio@53f84000 { |
aeb27748 | 229 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
230 | reg = <0x53f84000 0x4000>; |
231 | interrupts = <50 51>; | |
232 | gpio-controller; | |
233 | #gpio-cells = <2>; | |
234 | interrupt-controller; | |
88cde8b7 | 235 | #interrupt-cells = <2>; |
73d2b4cd SG |
236 | }; |
237 | ||
4d191868 | 238 | gpio2: gpio@53f88000 { |
aeb27748 | 239 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
240 | reg = <0x53f88000 0x4000>; |
241 | interrupts = <52 53>; | |
242 | gpio-controller; | |
243 | #gpio-cells = <2>; | |
244 | interrupt-controller; | |
88cde8b7 | 245 | #interrupt-cells = <2>; |
73d2b4cd SG |
246 | }; |
247 | ||
4d191868 | 248 | gpio3: gpio@53f8c000 { |
aeb27748 | 249 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
250 | reg = <0x53f8c000 0x4000>; |
251 | interrupts = <54 55>; | |
252 | gpio-controller; | |
253 | #gpio-cells = <2>; | |
254 | interrupt-controller; | |
88cde8b7 | 255 | #interrupt-cells = <2>; |
73d2b4cd SG |
256 | }; |
257 | ||
4d191868 | 258 | gpio4: gpio@53f90000 { |
aeb27748 | 259 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
260 | reg = <0x53f90000 0x4000>; |
261 | interrupts = <56 57>; | |
262 | gpio-controller; | |
263 | #gpio-cells = <2>; | |
264 | interrupt-controller; | |
88cde8b7 | 265 | #interrupt-cells = <2>; |
73d2b4cd SG |
266 | }; |
267 | ||
7b7d6727 | 268 | wdog1: wdog@53f98000 { |
73d2b4cd SG |
269 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
270 | reg = <0x53f98000 0x4000>; | |
271 | interrupts = <58>; | |
f40f38d1 | 272 | clocks = <&clks 0>; |
73d2b4cd SG |
273 | }; |
274 | ||
7b7d6727 | 275 | wdog2: wdog@53f9c000 { |
73d2b4cd SG |
276 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
277 | reg = <0x53f9c000 0x4000>; | |
278 | interrupts = <59>; | |
f40f38d1 | 279 | clocks = <&clks 0>; |
73d2b4cd SG |
280 | status = "disabled"; |
281 | }; | |
282 | ||
cc8aae9b SH |
283 | gpt: timer@53fa0000 { |
284 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
285 | reg = <0x53fa0000 0x4000>; | |
286 | interrupts = <39>; | |
287 | clocks = <&clks 36>, <&clks 41>; | |
288 | clock-names = "ipg", "per"; | |
289 | }; | |
290 | ||
7b7d6727 | 291 | iomuxc: iomuxc@53fa8000 { |
5be03a7b SG |
292 | compatible = "fsl,imx53-iomuxc"; |
293 | reg = <0x53fa8000 0x4000>; | |
294 | ||
295 | audmux { | |
296 | pinctrl_audmux_1: audmuxgrp-1 { | |
297 | fsl,pins = < | |
e1641531 SG |
298 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 |
299 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | |
300 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | |
301 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | |
5be03a7b SG |
302 | >; |
303 | }; | |
dd04c17b MV |
304 | |
305 | pinctrl_audmux_2: audmuxgrp-2 { | |
306 | fsl,pins = < | |
307 | MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 | |
308 | MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 | |
309 | MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 | |
310 | MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 | |
311 | >; | |
312 | }; | |
bb6e2fa3 ST |
313 | |
314 | pinctrl_audmux_3: audmuxgrp-3 { | |
315 | fsl,pins = < | |
316 | MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 | |
317 | MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 | |
318 | MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 | |
319 | MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 | |
320 | >; | |
321 | }; | |
5be03a7b SG |
322 | }; |
323 | ||
324 | fec { | |
325 | pinctrl_fec_1: fecgrp-1 { | |
326 | fsl,pins = < | |
e1641531 SG |
327 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 |
328 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | |
329 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | |
330 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | |
331 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | |
332 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | |
333 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | |
334 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | |
335 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | |
336 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | |
5be03a7b SG |
337 | >; |
338 | }; | |
fad1ea00 JA |
339 | |
340 | pinctrl_fec_2: fecgrp-2 { | |
341 | fsl,pins = < | |
342 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | |
343 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | |
344 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | |
345 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | |
346 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | |
347 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | |
348 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | |
349 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | |
350 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | |
351 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | |
352 | MX53_PAD_KEY_ROW1__FEC_COL 0x80000000 | |
353 | MX53_PAD_KEY_COL3__FEC_CRS 0x80000000 | |
354 | MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000 | |
355 | MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000 | |
356 | MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000 | |
357 | MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000 | |
358 | MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000 | |
359 | MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000 | |
360 | >; | |
361 | }; | |
5be03a7b SG |
362 | }; |
363 | ||
11ab21e9 ST |
364 | csi { |
365 | pinctrl_csi_1: csigrp-1 { | |
366 | fsl,pins = < | |
e1641531 SG |
367 | MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 |
368 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 | |
369 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 | |
370 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | |
371 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 | |
372 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 | |
373 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 | |
374 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 | |
375 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 | |
376 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 | |
377 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 | |
378 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 | |
379 | MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 | |
380 | MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 | |
381 | MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 | |
382 | MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 | |
383 | MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 | |
384 | MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 | |
385 | MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 | |
386 | MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 | |
387 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | |
11ab21e9 ST |
388 | >; |
389 | }; | |
d0cae684 ST |
390 | |
391 | pinctrl_csi_2: csigrp-2 { | |
392 | fsl,pins = < | |
393 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 | |
394 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 | |
395 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | |
396 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 | |
397 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 | |
398 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 | |
399 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 | |
400 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 | |
401 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 | |
402 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 | |
403 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 | |
404 | >; | |
405 | }; | |
11ab21e9 ST |
406 | }; |
407 | ||
408 | cspi { | |
409 | pinctrl_cspi_1: cspigrp-1 { | |
410 | fsl,pins = < | |
e1641531 SG |
411 | MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 |
412 | MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 | |
413 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 | |
11ab21e9 ST |
414 | >; |
415 | }; | |
4017f791 JA |
416 | |
417 | pinctrl_cspi_2: cspigrp-2 { | |
418 | fsl,pins = < | |
419 | MX53_PAD_EIM_D22__CSPI_MISO 0x1d5 | |
420 | MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5 | |
421 | MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5 | |
422 | >; | |
423 | }; | |
11ab21e9 ST |
424 | }; |
425 | ||
327a79c0 SG |
426 | ecspi1 { |
427 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
428 | fsl,pins = < | |
e1641531 SG |
429 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 |
430 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | |
431 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | |
327a79c0 SG |
432 | >; |
433 | }; | |
6a079e68 ST |
434 | |
435 | pinctrl_ecspi1_2: ecspi1grp-2 { | |
436 | fsl,pins = < | |
437 | MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 | |
438 | MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 | |
439 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | |
440 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | |
441 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | |
442 | MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 | |
443 | >; | |
444 | }; | |
327a79c0 SG |
445 | }; |
446 | ||
1a6c5600 JA |
447 | ecspi2 { |
448 | pinctrl_ecspi2_1: ecspi2grp-1 { | |
449 | fsl,pins = < | |
450 | MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000 | |
451 | MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000 | |
452 | MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000 | |
453 | >; | |
454 | }; | |
455 | }; | |
456 | ||
5be03a7b SG |
457 | esdhc1 { |
458 | pinctrl_esdhc1_1: esdhc1grp-1 { | |
459 | fsl,pins = < | |
e1641531 SG |
460 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
461 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | |
462 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | |
463 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | |
464 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | |
465 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | |
5be03a7b SG |
466 | >; |
467 | }; | |
4bb6143c SG |
468 | |
469 | pinctrl_esdhc1_2: esdhc1grp-2 { | |
470 | fsl,pins = < | |
e1641531 SG |
471 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
472 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | |
473 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | |
474 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | |
475 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 | |
476 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 | |
477 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 | |
478 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 | |
479 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | |
480 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | |
4bb6143c SG |
481 | >; |
482 | }; | |
5be03a7b SG |
483 | }; |
484 | ||
07248042 SG |
485 | esdhc2 { |
486 | pinctrl_esdhc2_1: esdhc2grp-1 { | |
487 | fsl,pins = < | |
e1641531 SG |
488 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 |
489 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | |
490 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | |
491 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | |
492 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | |
493 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | |
07248042 SG |
494 | >; |
495 | }; | |
496 | }; | |
497 | ||
5be03a7b SG |
498 | esdhc3 { |
499 | pinctrl_esdhc3_1: esdhc3grp-1 { | |
500 | fsl,pins = < | |
e1641531 SG |
501 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 |
502 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 | |
503 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 | |
504 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 | |
505 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 | |
506 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 | |
507 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 | |
508 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 | |
509 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 | |
510 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 | |
5be03a7b SG |
511 | >; |
512 | }; | |
513 | }; | |
514 | ||
a1fff236 RS |
515 | can1 { |
516 | pinctrl_can1_1: can1grp-1 { | |
517 | fsl,pins = < | |
e1641531 SG |
518 | MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 |
519 | MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000 | |
a1fff236 RS |
520 | >; |
521 | }; | |
11ab21e9 ST |
522 | |
523 | pinctrl_can1_2: can1grp-2 { | |
524 | fsl,pins = < | |
e1641531 SG |
525 | MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 |
526 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 | |
11ab21e9 ST |
527 | >; |
528 | }; | |
0f14ac4e MV |
529 | |
530 | pinctrl_can1_3: can1grp-3 { | |
531 | fsl,pins = < | |
532 | MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 | |
533 | MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 | |
534 | >; | |
535 | }; | |
a1fff236 RS |
536 | }; |
537 | ||
538 | can2 { | |
539 | pinctrl_can2_1: can2grp-1 { | |
540 | fsl,pins = < | |
e1641531 SG |
541 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 |
542 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 | |
a1fff236 RS |
543 | >; |
544 | }; | |
545 | }; | |
546 | ||
5be03a7b SG |
547 | i2c1 { |
548 | pinctrl_i2c1_1: i2c1grp-1 { | |
549 | fsl,pins = < | |
e1641531 SG |
550 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 |
551 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 | |
5be03a7b SG |
552 | >; |
553 | }; | |
d7974714 MV |
554 | |
555 | pinctrl_i2c1_2: i2c1grp-2 { | |
556 | fsl,pins = < | |
557 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | |
558 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | |
559 | >; | |
560 | }; | |
5be03a7b SG |
561 | }; |
562 | ||
563 | i2c2 { | |
564 | pinctrl_i2c2_1: i2c2grp-1 { | |
565 | fsl,pins = < | |
e1641531 SG |
566 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 |
567 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | |
5be03a7b SG |
568 | >; |
569 | }; | |
ed5be465 MV |
570 | |
571 | pinctrl_i2c2_2: i2c2grp-2 { | |
572 | fsl,pins = < | |
573 | MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 | |
574 | MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 | |
575 | >; | |
576 | }; | |
5be03a7b SG |
577 | }; |
578 | ||
a1fff236 RS |
579 | i2c3 { |
580 | pinctrl_i2c3_1: i2c3grp-1 { | |
581 | fsl,pins = < | |
e1641531 SG |
582 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 |
583 | MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 | |
a1fff236 RS |
584 | >; |
585 | }; | |
586 | }; | |
587 | ||
c268947a RP |
588 | ipu_disp0 { |
589 | pinctrl_ipu_disp0_1: ipudisp0grp-1 { | |
590 | fsl,pins = < | |
591 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 | |
592 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 | |
593 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 | |
594 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 | |
595 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 | |
596 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 | |
597 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 | |
598 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 | |
599 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 | |
600 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 | |
601 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 | |
602 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 | |
603 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 | |
604 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 | |
605 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 | |
606 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 | |
607 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 | |
608 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 | |
609 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 | |
610 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 | |
611 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 | |
612 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 | |
613 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 | |
614 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 | |
615 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 | |
616 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 | |
617 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 | |
618 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 | |
619 | >; | |
620 | }; | |
621 | }; | |
622 | ||
9f7fbb15 MV |
623 | ipu_disp1 { |
624 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | |
625 | fsl,pins = < | |
626 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 | |
627 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 | |
628 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 | |
629 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 | |
630 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 | |
631 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 | |
632 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 | |
633 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 | |
634 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 | |
635 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 | |
636 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | |
637 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | |
638 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | |
639 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | |
640 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | |
641 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | |
642 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | |
643 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | |
644 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | |
645 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | |
646 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | |
647 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | |
648 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | |
649 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | |
650 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | |
651 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | |
652 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | |
653 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | |
654 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | |
655 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | |
656 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | |
657 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | |
658 | >; | |
659 | }; | |
660 | }; | |
661 | ||
662 | ipu_disp2 { | |
663 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | |
664 | fsl,pins = < | |
665 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | |
666 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | |
667 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | |
668 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | |
669 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | |
670 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | |
671 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | |
672 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | |
673 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | |
674 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | |
675 | >; | |
676 | }; | |
677 | }; | |
678 | ||
efee5e14 MV |
679 | nand { |
680 | pinctrl_nand_1: nandgrp-1 { | |
681 | fsl,pins = < | |
682 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | |
683 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | |
684 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | |
685 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | |
686 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | |
687 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | |
688 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | |
689 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 | |
690 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 | |
691 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 | |
692 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 | |
693 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 | |
694 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 | |
695 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 | |
696 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 | |
697 | >; | |
698 | }; | |
699 | }; | |
700 | ||
a82b7b9c MF |
701 | owire { |
702 | pinctrl_owire_1: owiregrp-1 { | |
703 | fsl,pins = < | |
e1641531 | 704 | MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000 |
a82b7b9c MF |
705 | >; |
706 | }; | |
707 | }; | |
708 | ||
95050497 MV |
709 | pwm1 { |
710 | pinctrl_pwm1_1: pwm1grp-1 { | |
711 | fsl,pins = < | |
712 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | |
713 | >; | |
714 | }; | |
715 | }; | |
716 | ||
20e081cf ST |
717 | pwm2 { |
718 | pinctrl_pwm2_1: pwm2grp-1 { | |
719 | fsl,pins = < | |
720 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 | |
721 | >; | |
722 | }; | |
723 | }; | |
724 | ||
5be03a7b SG |
725 | uart1 { |
726 | pinctrl_uart1_1: uart1grp-1 { | |
727 | fsl,pins = < | |
f5786b8e PZ |
728 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 |
729 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 | |
5be03a7b SG |
730 | >; |
731 | }; | |
4bb6143c SG |
732 | |
733 | pinctrl_uart1_2: uart1grp-2 { | |
734 | fsl,pins = < | |
f5786b8e PZ |
735 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 |
736 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | |
4bb6143c SG |
737 | >; |
738 | }; | |
47d63397 ST |
739 | |
740 | pinctrl_uart1_3: uart1grp-3 { | |
741 | fsl,pins = < | |
742 | MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 | |
743 | MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 | |
744 | >; | |
745 | }; | |
5be03a7b | 746 | }; |
07248042 SG |
747 | |
748 | uart2 { | |
749 | pinctrl_uart2_1: uart2grp-1 { | |
750 | fsl,pins = < | |
f5786b8e PZ |
751 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 |
752 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 | |
07248042 SG |
753 | >; |
754 | }; | |
c3fcca2a ST |
755 | |
756 | pinctrl_uart2_2: uart2grp-2 { | |
757 | fsl,pins = < | |
758 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 | |
759 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | |
760 | MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 | |
761 | MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 | |
762 | >; | |
763 | }; | |
07248042 SG |
764 | }; |
765 | ||
766 | uart3 { | |
767 | pinctrl_uart3_1: uart3grp-1 { | |
768 | fsl,pins = < | |
f5786b8e PZ |
769 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 |
770 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | |
771 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 | |
772 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 | |
07248042 SG |
773 | >; |
774 | }; | |
11ab21e9 ST |
775 | |
776 | pinctrl_uart3_2: uart3grp-2 { | |
777 | fsl,pins = < | |
f5786b8e PZ |
778 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 |
779 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | |
11ab21e9 ST |
780 | >; |
781 | }; | |
782 | ||
07248042 | 783 | }; |
a1fff236 RS |
784 | |
785 | uart4 { | |
786 | pinctrl_uart4_1: uart4grp-1 { | |
787 | fsl,pins = < | |
f5786b8e PZ |
788 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 |
789 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 | |
a1fff236 RS |
790 | >; |
791 | }; | |
792 | }; | |
793 | ||
794 | uart5 { | |
795 | pinctrl_uart5_1: uart5grp-1 { | |
796 | fsl,pins = < | |
f5786b8e PZ |
797 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 |
798 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 | |
a1fff236 RS |
799 | >; |
800 | }; | |
801 | }; | |
5be03a7b SG |
802 | }; |
803 | ||
5af9f143 PZ |
804 | gpr: iomuxc-gpr@53fa8000 { |
805 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
806 | reg = <0x53fa8000 0xc>; | |
807 | }; | |
808 | ||
420714aa PZ |
809 | ldb: ldb@53fa8008 { |
810 | #address-cells = <1>; | |
811 | #size-cells = <0>; | |
812 | compatible = "fsl,imx53-ldb"; | |
813 | reg = <0x53fa8008 0x4>; | |
814 | gpr = <&gpr>; | |
815 | clocks = <&clks 122>, <&clks 120>, | |
816 | <&clks 115>, <&clks 116>, | |
817 | <&clks 123>, <&clks 85>; | |
818 | clock-names = "di0_pll", "di1_pll", | |
819 | "di0_sel", "di1_sel", | |
820 | "di0", "di1"; | |
821 | status = "disabled"; | |
822 | ||
823 | lvds-channel@0 { | |
824 | reg = <0>; | |
825 | crtcs = <&ipu 0>; | |
826 | status = "disabled"; | |
827 | }; | |
828 | ||
829 | lvds-channel@1 { | |
830 | reg = <1>; | |
831 | crtcs = <&ipu 1>; | |
832 | status = "disabled"; | |
833 | }; | |
834 | }; | |
835 | ||
9ae90afa SH |
836 | pwm1: pwm@53fb4000 { |
837 | #pwm-cells = <2>; | |
838 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
839 | reg = <0x53fb4000 0x4000>; | |
840 | clocks = <&clks 37>, <&clks 38>; | |
841 | clock-names = "ipg", "per"; | |
842 | interrupts = <61>; | |
843 | }; | |
844 | ||
845 | pwm2: pwm@53fb8000 { | |
846 | #pwm-cells = <2>; | |
847 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
848 | reg = <0x53fb8000 0x4000>; | |
849 | clocks = <&clks 39>, <&clks 40>; | |
850 | clock-names = "ipg", "per"; | |
851 | interrupts = <94>; | |
852 | }; | |
853 | ||
0c456cfa | 854 | uart1: serial@53fbc000 { |
73d2b4cd SG |
855 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
856 | reg = <0x53fbc000 0x4000>; | |
857 | interrupts = <31>; | |
f40f38d1 FE |
858 | clocks = <&clks 28>, <&clks 29>; |
859 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
860 | status = "disabled"; |
861 | }; | |
862 | ||
0c456cfa | 863 | uart2: serial@53fc0000 { |
73d2b4cd SG |
864 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
865 | reg = <0x53fc0000 0x4000>; | |
866 | interrupts = <32>; | |
f40f38d1 FE |
867 | clocks = <&clks 30>, <&clks 31>; |
868 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
869 | status = "disabled"; |
870 | }; | |
871 | ||
a9d1f924 ST |
872 | can1: can@53fc8000 { |
873 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
874 | reg = <0x53fc8000 0x4000>; | |
875 | interrupts = <82>; | |
f40f38d1 FE |
876 | clocks = <&clks 158>, <&clks 157>; |
877 | clock-names = "ipg", "per"; | |
a9d1f924 ST |
878 | status = "disabled"; |
879 | }; | |
880 | ||
881 | can2: can@53fcc000 { | |
882 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
883 | reg = <0x53fcc000 0x4000>; | |
884 | interrupts = <83>; | |
e37f0d5b | 885 | clocks = <&clks 87>, <&clks 86>; |
f40f38d1 | 886 | clock-names = "ipg", "per"; |
a9d1f924 ST |
887 | status = "disabled"; |
888 | }; | |
889 | ||
8d84c374 PZ |
890 | src: src@53fd0000 { |
891 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
892 | reg = <0x53fd0000 0x4000>; | |
893 | #reset-cells = <1>; | |
894 | }; | |
895 | ||
f40f38d1 FE |
896 | clks: ccm@53fd4000{ |
897 | compatible = "fsl,imx53-ccm"; | |
898 | reg = <0x53fd4000 0x4000>; | |
899 | interrupts = <0 71 0x04 0 72 0x04>; | |
900 | #clock-cells = <1>; | |
901 | }; | |
902 | ||
4d191868 | 903 | gpio5: gpio@53fdc000 { |
aeb27748 | 904 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
905 | reg = <0x53fdc000 0x4000>; |
906 | interrupts = <103 104>; | |
907 | gpio-controller; | |
908 | #gpio-cells = <2>; | |
909 | interrupt-controller; | |
88cde8b7 | 910 | #interrupt-cells = <2>; |
73d2b4cd SG |
911 | }; |
912 | ||
4d191868 | 913 | gpio6: gpio@53fe0000 { |
aeb27748 | 914 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
915 | reg = <0x53fe0000 0x4000>; |
916 | interrupts = <105 106>; | |
917 | gpio-controller; | |
918 | #gpio-cells = <2>; | |
919 | interrupt-controller; | |
88cde8b7 | 920 | #interrupt-cells = <2>; |
73d2b4cd SG |
921 | }; |
922 | ||
4d191868 | 923 | gpio7: gpio@53fe4000 { |
aeb27748 | 924 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
925 | reg = <0x53fe4000 0x4000>; |
926 | interrupts = <107 108>; | |
927 | gpio-controller; | |
928 | #gpio-cells = <2>; | |
929 | interrupt-controller; | |
88cde8b7 | 930 | #interrupt-cells = <2>; |
73d2b4cd SG |
931 | }; |
932 | ||
7b7d6727 | 933 | i2c3: i2c@53fec000 { |
73d2b4cd SG |
934 | #address-cells = <1>; |
935 | #size-cells = <0>; | |
5bdfba29 | 936 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
937 | reg = <0x53fec000 0x4000>; |
938 | interrupts = <64>; | |
f40f38d1 | 939 | clocks = <&clks 88>; |
73d2b4cd SG |
940 | status = "disabled"; |
941 | }; | |
942 | ||
0c456cfa | 943 | uart4: serial@53ff0000 { |
73d2b4cd SG |
944 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
945 | reg = <0x53ff0000 0x4000>; | |
946 | interrupts = <13>; | |
f40f38d1 FE |
947 | clocks = <&clks 65>, <&clks 66>; |
948 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
949 | status = "disabled"; |
950 | }; | |
951 | }; | |
952 | ||
953 | aips@60000000 { /* AIPS2 */ | |
954 | compatible = "fsl,aips-bus", "simple-bus"; | |
955 | #address-cells = <1>; | |
956 | #size-cells = <1>; | |
957 | reg = <0x60000000 0x10000000>; | |
958 | ranges; | |
959 | ||
0c456cfa | 960 | uart5: serial@63f90000 { |
73d2b4cd SG |
961 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
962 | reg = <0x63f90000 0x4000>; | |
963 | interrupts = <86>; | |
f40f38d1 FE |
964 | clocks = <&clks 67>, <&clks 68>; |
965 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
966 | status = "disabled"; |
967 | }; | |
968 | ||
a82b7b9c MF |
969 | owire: owire@63fa4000 { |
970 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
971 | reg = <0x63fa4000 0x4000>; | |
972 | clocks = <&clks 159>; | |
973 | status = "disabled"; | |
974 | }; | |
975 | ||
7b7d6727 | 976 | ecspi2: ecspi@63fac000 { |
73d2b4cd SG |
977 | #address-cells = <1>; |
978 | #size-cells = <0>; | |
979 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
980 | reg = <0x63fac000 0x4000>; | |
981 | interrupts = <37>; | |
f40f38d1 FE |
982 | clocks = <&clks 53>, <&clks 54>; |
983 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
984 | status = "disabled"; |
985 | }; | |
986 | ||
7b7d6727 | 987 | sdma: sdma@63fb0000 { |
73d2b4cd SG |
988 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
989 | reg = <0x63fb0000 0x4000>; | |
990 | interrupts = <6>; | |
f40f38d1 FE |
991 | clocks = <&clks 56>, <&clks 56>; |
992 | clock-names = "ipg", "ahb"; | |
7e4f0365 | 993 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
73d2b4cd SG |
994 | }; |
995 | ||
7b7d6727 | 996 | cspi: cspi@63fc0000 { |
73d2b4cd SG |
997 | #address-cells = <1>; |
998 | #size-cells = <0>; | |
999 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
1000 | reg = <0x63fc0000 0x4000>; | |
1001 | interrupts = <38>; | |
37523dc5 | 1002 | clocks = <&clks 55>, <&clks 55>; |
f40f38d1 | 1003 | clock-names = "ipg", "per"; |
73d2b4cd SG |
1004 | status = "disabled"; |
1005 | }; | |
1006 | ||
7b7d6727 | 1007 | i2c2: i2c@63fc4000 { |
73d2b4cd SG |
1008 | #address-cells = <1>; |
1009 | #size-cells = <0>; | |
5bdfba29 | 1010 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
1011 | reg = <0x63fc4000 0x4000>; |
1012 | interrupts = <63>; | |
f40f38d1 | 1013 | clocks = <&clks 35>; |
73d2b4cd SG |
1014 | status = "disabled"; |
1015 | }; | |
1016 | ||
7b7d6727 | 1017 | i2c1: i2c@63fc8000 { |
73d2b4cd SG |
1018 | #address-cells = <1>; |
1019 | #size-cells = <0>; | |
5bdfba29 | 1020 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
1021 | reg = <0x63fc8000 0x4000>; |
1022 | interrupts = <62>; | |
f40f38d1 | 1023 | clocks = <&clks 34>; |
73d2b4cd SG |
1024 | status = "disabled"; |
1025 | }; | |
1026 | ||
ffc505c0 SG |
1027 | ssi1: ssi@63fcc000 { |
1028 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
1029 | reg = <0x63fcc000 0x4000>; | |
1030 | interrupts = <29>; | |
f40f38d1 | 1031 | clocks = <&clks 48>; |
ffc505c0 SG |
1032 | fsl,fifo-depth = <15>; |
1033 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
1034 | status = "disabled"; | |
1035 | }; | |
1036 | ||
7b7d6727 | 1037 | audmux: audmux@63fd0000 { |
ffc505c0 SG |
1038 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
1039 | reg = <0x63fd0000 0x4000>; | |
1040 | status = "disabled"; | |
1041 | }; | |
1042 | ||
7b7d6727 | 1043 | nfc: nand@63fdb000 { |
75453a08 SH |
1044 | compatible = "fsl,imx53-nand"; |
1045 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
1046 | interrupts = <8>; | |
f40f38d1 | 1047 | clocks = <&clks 60>; |
75453a08 SH |
1048 | status = "disabled"; |
1049 | }; | |
1050 | ||
ffc505c0 SG |
1051 | ssi3: ssi@63fe8000 { |
1052 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
1053 | reg = <0x63fe8000 0x4000>; | |
1054 | interrupts = <96>; | |
f40f38d1 | 1055 | clocks = <&clks 50>; |
ffc505c0 SG |
1056 | fsl,fifo-depth = <15>; |
1057 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ | |
1058 | status = "disabled"; | |
1059 | }; | |
1060 | ||
7b7d6727 | 1061 | fec: ethernet@63fec000 { |
73d2b4cd SG |
1062 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
1063 | reg = <0x63fec000 0x4000>; | |
1064 | interrupts = <87>; | |
f40f38d1 FE |
1065 | clocks = <&clks 42>, <&clks 42>, <&clks 42>; |
1066 | clock-names = "ipg", "ahb", "ptp"; | |
73d2b4cd SG |
1067 | status = "disabled"; |
1068 | }; | |
19194c2b PZ |
1069 | |
1070 | tve: tve@63ff0000 { | |
1071 | compatible = "fsl,imx53-tve"; | |
1072 | reg = <0x63ff0000 0x1000>; | |
1073 | interrupts = <92>; | |
1074 | clocks = <&clks 69>, <&clks 116>; | |
1075 | clock-names = "tve", "di_sel"; | |
1076 | crtcs = <&ipu 1>; | |
1077 | status = "disabled"; | |
1078 | }; | |
73d2b4cd SG |
1079 | }; |
1080 | }; | |
1081 | }; |