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ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
CommitLineData
73d2b4cd
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
e1641531 14#include "imx53-pinfunc.h"
564695dd 15#include <dt-bindings/clock/imx5-clock.h>
4e05a7af
DC		 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
73d2b4cd
SG		 18
19/ {
20 aliases {
22970070 21 ethernet0 = &fec;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
c60dc1d1
PZ		 29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
c63d06de
SH		 32 mmc0 = &esdhc1;
33 mmc1 = &esdhc2;
34 mmc2 = &esdhc3;
35 mmc3 = &esdhc4;
cf4e577e
SH		 36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 spi0 = &ecspi1;
42 spi1 = &ecspi2;
43 spi2 = &cspi;
73d2b4cd
SG		 44 };
45
070bd7e4
FE		 46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a8";
52 reg = <0x0>;
53 };
54 };
55
e05c8c9a
PZ		 56 display-subsystem {
57 compatible = "fsl,imx-display-subsystem";
58 ports = <&ipu_di0>, <&ipu_di1>;
59 };
60
73d2b4cd
SG		 61 tzic: tz-interrupt-controller@0fffc000 {
62 compatible = "fsl,imx53-tzic", "fsl,tzic";
63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x0fffc000 0x4000>;
66 };
67
68 clocks {
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 ckil {
73 compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043 74 #clock-cells = <0>;
73d2b4cd
SG		 75 clock-frequency = <32768>;
76 };
77
78 ckih1 {
79 compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043 80 #clock-cells = <0>;
73d2b4cd
SG		 81 clock-frequency = <22579200>;
82 };
83
84 ckih2 {
85 compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043 86 #clock-cells = <0>;
73d2b4cd
SG		 87 clock-frequency = <0>;
88 };
89
90 osc {
91 compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043 92 #clock-cells = <0>;
73d2b4cd
SG		 93 clock-frequency = <24000000>;
94 };
95 };
96
97 soc {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>;
102 ranges;
103
7affee43
MV		 104 sata: sata@10000000 {
105 compatible = "fsl,imx53-ahci";
106 reg = <0x10000000 0x1000>;
107 interrupts = <28>;
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
02578153 111 clock-names = "sata", "sata_ref", "ahb";
7affee43
MV		 112 status = "disabled";
113 };
114
abed9a6b 115 ipu: ipu@18000000 {
e05c8c9a
PZ		 116 #address-cells = <1>;
117 #size-cells = <0>;
abed9a6b 118 compatible = "fsl,imx53-ipu";
6d66da89 119 reg = <0x18000000 0x08000000>;
abed9a6b 120 interrupts = <11 10>;
564695dd
LS		 121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
4438a6a1 124 clock-names = "bus", "di0", "di1";
8d84c374 125 resets = <&src 2>;
e05c8c9a
PZ		 126
127 ipu_di0: port@2 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <2>;
131
132 ipu_di0_disp0: endpoint@0 {
133 reg = <0>;
134 };
135
136 ipu_di0_lvds0: endpoint@1 {
137 reg = <1>;
138 remote-endpoint = <&lvds0_in>;
139 };
140 };
141
142 ipu_di1: port@3 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <3>;
146
147 ipu_di1_disp1: endpoint@0 {
148 reg = <0>;
149 };
150
151 ipu_di1_lvds1: endpoint@1 {
152 reg = <1>;
153 remote-endpoint = <&lvds1_in>;
154 };
155
156 ipu_di1_tve: endpoint@2 {
157 reg = <2>;
158 remote-endpoint = <&tve_in>;
159 };
160 };
abed9a6b
SH		 161 };
162
73d2b4cd
SG		 163 aips@50000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 reg = <0x50000000 0x10000000>;
168 ranges;
169
170 spba@50000000 {
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x50000000 0x40000>;
175 ranges;
176
7b7d6727 177 esdhc1: esdhc@50004000 {
73d2b4cd
SG		 178 compatible = "fsl,imx53-esdhc";
179 reg = <0x50004000 0x4000>;
180 interrupts = <1>;
564695dd
LS		 181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
f40f38d1 184 clock-names = "ipg", "ahb", "per";
c104b6a2 185 bus-width = <4>;
73d2b4cd
SG		 186 status = "disabled";
187 };
188
7b7d6727 189 esdhc2: esdhc@50008000 {
73d2b4cd
SG		 190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50008000 0x4000>;
192 interrupts = <2>;
564695dd
LS		 193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
f40f38d1 196 clock-names = "ipg", "ahb", "per";
c104b6a2 197 bus-width = <4>;
73d2b4cd
SG		 198 status = "disabled";
199 };
200
0c456cfa 201 uart3: serial@5000c000 {
73d2b4cd
SG		 202 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
203 reg = <0x5000c000 0x4000>;
204 interrupts = <33>;
564695dd
LS		 205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
f40f38d1 207 clock-names = "ipg", "per";
73d2b4cd
SG		 208 status = "disabled";
209 };
210
7b7d6727 211 ecspi1: ecspi@50010000 {
73d2b4cd
SG		 212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
215 reg = <0x50010000 0x4000>;
216 interrupts = <36>;
564695dd
LS		 217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
f40f38d1 219 clock-names = "ipg", "per";
73d2b4cd
SG		 220 status = "disabled";
221 };
222
ffc505c0 223 ssi2: ssi@50014000 {
6ff7f51e 224 #sound-dai-cells = <0>;
28f93d0b
MP		 225 compatible = "fsl,imx53-ssi",
226 "fsl,imx51-ssi",
227 "fsl,imx21-ssi";
ffc505c0
SG		 228 reg = <0x50014000 0x4000>;
229 interrupts = <30>;
564695dd 230 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
5da826ab
SG		 231 dmas = <&sdma 24 1 0>,
232 <&sdma 25 1 0>;
233 dma-names = "rx", "tx";
ffc505c0 234 fsl,fifo-depth = <15>;
ffc505c0
SG		 235 status = "disabled";
236 };
237
7b7d6727 238 esdhc3: esdhc@50020000 {
73d2b4cd
SG		 239 compatible = "fsl,imx53-esdhc";
240 reg = <0x50020000 0x4000>;
241 interrupts = <3>;
564695dd
LS		 242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
f40f38d1 245 clock-names = "ipg", "ahb", "per";
c104b6a2 246 bus-width = <4>;
73d2b4cd
SG		 247 status = "disabled";
248 };
249
7b7d6727 250 esdhc4: esdhc@50024000 {
73d2b4cd
SG		 251 compatible = "fsl,imx53-esdhc";
252 reg = <0x50024000 0x4000>;
253 interrupts = <4>;
564695dd
LS		 254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
f40f38d1 257 clock-names = "ipg", "ahb", "per";
c104b6a2 258 bus-width = <4>;
73d2b4cd
SG		 259 status = "disabled";
260 };
261 };
262
ac08281e
ST		 263 aipstz1: bridge@53f00000 {
264 compatible = "fsl,imx53-aipstz";
265 reg = <0x53f00000 0x60>;
266 };
267
a79025c4
MG		 268 usbphy0: usbphy@0 {
269 compatible = "usb-nop-xceiv";
564695dd 270 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
a79025c4
MG		 271 clock-names = "main_clk";
272 status = "okay";
273 };
274
275 usbphy1: usbphy@1 {
276 compatible = "usb-nop-xceiv";
564695dd 277 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
a79025c4
MG		 278 clock-names = "main_clk";
279 status = "okay";
280 };
281
7b7d6727 282 usbotg: usb@53f80000 {
212d0b83
MG		 283 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
284 reg = <0x53f80000 0x0200>;
285 interrupts = <18>;
564695dd 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 287 fsl,usbmisc = <&usbmisc 0>;
a79025c4 288 fsl,usbphy = <&usbphy0>;
212d0b83
MG		 289 status = "disabled";
290 };
291
7b7d6727 292 usbh1: usb@53f80200 {
212d0b83
MG		 293 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
294 reg = <0x53f80200 0x0200>;
295 interrupts = <14>;
564695dd 296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 297 fsl,usbmisc = <&usbmisc 1>;
a79025c4 298 fsl,usbphy = <&usbphy1>;
212d0b83
MG		 299 status = "disabled";
300 };
301
7b7d6727 302 usbh2: usb@53f80400 {
212d0b83
MG		 303 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
304 reg = <0x53f80400 0x0200>;
305 interrupts = <16>;
564695dd 306 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 307 fsl,usbmisc = <&usbmisc 2>;
212d0b83
MG		 308 status = "disabled";
309 };
310
7b7d6727 311 usbh3: usb@53f80600 {
212d0b83
MG		 312 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
313 reg = <0x53f80600 0x0200>;
314 interrupts = <17>;
564695dd 315 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 316 fsl,usbmisc = <&usbmisc 3>;
212d0b83
MG		 317 status = "disabled";
318 };
319
a5735021
MG		 320 usbmisc: usbmisc@53f80800 {
321 #index-cells = <1>;
322 compatible = "fsl,imx53-usbmisc";
323 reg = <0x53f80800 0x200>;
564695dd 324 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021
MG		 325 };
326
4d191868 327 gpio1: gpio@53f84000 {
aeb27748 328 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 329 reg = <0x53f84000 0x4000>;
330 interrupts = <50 51>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
88cde8b7 334 #interrupt-cells = <2>;
73d2b4cd
SG		 335 };
336
4d191868 337 gpio2: gpio@53f88000 {
aeb27748 338 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 339 reg = <0x53f88000 0x4000>;
340 interrupts = <52 53>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
88cde8b7 344 #interrupt-cells = <2>;
73d2b4cd
SG		 345 };
346
4d191868 347 gpio3: gpio@53f8c000 {
aeb27748 348 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 349 reg = <0x53f8c000 0x4000>;
350 interrupts = <54 55>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
88cde8b7 354 #interrupt-cells = <2>;
73d2b4cd
SG		 355 };
356
4d191868 357 gpio4: gpio@53f90000 {
aeb27748 358 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 359 reg = <0x53f90000 0x4000>;
360 interrupts = <56 57>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
88cde8b7 364 #interrupt-cells = <2>;
73d2b4cd
SG		 365 };
366
675e4d03
RL		 367 kpp: kpp@53f94000 {
368 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
369 reg = <0x53f94000 0x4000>;
370 interrupts = <60>;
564695dd 371 clocks = <&clks IMX5_CLK_DUMMY>;
675e4d03
RL		 372 status = "disabled";
373 };
374
7b7d6727 375 wdog1: wdog@53f98000 {
73d2b4cd
SG		 376 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
377 reg = <0x53f98000 0x4000>;
378 interrupts = <58>;
564695dd 379 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 380 };
381
7b7d6727 382 wdog2: wdog@53f9c000 {
73d2b4cd
SG		 383 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
384 reg = <0x53f9c000 0x4000>;
385 interrupts = <59>;
564695dd 386 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 387 status = "disabled";
388 };
389
cc8aae9b
SH		 390 gpt: timer@53fa0000 {
391 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
392 reg = <0x53fa0000 0x4000>;
393 interrupts = <39>;
564695dd
LS		 394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
395 <&clks IMX5_CLK_GPT_HF_GATE>;
cc8aae9b
SH		 396 clock-names = "ipg", "per";
397 };
398
7b7d6727 399 iomuxc: iomuxc@53fa8000 {
5be03a7b
SG		 400 compatible = "fsl,imx53-iomuxc";
401 reg = <0x53fa8000 0x4000>;
5be03a7b
SG		 402 };
403
5af9f143
PZ		 404 gpr: iomuxc-gpr@53fa8000 {
405 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
406 reg = <0x53fa8000 0xc>;
407 };
408
420714aa
PZ		 409 ldb: ldb@53fa8008 {
410 #address-cells = <1>;
411 #size-cells = <0>;
412 compatible = "fsl,imx53-ldb";
413 reg = <0x53fa8008 0x4>;
414 gpr = <&gpr>;
564695dd
LS		 415 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
416 <&clks IMX5_CLK_LDB_DI1_SEL>,
417 <&clks IMX5_CLK_IPU_DI0_SEL>,
418 <&clks IMX5_CLK_IPU_DI1_SEL>,
419 <&clks IMX5_CLK_LDB_DI0_GATE>,
420 <&clks IMX5_CLK_LDB_DI1_GATE>;
420714aa
PZ		 421 clock-names = "di0_pll", "di1_pll",
422 "di0_sel", "di1_sel",
423 "di0", "di1";
424 status = "disabled";
425
426 lvds-channel@0 {
427 reg = <0>;
420714aa 428 status = "disabled";
e05c8c9a
PZ		 429
430 port {
431 lvds0_in: endpoint {
432 remote-endpoint = <&ipu_di0_lvds0>;
433 };
434 };
420714aa
PZ		 435 };
436
437 lvds-channel@1 {
438 reg = <1>;
420714aa 439 status = "disabled";
e05c8c9a
PZ		 440
441 port {
442 lvds1_in: endpoint {
fa1746ae 443 remote-endpoint = <&ipu_di1_lvds1>;
e05c8c9a
PZ		 444 };
445 };
420714aa
PZ		 446 };
447 };
448
9ae90afa
SH		 449 pwm1: pwm@53fb4000 {
450 #pwm-cells = <2>;
451 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
452 reg = <0x53fb4000 0x4000>;
564695dd
LS		 453 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
454 <&clks IMX5_CLK_PWM1_HF_GATE>;
9ae90afa
SH		 455 clock-names = "ipg", "per";
456 interrupts = <61>;
457 };
458
459 pwm2: pwm@53fb8000 {
460 #pwm-cells = <2>;
461 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
462 reg = <0x53fb8000 0x4000>;
564695dd
LS		 463 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
464 <&clks IMX5_CLK_PWM2_HF_GATE>;
9ae90afa
SH		 465 clock-names = "ipg", "per";
466 interrupts = <94>;
467 };
468
0c456cfa 469 uart1: serial@53fbc000 {
73d2b4cd
SG		 470 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
471 reg = <0x53fbc000 0x4000>;
472 interrupts = <31>;
564695dd
LS		 473 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
474 <&clks IMX5_CLK_UART1_PER_GATE>;
f40f38d1 475 clock-names = "ipg", "per";
73d2b4cd
SG		 476 status = "disabled";
477 };
478
0c456cfa 479 uart2: serial@53fc0000 {
73d2b4cd
SG		 480 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
481 reg = <0x53fc0000 0x4000>;
482 interrupts = <32>;
564695dd
LS		 483 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
484 <&clks IMX5_CLK_UART2_PER_GATE>;
f40f38d1 485 clock-names = "ipg", "per";
73d2b4cd
SG		 486 status = "disabled";
487 };
488
a9d1f924
ST		 489 can1: can@53fc8000 {
490 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
491 reg = <0x53fc8000 0x4000>;
492 interrupts = <82>;
564695dd
LS		 493 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
494 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
f40f38d1 495 clock-names = "ipg", "per";
a9d1f924
ST		 496 status = "disabled";
497 };
498
499 can2: can@53fcc000 {
500 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
501 reg = <0x53fcc000 0x4000>;
502 interrupts = <83>;
564695dd
LS		 503 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
504 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
f40f38d1 505 clock-names = "ipg", "per";
a9d1f924
ST		 506 status = "disabled";
507 };
508
8d84c374
PZ		 509 src: src@53fd0000 {
510 compatible = "fsl,imx53-src", "fsl,imx51-src";
511 reg = <0x53fd0000 0x4000>;
512 #reset-cells = <1>;
513 };
514
f40f38d1
FE		 515 clks: ccm@53fd4000{
516 compatible = "fsl,imx53-ccm";
517 reg = <0x53fd4000 0x4000>;
518 interrupts = <0 71 0x04 0 72 0x04>;
519 #clock-cells = <1>;
520 };
521
4d191868 522 gpio5: gpio@53fdc000 {
aeb27748 523 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 524 reg = <0x53fdc000 0x4000>;
525 interrupts = <103 104>;
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
88cde8b7 529 #interrupt-cells = <2>;
73d2b4cd
SG		 530 };
531
4d191868 532 gpio6: gpio@53fe0000 {
aeb27748 533 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 534 reg = <0x53fe0000 0x4000>;
535 interrupts = <105 106>;
536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
88cde8b7 539 #interrupt-cells = <2>;
73d2b4cd
SG		 540 };
541
4d191868 542 gpio7: gpio@53fe4000 {
aeb27748 543 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 544 reg = <0x53fe4000 0x4000>;
545 interrupts = <107 108>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
88cde8b7 549 #interrupt-cells = <2>;
73d2b4cd
SG		 550 };
551
7b7d6727 552 i2c3: i2c@53fec000 {
73d2b4cd
SG		 553 #address-cells = <1>;
554 #size-cells = <0>;
5bdfba29 555 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 556 reg = <0x53fec000 0x4000>;
557 interrupts = <64>;
564695dd 558 clocks = <&clks IMX5_CLK_I2C3_GATE>;
73d2b4cd
SG		 559 status = "disabled";
560 };
561
0c456cfa 562 uart4: serial@53ff0000 {
73d2b4cd
SG		 563 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
564 reg = <0x53ff0000 0x4000>;
565 interrupts = <13>;
564695dd
LS		 566 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
567 <&clks IMX5_CLK_UART4_PER_GATE>;
f40f38d1 568 clock-names = "ipg", "per";
73d2b4cd
SG		 569 status = "disabled";
570 };
571 };
572
573 aips@60000000 { /* AIPS2 */
574 compatible = "fsl,aips-bus", "simple-bus";
575 #address-cells = <1>;
576 #size-cells = <1>;
577 reg = <0x60000000 0x10000000>;
578 ranges;
579
ac08281e
ST		 580 aipstz2: bridge@63f00000 {
581 compatible = "fsl,imx53-aipstz";
582 reg = <0x63f00000 0x60>;
583 };
584
4f3b2a41
SH		 585 iim: iim@63f98000 {
586 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
587 reg = <0x63f98000 0x4000>;
588 interrupts = <69>;
564695dd 589 clocks = <&clks IMX5_CLK_IIM_GATE>;
4f3b2a41
SH		 590 };
591
0c456cfa 592 uart5: serial@63f90000 {
73d2b4cd
SG		 593 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
594 reg = <0x63f90000 0x4000>;
595 interrupts = <86>;
564695dd
LS		 596 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
597 <&clks IMX5_CLK_UART5_PER_GATE>;
f40f38d1 598 clock-names = "ipg", "per";
73d2b4cd
SG		 599 status = "disabled";
600 };
601
a82b7b9c
MF		 602 owire: owire@63fa4000 {
603 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
604 reg = <0x63fa4000 0x4000>;
564695dd 605 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
a82b7b9c
MF		 606 status = "disabled";
607 };
608
7b7d6727 609 ecspi2: ecspi@63fac000 {
73d2b4cd
SG		 610 #address-cells = <1>;
611 #size-cells = <0>;
612 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
613 reg = <0x63fac000 0x4000>;
614 interrupts = <37>;
564695dd
LS		 615 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
616 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
f40f38d1 617 clock-names = "ipg", "per";
73d2b4cd
SG		 618 status = "disabled";
619 };
620
7b7d6727 621 sdma: sdma@63fb0000 {
73d2b4cd
SG		 622 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
623 reg = <0x63fb0000 0x4000>;
624 interrupts = <6>;
564695dd
LS		 625 clocks = <&clks IMX5_CLK_SDMA_GATE>,
626 <&clks IMX5_CLK_SDMA_GATE>;
f40f38d1 627 clock-names = "ipg", "ahb";
fb72bb21 628 #dma-cells = <3>;
7e4f0365 629 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd
SG		 630 };
631
7b7d6727 632 cspi: cspi@63fc0000 {
73d2b4cd
SG		 633 #address-cells = <1>;
634 #size-cells = <0>;
635 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
636 reg = <0x63fc0000 0x4000>;
637 interrupts = <38>;
564695dd
LS		 638 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
639 <&clks IMX5_CLK_CSPI_IPG_GATE>;
f40f38d1 640 clock-names = "ipg", "per";
73d2b4cd
SG		 641 status = "disabled";
642 };
643
7b7d6727 644 i2c2: i2c@63fc4000 {
73d2b4cd
SG		 645 #address-cells = <1>;
646 #size-cells = <0>;
5bdfba29 647 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 648 reg = <0x63fc4000 0x4000>;
649 interrupts = <63>;
564695dd 650 clocks = <&clks IMX5_CLK_I2C2_GATE>;
73d2b4cd
SG		 651 status = "disabled";
652 };
653
7b7d6727 654 i2c1: i2c@63fc8000 {
73d2b4cd
SG		 655 #address-cells = <1>;
656 #size-cells = <0>;
5bdfba29 657 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 658 reg = <0x63fc8000 0x4000>;
659 interrupts = <62>;
564695dd 660 clocks = <&clks IMX5_CLK_I2C1_GATE>;
73d2b4cd
SG		 661 status = "disabled";
662 };
663
ffc505c0 664 ssi1: ssi@63fcc000 {
6ff7f51e 665 #sound-dai-cells = <0>;
28f93d0b
MP		 666 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
667 "fsl,imx21-ssi";
ffc505c0
SG		 668 reg = <0x63fcc000 0x4000>;
669 interrupts = <29>;
564695dd 670 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
5da826ab
SG		 671 dmas = <&sdma 28 0 0>,
672 <&sdma 29 0 0>;
673 dma-names = "rx", "tx";
ffc505c0 674 fsl,fifo-depth = <15>;
ffc505c0
SG		 675 status = "disabled";
676 };
677
7b7d6727 678 audmux: audmux@63fd0000 {
ffc505c0
SG		 679 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
680 reg = <0x63fd0000 0x4000>;
681 status = "disabled";
682 };
683
7b7d6727 684 nfc: nand@63fdb000 {
75453a08
SH		 685 compatible = "fsl,imx53-nand";
686 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
687 interrupts = <8>;
564695dd 688 clocks = <&clks IMX5_CLK_NFC_GATE>;
75453a08
SH		 689 status = "disabled";
690 };
691
ffc505c0 692 ssi3: ssi@63fe8000 {
6ff7f51e 693 #sound-dai-cells = <0>;
28f93d0b
MP		 694 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
695 "fsl,imx21-ssi";
ffc505c0
SG		 696 reg = <0x63fe8000 0x4000>;
697 interrupts = <96>;
564695dd 698 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
5da826ab
SG		 699 dmas = <&sdma 46 0 0>,
700 <&sdma 47 0 0>;
701 dma-names = "rx", "tx";
ffc505c0 702 fsl,fifo-depth = <15>;
ffc505c0
SG		 703 status = "disabled";
704 };
705
7b7d6727 706 fec: ethernet@63fec000 {
73d2b4cd
SG		 707 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
708 reg = <0x63fec000 0x4000>;
709 interrupts = <87>;
564695dd
LS		 710 clocks = <&clks IMX5_CLK_FEC_GATE>,
711 <&clks IMX5_CLK_FEC_GATE>,
712 <&clks IMX5_CLK_FEC_GATE>;
f40f38d1 713 clock-names = "ipg", "ahb", "ptp";
73d2b4cd
SG		 714 status = "disabled";
715 };
19194c2b
PZ		 716
717 tve: tve@63ff0000 {
718 compatible = "fsl,imx53-tve";
719 reg = <0x63ff0000 0x1000>;
720 interrupts = <92>;
564695dd
LS		 721 clocks = <&clks IMX5_CLK_TVE_GATE>,
722 <&clks IMX5_CLK_IPU_DI1_SEL>;
19194c2b 723 clock-names = "tve", "di_sel";
19194c2b 724 status = "disabled";
e05c8c9a
PZ		 725
726 port {
727 tve_in: endpoint {
728 remote-endpoint = <&ipu_di1_tve>;
729 };
730 };
19194c2b 731 };
fbf970f6
FE		 732
733 vpu: vpu@63ff4000 {
734 compatible = "fsl,imx53-vpu";
735 reg = <0x63ff4000 0x1000>;
736 interrupts = <9>;
fa97d2f7 737 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
564695dd 738 <&clks IMX5_CLK_VPU_GATE>;
fbf970f6 739 clock-names = "per", "ahb";
b1e2e546 740 resets = <&src 1>;
fbf970f6 741 iram = <&ocram>;
fbf970f6 742 };
73d2b4cd 743 };
481fbe13
PZ		 744
745 ocram: sram@f8000000 {
746 compatible = "mmio-sram";
747 reg = <0xf8000000 0x20000>;
564695dd 748 clocks = <&clks IMX5_CLK_OCRAM>;
481fbe13 749 };
49bdf58e
ST		 750
751 pmu {
752 compatible = "arm,cortex-a8-pmu";
753 interrupts = <77>;
754 };
73d2b4cd
SG		 755 };
756};
Linux kernel - Deliverables
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