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ARM: mvebu: use stdout-path in all armada-*.dts
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
CommitLineData
73d2b4cd
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
e1641531 14#include "imx53-pinfunc.h"
564695dd 15#include <dt-bindings/clock/imx5-clock.h>
4e05a7af
DC		 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
73d2b4cd
SG		 18
19/ {
20 aliases {
22970070 21 ethernet0 = &fec;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
c60dc1d1
PZ		 29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
c63d06de
SH		 32 mmc0 = &esdhc1;
33 mmc1 = &esdhc2;
34 mmc2 = &esdhc3;
35 mmc3 = &esdhc4;
cf4e577e
SH		 36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 spi0 = &ecspi1;
42 spi1 = &ecspi2;
43 spi2 = &cspi;
73d2b4cd
SG		 44 };
45
070bd7e4
FE		 46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
791f4166 49 cpu0: cpu@0 {
070bd7e4
FE		 50 device_type = "cpu";
51 compatible = "arm,cortex-a8";
52 reg = <0x0>;
791f4166
LS		 53 clocks = <&clks IMX5_CLK_ARM>;
54 clock-latency = <61036>;
55 voltage-tolerance = <5>;
56 operating-points = <
57 /* kHz */
58 166666 850000
59 400000 900000
60 800000 1050000
61 1000000 1200000
62 1200000 1300000
63 >;
070bd7e4
FE		 64 };
65 };
66
e05c8c9a
PZ		 67 display-subsystem {
68 compatible = "fsl,imx-display-subsystem";
69 ports = <&ipu_di0>, <&ipu_di1>;
70 };
71
73d2b4cd
SG		 72 tzic: tz-interrupt-controller@0fffc000 {
73 compatible = "fsl,imx53-tzic", "fsl,tzic";
74 interrupt-controller;
75 #interrupt-cells = <1>;
76 reg = <0x0fffc000 0x4000>;
77 };
78
79 clocks {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 ckil {
84 compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043 85 #clock-cells = <0>;
73d2b4cd
SG		 86 clock-frequency = <32768>;
87 };
88
89 ckih1 {
90 compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043 91 #clock-cells = <0>;
73d2b4cd
SG		 92 clock-frequency = <22579200>;
93 };
94
95 ckih2 {
96 compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043 97 #clock-cells = <0>;
73d2b4cd
SG		 98 clock-frequency = <0>;
99 };
100
101 osc {
102 compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043 103 #clock-cells = <0>;
73d2b4cd
SG		 104 clock-frequency = <24000000>;
105 };
106 };
107
108 soc {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&tzic>;
113 ranges;
114
7affee43
MV		 115 sata: sata@10000000 {
116 compatible = "fsl,imx53-ahci";
117 reg = <0x10000000 0x1000>;
118 interrupts = <28>;
119 clocks = <&clks IMX5_CLK_SATA_GATE>,
120 <&clks IMX5_CLK_SATA_REF>,
121 <&clks IMX5_CLK_AHB>;
02578153 122 clock-names = "sata", "sata_ref", "ahb";
7affee43
MV		 123 status = "disabled";
124 };
125
abed9a6b 126 ipu: ipu@18000000 {
e05c8c9a
PZ		 127 #address-cells = <1>;
128 #size-cells = <0>;
abed9a6b 129 compatible = "fsl,imx53-ipu";
6d66da89 130 reg = <0x18000000 0x08000000>;
abed9a6b 131 interrupts = <11 10>;
564695dd
LS		 132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
4438a6a1 135 clock-names = "bus", "di0", "di1";
8d84c374 136 resets = <&src 2>;
e05c8c9a
PZ		 137
138 ipu_di0: port@2 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <2>;
142
143 ipu_di0_disp0: endpoint@0 {
144 reg = <0>;
145 };
146
147 ipu_di0_lvds0: endpoint@1 {
148 reg = <1>;
149 remote-endpoint = <&lvds0_in>;
150 };
151 };
152
153 ipu_di1: port@3 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 reg = <3>;
157
158 ipu_di1_disp1: endpoint@0 {
159 reg = <0>;
160 };
161
162 ipu_di1_lvds1: endpoint@1 {
163 reg = <1>;
164 remote-endpoint = <&lvds1_in>;
165 };
166
167 ipu_di1_tve: endpoint@2 {
168 reg = <2>;
169 remote-endpoint = <&tve_in>;
170 };
171 };
abed9a6b
SH		 172 };
173
73d2b4cd
SG		 174 aips@50000000 { /* AIPS1 */
175 compatible = "fsl,aips-bus", "simple-bus";
176 #address-cells = <1>;
177 #size-cells = <1>;
178 reg = <0x50000000 0x10000000>;
179 ranges;
180
181 spba@50000000 {
182 compatible = "fsl,spba-bus", "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 reg = <0x50000000 0x40000>;
186 ranges;
187
7b7d6727 188 esdhc1: esdhc@50004000 {
73d2b4cd
SG		 189 compatible = "fsl,imx53-esdhc";
190 reg = <0x50004000 0x4000>;
191 interrupts = <1>;
564695dd
LS		 192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
f40f38d1 195 clock-names = "ipg", "ahb", "per";
c104b6a2 196 bus-width = <4>;
73d2b4cd
SG		 197 status = "disabled";
198 };
199
7b7d6727 200 esdhc2: esdhc@50008000 {
73d2b4cd
SG		 201 compatible = "fsl,imx53-esdhc";
202 reg = <0x50008000 0x4000>;
203 interrupts = <2>;
564695dd
LS		 204 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
205 <&clks IMX5_CLK_DUMMY>,
206 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
f40f38d1 207 clock-names = "ipg", "ahb", "per";
c104b6a2 208 bus-width = <4>;
73d2b4cd
SG		 209 status = "disabled";
210 };
211
0c456cfa 212 uart3: serial@5000c000 {
73d2b4cd
SG		 213 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
214 reg = <0x5000c000 0x4000>;
215 interrupts = <33>;
564695dd
LS		 216 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
217 <&clks IMX5_CLK_UART3_PER_GATE>;
f40f38d1 218 clock-names = "ipg", "per";
73d2b4cd
SG		 219 status = "disabled";
220 };
221
7b7d6727 222 ecspi1: ecspi@50010000 {
73d2b4cd
SG		 223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
226 reg = <0x50010000 0x4000>;
227 interrupts = <36>;
564695dd
LS		 228 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
229 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
f40f38d1 230 clock-names = "ipg", "per";
73d2b4cd
SG		 231 status = "disabled";
232 };
233
ffc505c0 234 ssi2: ssi@50014000 {
6ff7f51e 235 #sound-dai-cells = <0>;
28f93d0b
MP		 236 compatible = "fsl,imx53-ssi",
237 "fsl,imx51-ssi",
238 "fsl,imx21-ssi";
ffc505c0
SG		 239 reg = <0x50014000 0x4000>;
240 interrupts = <30>;
685570ab
FE		 241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
242 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
243 clock-names = "ipg", "baud";
5da826ab
SG		 244 dmas = <&sdma 24 1 0>,
245 <&sdma 25 1 0>;
246 dma-names = "rx", "tx";
ffc505c0 247 fsl,fifo-depth = <15>;
ffc505c0
SG		 248 status = "disabled";
249 };
250
7b7d6727 251 esdhc3: esdhc@50020000 {
73d2b4cd
SG		 252 compatible = "fsl,imx53-esdhc";
253 reg = <0x50020000 0x4000>;
254 interrupts = <3>;
564695dd
LS		 255 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
256 <&clks IMX5_CLK_DUMMY>,
257 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
f40f38d1 258 clock-names = "ipg", "ahb", "per";
c104b6a2 259 bus-width = <4>;
73d2b4cd
SG		 260 status = "disabled";
261 };
262
7b7d6727 263 esdhc4: esdhc@50024000 {
73d2b4cd
SG		 264 compatible = "fsl,imx53-esdhc";
265 reg = <0x50024000 0x4000>;
266 interrupts = <4>;
564695dd
LS		 267 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
268 <&clks IMX5_CLK_DUMMY>,
269 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
f40f38d1 270 clock-names = "ipg", "ahb", "per";
c104b6a2 271 bus-width = <4>;
73d2b4cd
SG		 272 status = "disabled";
273 };
274 };
275
ac08281e
ST		 276 aipstz1: bridge@53f00000 {
277 compatible = "fsl,imx53-aipstz";
278 reg = <0x53f00000 0x60>;
279 };
280
a79025c4
MG		 281 usbphy0: usbphy@0 {
282 compatible = "usb-nop-xceiv";
564695dd 283 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
a79025c4
MG		 284 clock-names = "main_clk";
285 status = "okay";
286 };
287
288 usbphy1: usbphy@1 {
289 compatible = "usb-nop-xceiv";
564695dd 290 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
a79025c4
MG		 291 clock-names = "main_clk";
292 status = "okay";
293 };
294
7b7d6727 295 usbotg: usb@53f80000 {
212d0b83
MG		 296 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
297 reg = <0x53f80000 0x0200>;
298 interrupts = <18>;
564695dd 299 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 300 fsl,usbmisc = <&usbmisc 0>;
a79025c4 301 fsl,usbphy = <&usbphy0>;
212d0b83
MG		 302 status = "disabled";
303 };
304
7b7d6727 305 usbh1: usb@53f80200 {
212d0b83
MG		 306 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
307 reg = <0x53f80200 0x0200>;
308 interrupts = <14>;
564695dd 309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 310 fsl,usbmisc = <&usbmisc 1>;
a79025c4 311 fsl,usbphy = <&usbphy1>;
212d0b83
MG		 312 status = "disabled";
313 };
314
7b7d6727 315 usbh2: usb@53f80400 {
212d0b83
MG		 316 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
317 reg = <0x53f80400 0x0200>;
318 interrupts = <16>;
564695dd 319 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 320 fsl,usbmisc = <&usbmisc 2>;
212d0b83
MG		 321 status = "disabled";
322 };
323
7b7d6727 324 usbh3: usb@53f80600 {
212d0b83
MG		 325 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
326 reg = <0x53f80600 0x0200>;
327 interrupts = <17>;
564695dd 328 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 329 fsl,usbmisc = <&usbmisc 3>;
212d0b83
MG		 330 status = "disabled";
331 };
332
a5735021
MG		 333 usbmisc: usbmisc@53f80800 {
334 #index-cells = <1>;
335 compatible = "fsl,imx53-usbmisc";
336 reg = <0x53f80800 0x200>;
564695dd 337 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021
MG		 338 };
339
4d191868 340 gpio1: gpio@53f84000 {
aeb27748 341 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 342 reg = <0x53f84000 0x4000>;
343 interrupts = <50 51>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
88cde8b7 347 #interrupt-cells = <2>;
73d2b4cd
SG		 348 };
349
4d191868 350 gpio2: gpio@53f88000 {
aeb27748 351 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 352 reg = <0x53f88000 0x4000>;
353 interrupts = <52 53>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-controller;
88cde8b7 357 #interrupt-cells = <2>;
73d2b4cd
SG		 358 };
359
4d191868 360 gpio3: gpio@53f8c000 {
aeb27748 361 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 362 reg = <0x53f8c000 0x4000>;
363 interrupts = <54 55>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
88cde8b7 367 #interrupt-cells = <2>;
73d2b4cd
SG		 368 };
369
4d191868 370 gpio4: gpio@53f90000 {
aeb27748 371 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 372 reg = <0x53f90000 0x4000>;
373 interrupts = <56 57>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
88cde8b7 377 #interrupt-cells = <2>;
73d2b4cd
SG		 378 };
379
675e4d03
RL		 380 kpp: kpp@53f94000 {
381 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
382 reg = <0x53f94000 0x4000>;
383 interrupts = <60>;
564695dd 384 clocks = <&clks IMX5_CLK_DUMMY>;
675e4d03
RL		 385 status = "disabled";
386 };
387
7b7d6727 388 wdog1: wdog@53f98000 {
73d2b4cd
SG		 389 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
390 reg = <0x53f98000 0x4000>;
391 interrupts = <58>;
564695dd 392 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 393 };
394
7b7d6727 395 wdog2: wdog@53f9c000 {
73d2b4cd
SG		 396 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
397 reg = <0x53f9c000 0x4000>;
398 interrupts = <59>;
564695dd 399 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 400 status = "disabled";
401 };
402
cc8aae9b
SH		 403 gpt: timer@53fa0000 {
404 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
405 reg = <0x53fa0000 0x4000>;
406 interrupts = <39>;
564695dd
LS		 407 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
408 <&clks IMX5_CLK_GPT_HF_GATE>;
cc8aae9b
SH		 409 clock-names = "ipg", "per";
410 };
411
7b7d6727 412 iomuxc: iomuxc@53fa8000 {
5be03a7b
SG		 413 compatible = "fsl,imx53-iomuxc";
414 reg = <0x53fa8000 0x4000>;
5be03a7b
SG		 415 };
416
5af9f143
PZ		 417 gpr: iomuxc-gpr@53fa8000 {
418 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
419 reg = <0x53fa8000 0xc>;
420 };
421
420714aa
PZ		 422 ldb: ldb@53fa8008 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,imx53-ldb";
426 reg = <0x53fa8008 0x4>;
427 gpr = <&gpr>;
564695dd
LS		 428 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
429 <&clks IMX5_CLK_LDB_DI1_SEL>,
430 <&clks IMX5_CLK_IPU_DI0_SEL>,
431 <&clks IMX5_CLK_IPU_DI1_SEL>,
432 <&clks IMX5_CLK_LDB_DI0_GATE>,
433 <&clks IMX5_CLK_LDB_DI1_GATE>;
420714aa
PZ		 434 clock-names = "di0_pll", "di1_pll",
435 "di0_sel", "di1_sel",
436 "di0", "di1";
437 status = "disabled";
438
439 lvds-channel@0 {
1b134c9c
MN		 440 #address-cells = <1>;
441 #size-cells = <0>;
420714aa 442 reg = <0>;
420714aa 443 status = "disabled";
e05c8c9a 444
1b134c9c
MN		 445 port@0 {
446 reg = <0>;
447
e05c8c9a
PZ		 448 lvds0_in: endpoint {
449 remote-endpoint = <&ipu_di0_lvds0>;
450 };
451 };
420714aa
PZ		 452 };
453
454 lvds-channel@1 {
1b134c9c
MN		 455 #address-cells = <1>;
456 #size-cells = <0>;
420714aa 457 reg = <1>;
420714aa 458 status = "disabled";
e05c8c9a 459
1b134c9c
MN		 460 port@1 {
461 reg = <1>;
462
e05c8c9a 463 lvds1_in: endpoint {
fa1746ae 464 remote-endpoint = <&ipu_di1_lvds1>;
e05c8c9a
PZ		 465 };
466 };
420714aa
PZ		 467 };
468 };
469
9ae90afa
SH		 470 pwm1: pwm@53fb4000 {
471 #pwm-cells = <2>;
472 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
473 reg = <0x53fb4000 0x4000>;
564695dd
LS		 474 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
475 <&clks IMX5_CLK_PWM1_HF_GATE>;
9ae90afa
SH		 476 clock-names = "ipg", "per";
477 interrupts = <61>;
478 };
479
480 pwm2: pwm@53fb8000 {
481 #pwm-cells = <2>;
482 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
483 reg = <0x53fb8000 0x4000>;
564695dd
LS		 484 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
485 <&clks IMX5_CLK_PWM2_HF_GATE>;
9ae90afa
SH		 486 clock-names = "ipg", "per";
487 interrupts = <94>;
488 };
489
0c456cfa 490 uart1: serial@53fbc000 {
73d2b4cd
SG		 491 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
492 reg = <0x53fbc000 0x4000>;
493 interrupts = <31>;
564695dd
LS		 494 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
495 <&clks IMX5_CLK_UART1_PER_GATE>;
f40f38d1 496 clock-names = "ipg", "per";
73d2b4cd
SG		 497 status = "disabled";
498 };
499
0c456cfa 500 uart2: serial@53fc0000 {
73d2b4cd
SG		 501 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
502 reg = <0x53fc0000 0x4000>;
503 interrupts = <32>;
564695dd
LS		 504 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
505 <&clks IMX5_CLK_UART2_PER_GATE>;
f40f38d1 506 clock-names = "ipg", "per";
73d2b4cd
SG		 507 status = "disabled";
508 };
509
a9d1f924
ST		 510 can1: can@53fc8000 {
511 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
512 reg = <0x53fc8000 0x4000>;
513 interrupts = <82>;
564695dd
LS		 514 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
515 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
f40f38d1 516 clock-names = "ipg", "per";
a9d1f924
ST		 517 status = "disabled";
518 };
519
520 can2: can@53fcc000 {
521 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
522 reg = <0x53fcc000 0x4000>;
523 interrupts = <83>;
564695dd
LS		 524 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
525 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
f40f38d1 526 clock-names = "ipg", "per";
a9d1f924
ST		 527 status = "disabled";
528 };
529
8d84c374
PZ		 530 src: src@53fd0000 {
531 compatible = "fsl,imx53-src", "fsl,imx51-src";
532 reg = <0x53fd0000 0x4000>;
533 #reset-cells = <1>;
534 };
535
f40f38d1
FE		 536 clks: ccm@53fd4000{
537 compatible = "fsl,imx53-ccm";
538 reg = <0x53fd4000 0x4000>;
539 interrupts = <0 71 0x04 0 72 0x04>;
540 #clock-cells = <1>;
541 };
542
4d191868 543 gpio5: gpio@53fdc000 {
aeb27748 544 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 545 reg = <0x53fdc000 0x4000>;
546 interrupts = <103 104>;
547 gpio-controller;
548 #gpio-cells = <2>;
549 interrupt-controller;
88cde8b7 550 #interrupt-cells = <2>;
73d2b4cd
SG		 551 };
552
4d191868 553 gpio6: gpio@53fe0000 {
aeb27748 554 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 555 reg = <0x53fe0000 0x4000>;
556 interrupts = <105 106>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
88cde8b7 560 #interrupt-cells = <2>;
73d2b4cd
SG		 561 };
562
4d191868 563 gpio7: gpio@53fe4000 {
aeb27748 564 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 565 reg = <0x53fe4000 0x4000>;
566 interrupts = <107 108>;
567 gpio-controller;
568 #gpio-cells = <2>;
569 interrupt-controller;
88cde8b7 570 #interrupt-cells = <2>;
73d2b4cd
SG		 571 };
572
7b7d6727 573 i2c3: i2c@53fec000 {
73d2b4cd
SG		 574 #address-cells = <1>;
575 #size-cells = <0>;
5bdfba29 576 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 577 reg = <0x53fec000 0x4000>;
578 interrupts = <64>;
564695dd 579 clocks = <&clks IMX5_CLK_I2C3_GATE>;
73d2b4cd
SG		 580 status = "disabled";
581 };
582
0c456cfa 583 uart4: serial@53ff0000 {
73d2b4cd
SG		 584 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
585 reg = <0x53ff0000 0x4000>;
586 interrupts = <13>;
564695dd
LS		 587 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
588 <&clks IMX5_CLK_UART4_PER_GATE>;
f40f38d1 589 clock-names = "ipg", "per";
73d2b4cd
SG		 590 status = "disabled";
591 };
592 };
593
594 aips@60000000 { /* AIPS2 */
595 compatible = "fsl,aips-bus", "simple-bus";
596 #address-cells = <1>;
597 #size-cells = <1>;
598 reg = <0x60000000 0x10000000>;
599 ranges;
600
ac08281e
ST		 601 aipstz2: bridge@63f00000 {
602 compatible = "fsl,imx53-aipstz";
603 reg = <0x63f00000 0x60>;
604 };
605
4f3b2a41
SH		 606 iim: iim@63f98000 {
607 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
608 reg = <0x63f98000 0x4000>;
609 interrupts = <69>;
564695dd 610 clocks = <&clks IMX5_CLK_IIM_GATE>;
4f3b2a41
SH		 611 };
612
0c456cfa 613 uart5: serial@63f90000 {
73d2b4cd
SG		 614 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
615 reg = <0x63f90000 0x4000>;
616 interrupts = <86>;
564695dd
LS		 617 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
618 <&clks IMX5_CLK_UART5_PER_GATE>;
f40f38d1 619 clock-names = "ipg", "per";
73d2b4cd
SG		 620 status = "disabled";
621 };
622
a82b7b9c
MF		 623 owire: owire@63fa4000 {
624 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
625 reg = <0x63fa4000 0x4000>;
564695dd 626 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
a82b7b9c
MF		 627 status = "disabled";
628 };
629
7b7d6727 630 ecspi2: ecspi@63fac000 {
73d2b4cd
SG		 631 #address-cells = <1>;
632 #size-cells = <0>;
633 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
634 reg = <0x63fac000 0x4000>;
635 interrupts = <37>;
564695dd
LS		 636 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
637 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
f40f38d1 638 clock-names = "ipg", "per";
73d2b4cd
SG		 639 status = "disabled";
640 };
641
7b7d6727 642 sdma: sdma@63fb0000 {
73d2b4cd
SG		 643 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
644 reg = <0x63fb0000 0x4000>;
645 interrupts = <6>;
564695dd
LS		 646 clocks = <&clks IMX5_CLK_SDMA_GATE>,
647 <&clks IMX5_CLK_SDMA_GATE>;
f40f38d1 648 clock-names = "ipg", "ahb";
fb72bb21 649 #dma-cells = <3>;
7e4f0365 650 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd
SG		 651 };
652
7b7d6727 653 cspi: cspi@63fc0000 {
73d2b4cd
SG		 654 #address-cells = <1>;
655 #size-cells = <0>;
656 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
657 reg = <0x63fc0000 0x4000>;
658 interrupts = <38>;
564695dd
LS		 659 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
660 <&clks IMX5_CLK_CSPI_IPG_GATE>;
f40f38d1 661 clock-names = "ipg", "per";
73d2b4cd
SG		 662 status = "disabled";
663 };
664
7b7d6727 665 i2c2: i2c@63fc4000 {
73d2b4cd
SG		 666 #address-cells = <1>;
667 #size-cells = <0>;
5bdfba29 668 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 669 reg = <0x63fc4000 0x4000>;
670 interrupts = <63>;
564695dd 671 clocks = <&clks IMX5_CLK_I2C2_GATE>;
73d2b4cd
SG		 672 status = "disabled";
673 };
674
7b7d6727 675 i2c1: i2c@63fc8000 {
73d2b4cd
SG		 676 #address-cells = <1>;
677 #size-cells = <0>;
5bdfba29 678 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 679 reg = <0x63fc8000 0x4000>;
680 interrupts = <62>;
564695dd 681 clocks = <&clks IMX5_CLK_I2C1_GATE>;
73d2b4cd
SG		 682 status = "disabled";
683 };
684
ffc505c0 685 ssi1: ssi@63fcc000 {
6ff7f51e 686 #sound-dai-cells = <0>;
28f93d0b
MP		 687 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
688 "fsl,imx21-ssi";
ffc505c0
SG		 689 reg = <0x63fcc000 0x4000>;
690 interrupts = <29>;
685570ab
FE		 691 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
692 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
693 clock-names = "ipg", "baud";
5da826ab
SG		 694 dmas = <&sdma 28 0 0>,
695 <&sdma 29 0 0>;
696 dma-names = "rx", "tx";
ffc505c0 697 fsl,fifo-depth = <15>;
ffc505c0
SG		 698 status = "disabled";
699 };
700
7b7d6727 701 audmux: audmux@63fd0000 {
ffc505c0
SG		 702 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
703 reg = <0x63fd0000 0x4000>;
704 status = "disabled";
705 };
706
7b7d6727 707 nfc: nand@63fdb000 {
75453a08
SH		 708 compatible = "fsl,imx53-nand";
709 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
710 interrupts = <8>;
564695dd 711 clocks = <&clks IMX5_CLK_NFC_GATE>;
75453a08
SH		 712 status = "disabled";
713 };
714
ffc505c0 715 ssi3: ssi@63fe8000 {
6ff7f51e 716 #sound-dai-cells = <0>;
28f93d0b
MP		 717 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
718 "fsl,imx21-ssi";
ffc505c0
SG		 719 reg = <0x63fe8000 0x4000>;
720 interrupts = <96>;
685570ab
FE		 721 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
722 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
723 clock-names = "ipg", "baud";
5da826ab
SG		 724 dmas = <&sdma 46 0 0>,
725 <&sdma 47 0 0>;
726 dma-names = "rx", "tx";
ffc505c0 727 fsl,fifo-depth = <15>;
ffc505c0
SG		 728 status = "disabled";
729 };
730
7b7d6727 731 fec: ethernet@63fec000 {
73d2b4cd
SG		 732 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
733 reg = <0x63fec000 0x4000>;
734 interrupts = <87>;
564695dd
LS		 735 clocks = <&clks IMX5_CLK_FEC_GATE>,
736 <&clks IMX5_CLK_FEC_GATE>,
737 <&clks IMX5_CLK_FEC_GATE>;
f40f38d1 738 clock-names = "ipg", "ahb", "ptp";
73d2b4cd
SG		 739 status = "disabled";
740 };
19194c2b
PZ		 741
742 tve: tve@63ff0000 {
743 compatible = "fsl,imx53-tve";
744 reg = <0x63ff0000 0x1000>;
745 interrupts = <92>;
564695dd
LS		 746 clocks = <&clks IMX5_CLK_TVE_GATE>,
747 <&clks IMX5_CLK_IPU_DI1_SEL>;
19194c2b 748 clock-names = "tve", "di_sel";
19194c2b 749 status = "disabled";
e05c8c9a
PZ		 750
751 port {
752 tve_in: endpoint {
753 remote-endpoint = <&ipu_di1_tve>;
754 };
755 };
19194c2b 756 };
fbf970f6
FE		 757
758 vpu: vpu@63ff4000 {
71946619 759 compatible = "fsl,imx53-vpu", "cnm,coda7541";
fbf970f6
FE		 760 reg = <0x63ff4000 0x1000>;
761 interrupts = <9>;
fa97d2f7 762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
564695dd 763 <&clks IMX5_CLK_VPU_GATE>;
fbf970f6 764 clock-names = "per", "ahb";
b1e2e546 765 resets = <&src 1>;
fbf970f6 766 iram = <&ocram>;
fbf970f6 767 };
60811cc2
ST		 768
769 sahara: crypto@63ff8000 {
770 compatible = "fsl,imx53-sahara";
771 reg = <0x63ff8000 0x4000>;
772 interrupts = <19 20>;
773 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
774 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
775 clock-names = "ipg", "ahb";
776 };
73d2b4cd 777 };
481fbe13
PZ		 778
779 ocram: sram@f8000000 {
780 compatible = "mmio-sram";
781 reg = <0xf8000000 0x20000>;
564695dd 782 clocks = <&clks IMX5_CLK_OCRAM>;
481fbe13 783 };
49bdf58e
ST		 784
785 pmu {
786 compatible = "arm,cortex-a8-pmu";
787 interrupts = <77>;
788 };
73d2b4cd
SG		 789 };
790};
Linux kernel - Deliverables
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