Commit | Line | Data |
---|---|---|
73d2b4cd SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
36dffd8f | 13 | #include "skeleton.dtsi" |
e1641531 | 14 | #include "imx53-pinfunc.h" |
73d2b4cd SG |
15 | |
16 | / { | |
17 | aliases { | |
8f9ffecf RZ |
18 | serial0 = &uart1; |
19 | serial1 = &uart2; | |
20 | serial2 = &uart3; | |
21 | serial3 = &uart4; | |
22 | serial4 = &uart5; | |
5230f8fe SG |
23 | gpio0 = &gpio1; |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | gpio5 = &gpio6; | |
29 | gpio6 = &gpio7; | |
c60dc1d1 PZ |
30 | i2c0 = &i2c1; |
31 | i2c1 = &i2c2; | |
32 | i2c2 = &i2c3; | |
73d2b4cd SG |
33 | }; |
34 | ||
35 | tzic: tz-interrupt-controller@0fffc000 { | |
36 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
37 | interrupt-controller; | |
38 | #interrupt-cells = <1>; | |
39 | reg = <0x0fffc000 0x4000>; | |
40 | }; | |
41 | ||
42 | clocks { | |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | ckil { | |
47 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
48 | clock-frequency = <32768>; | |
49 | }; | |
50 | ||
51 | ckih1 { | |
52 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
53 | clock-frequency = <22579200>; | |
54 | }; | |
55 | ||
56 | ckih2 { | |
57 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
58 | clock-frequency = <0>; | |
59 | }; | |
60 | ||
61 | osc { | |
62 | compatible = "fsl,imx-osc", "fixed-clock"; | |
63 | clock-frequency = <24000000>; | |
64 | }; | |
65 | }; | |
66 | ||
67 | soc { | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | compatible = "simple-bus"; | |
71 | interrupt-parent = <&tzic>; | |
72 | ranges; | |
73 | ||
abed9a6b SH |
74 | ipu: ipu@18000000 { |
75 | #crtc-cells = <1>; | |
76 | compatible = "fsl,imx53-ipu"; | |
77 | reg = <0x18000000 0x080000000>; | |
78 | interrupts = <11 10>; | |
4438a6a1 PZ |
79 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; |
80 | clock-names = "bus", "di0", "di1"; | |
8d84c374 | 81 | resets = <&src 2>; |
abed9a6b SH |
82 | }; |
83 | ||
73d2b4cd SG |
84 | aips@50000000 { /* AIPS1 */ |
85 | compatible = "fsl,aips-bus", "simple-bus"; | |
86 | #address-cells = <1>; | |
87 | #size-cells = <1>; | |
88 | reg = <0x50000000 0x10000000>; | |
89 | ranges; | |
90 | ||
91 | spba@50000000 { | |
92 | compatible = "fsl,spba-bus", "simple-bus"; | |
93 | #address-cells = <1>; | |
94 | #size-cells = <1>; | |
95 | reg = <0x50000000 0x40000>; | |
96 | ranges; | |
97 | ||
7b7d6727 | 98 | esdhc1: esdhc@50004000 { |
73d2b4cd SG |
99 | compatible = "fsl,imx53-esdhc"; |
100 | reg = <0x50004000 0x4000>; | |
101 | interrupts = <1>; | |
f40f38d1 FE |
102 | clocks = <&clks 44>, <&clks 0>, <&clks 71>; |
103 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 104 | bus-width = <4>; |
73d2b4cd SG |
105 | status = "disabled"; |
106 | }; | |
107 | ||
7b7d6727 | 108 | esdhc2: esdhc@50008000 { |
73d2b4cd SG |
109 | compatible = "fsl,imx53-esdhc"; |
110 | reg = <0x50008000 0x4000>; | |
111 | interrupts = <2>; | |
f40f38d1 FE |
112 | clocks = <&clks 45>, <&clks 0>, <&clks 72>; |
113 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 114 | bus-width = <4>; |
73d2b4cd SG |
115 | status = "disabled"; |
116 | }; | |
117 | ||
0c456cfa | 118 | uart3: serial@5000c000 { |
73d2b4cd SG |
119 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
120 | reg = <0x5000c000 0x4000>; | |
121 | interrupts = <33>; | |
f40f38d1 FE |
122 | clocks = <&clks 32>, <&clks 33>; |
123 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
124 | status = "disabled"; |
125 | }; | |
126 | ||
7b7d6727 | 127 | ecspi1: ecspi@50010000 { |
73d2b4cd SG |
128 | #address-cells = <1>; |
129 | #size-cells = <0>; | |
130 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
131 | reg = <0x50010000 0x4000>; | |
132 | interrupts = <36>; | |
f40f38d1 FE |
133 | clocks = <&clks 51>, <&clks 52>; |
134 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
135 | status = "disabled"; |
136 | }; | |
137 | ||
ffc505c0 SG |
138 | ssi2: ssi@50014000 { |
139 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
140 | reg = <0x50014000 0x4000>; | |
141 | interrupts = <30>; | |
f40f38d1 | 142 | clocks = <&clks 49>; |
ffc505c0 SG |
143 | fsl,fifo-depth = <15>; |
144 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
145 | status = "disabled"; | |
146 | }; | |
147 | ||
7b7d6727 | 148 | esdhc3: esdhc@50020000 { |
73d2b4cd SG |
149 | compatible = "fsl,imx53-esdhc"; |
150 | reg = <0x50020000 0x4000>; | |
151 | interrupts = <3>; | |
f40f38d1 FE |
152 | clocks = <&clks 46>, <&clks 0>, <&clks 73>; |
153 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 154 | bus-width = <4>; |
73d2b4cd SG |
155 | status = "disabled"; |
156 | }; | |
157 | ||
7b7d6727 | 158 | esdhc4: esdhc@50024000 { |
73d2b4cd SG |
159 | compatible = "fsl,imx53-esdhc"; |
160 | reg = <0x50024000 0x4000>; | |
161 | interrupts = <4>; | |
f40f38d1 FE |
162 | clocks = <&clks 47>, <&clks 0>, <&clks 74>; |
163 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 164 | bus-width = <4>; |
73d2b4cd SG |
165 | status = "disabled"; |
166 | }; | |
167 | }; | |
168 | ||
a79025c4 MG |
169 | usbphy0: usbphy@0 { |
170 | compatible = "usb-nop-xceiv"; | |
171 | clocks = <&clks 124>; | |
172 | clock-names = "main_clk"; | |
173 | status = "okay"; | |
174 | }; | |
175 | ||
176 | usbphy1: usbphy@1 { | |
177 | compatible = "usb-nop-xceiv"; | |
178 | clocks = <&clks 125>; | |
179 | clock-names = "main_clk"; | |
180 | status = "okay"; | |
181 | }; | |
182 | ||
7b7d6727 | 183 | usbotg: usb@53f80000 { |
212d0b83 MG |
184 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
185 | reg = <0x53f80000 0x0200>; | |
186 | interrupts = <18>; | |
8e388908 | 187 | clocks = <&clks 108>; |
a5735021 | 188 | fsl,usbmisc = <&usbmisc 0>; |
a79025c4 | 189 | fsl,usbphy = <&usbphy0>; |
212d0b83 MG |
190 | status = "disabled"; |
191 | }; | |
192 | ||
7b7d6727 | 193 | usbh1: usb@53f80200 { |
212d0b83 MG |
194 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
195 | reg = <0x53f80200 0x0200>; | |
196 | interrupts = <14>; | |
8e388908 | 197 | clocks = <&clks 108>; |
a5735021 | 198 | fsl,usbmisc = <&usbmisc 1>; |
a79025c4 | 199 | fsl,usbphy = <&usbphy1>; |
212d0b83 MG |
200 | status = "disabled"; |
201 | }; | |
202 | ||
7b7d6727 | 203 | usbh2: usb@53f80400 { |
212d0b83 MG |
204 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
205 | reg = <0x53f80400 0x0200>; | |
206 | interrupts = <16>; | |
8e388908 | 207 | clocks = <&clks 108>; |
a5735021 | 208 | fsl,usbmisc = <&usbmisc 2>; |
212d0b83 MG |
209 | status = "disabled"; |
210 | }; | |
211 | ||
7b7d6727 | 212 | usbh3: usb@53f80600 { |
212d0b83 MG |
213 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
214 | reg = <0x53f80600 0x0200>; | |
215 | interrupts = <17>; | |
8e388908 | 216 | clocks = <&clks 108>; |
a5735021 | 217 | fsl,usbmisc = <&usbmisc 3>; |
212d0b83 MG |
218 | status = "disabled"; |
219 | }; | |
220 | ||
a5735021 MG |
221 | usbmisc: usbmisc@53f80800 { |
222 | #index-cells = <1>; | |
223 | compatible = "fsl,imx53-usbmisc"; | |
224 | reg = <0x53f80800 0x200>; | |
8e388908 | 225 | clocks = <&clks 108>; |
a5735021 MG |
226 | }; |
227 | ||
4d191868 | 228 | gpio1: gpio@53f84000 { |
aeb27748 | 229 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
230 | reg = <0x53f84000 0x4000>; |
231 | interrupts = <50 51>; | |
232 | gpio-controller; | |
233 | #gpio-cells = <2>; | |
234 | interrupt-controller; | |
88cde8b7 | 235 | #interrupt-cells = <2>; |
73d2b4cd SG |
236 | }; |
237 | ||
4d191868 | 238 | gpio2: gpio@53f88000 { |
aeb27748 | 239 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
240 | reg = <0x53f88000 0x4000>; |
241 | interrupts = <52 53>; | |
242 | gpio-controller; | |
243 | #gpio-cells = <2>; | |
244 | interrupt-controller; | |
88cde8b7 | 245 | #interrupt-cells = <2>; |
73d2b4cd SG |
246 | }; |
247 | ||
4d191868 | 248 | gpio3: gpio@53f8c000 { |
aeb27748 | 249 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
250 | reg = <0x53f8c000 0x4000>; |
251 | interrupts = <54 55>; | |
252 | gpio-controller; | |
253 | #gpio-cells = <2>; | |
254 | interrupt-controller; | |
88cde8b7 | 255 | #interrupt-cells = <2>; |
73d2b4cd SG |
256 | }; |
257 | ||
4d191868 | 258 | gpio4: gpio@53f90000 { |
aeb27748 | 259 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
260 | reg = <0x53f90000 0x4000>; |
261 | interrupts = <56 57>; | |
262 | gpio-controller; | |
263 | #gpio-cells = <2>; | |
264 | interrupt-controller; | |
88cde8b7 | 265 | #interrupt-cells = <2>; |
73d2b4cd SG |
266 | }; |
267 | ||
7b7d6727 | 268 | wdog1: wdog@53f98000 { |
73d2b4cd SG |
269 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
270 | reg = <0x53f98000 0x4000>; | |
271 | interrupts = <58>; | |
f40f38d1 | 272 | clocks = <&clks 0>; |
73d2b4cd SG |
273 | }; |
274 | ||
7b7d6727 | 275 | wdog2: wdog@53f9c000 { |
73d2b4cd SG |
276 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
277 | reg = <0x53f9c000 0x4000>; | |
278 | interrupts = <59>; | |
f40f38d1 | 279 | clocks = <&clks 0>; |
73d2b4cd SG |
280 | status = "disabled"; |
281 | }; | |
282 | ||
cc8aae9b SH |
283 | gpt: timer@53fa0000 { |
284 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
285 | reg = <0x53fa0000 0x4000>; | |
286 | interrupts = <39>; | |
287 | clocks = <&clks 36>, <&clks 41>; | |
288 | clock-names = "ipg", "per"; | |
289 | }; | |
290 | ||
7b7d6727 | 291 | iomuxc: iomuxc@53fa8000 { |
5be03a7b SG |
292 | compatible = "fsl,imx53-iomuxc"; |
293 | reg = <0x53fa8000 0x4000>; | |
294 | ||
295 | audmux { | |
296 | pinctrl_audmux_1: audmuxgrp-1 { | |
297 | fsl,pins = < | |
e1641531 SG |
298 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 |
299 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | |
300 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | |
301 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | |
5be03a7b SG |
302 | >; |
303 | }; | |
dd04c17b MV |
304 | |
305 | pinctrl_audmux_2: audmuxgrp-2 { | |
306 | fsl,pins = < | |
307 | MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 | |
308 | MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 | |
309 | MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 | |
310 | MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 | |
311 | >; | |
312 | }; | |
5be03a7b SG |
313 | }; |
314 | ||
315 | fec { | |
316 | pinctrl_fec_1: fecgrp-1 { | |
317 | fsl,pins = < | |
e1641531 SG |
318 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 |
319 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | |
320 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | |
321 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | |
322 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | |
323 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | |
324 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | |
325 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | |
326 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | |
327 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | |
5be03a7b SG |
328 | >; |
329 | }; | |
330 | }; | |
331 | ||
11ab21e9 ST |
332 | csi { |
333 | pinctrl_csi_1: csigrp-1 { | |
334 | fsl,pins = < | |
e1641531 SG |
335 | MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 |
336 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 | |
337 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 | |
338 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | |
339 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 | |
340 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 | |
341 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 | |
342 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 | |
343 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 | |
344 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 | |
345 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 | |
346 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 | |
347 | MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 | |
348 | MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 | |
349 | MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 | |
350 | MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 | |
351 | MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 | |
352 | MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 | |
353 | MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 | |
354 | MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 | |
355 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | |
11ab21e9 ST |
356 | >; |
357 | }; | |
358 | }; | |
359 | ||
360 | cspi { | |
361 | pinctrl_cspi_1: cspigrp-1 { | |
362 | fsl,pins = < | |
e1641531 SG |
363 | MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 |
364 | MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 | |
365 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 | |
11ab21e9 ST |
366 | >; |
367 | }; | |
368 | }; | |
369 | ||
327a79c0 SG |
370 | ecspi1 { |
371 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
372 | fsl,pins = < | |
e1641531 SG |
373 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 |
374 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | |
375 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | |
327a79c0 SG |
376 | >; |
377 | }; | |
378 | }; | |
379 | ||
5be03a7b SG |
380 | esdhc1 { |
381 | pinctrl_esdhc1_1: esdhc1grp-1 { | |
382 | fsl,pins = < | |
e1641531 SG |
383 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
384 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | |
385 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | |
386 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | |
387 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | |
388 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | |
5be03a7b SG |
389 | >; |
390 | }; | |
4bb6143c SG |
391 | |
392 | pinctrl_esdhc1_2: esdhc1grp-2 { | |
393 | fsl,pins = < | |
e1641531 SG |
394 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
395 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | |
396 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | |
397 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | |
398 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 | |
399 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 | |
400 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 | |
401 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 | |
402 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | |
403 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | |
4bb6143c SG |
404 | >; |
405 | }; | |
5be03a7b SG |
406 | }; |
407 | ||
07248042 SG |
408 | esdhc2 { |
409 | pinctrl_esdhc2_1: esdhc2grp-1 { | |
410 | fsl,pins = < | |
e1641531 SG |
411 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 |
412 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | |
413 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | |
414 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | |
415 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | |
416 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | |
07248042 SG |
417 | >; |
418 | }; | |
419 | }; | |
420 | ||
5be03a7b SG |
421 | esdhc3 { |
422 | pinctrl_esdhc3_1: esdhc3grp-1 { | |
423 | fsl,pins = < | |
e1641531 SG |
424 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 |
425 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 | |
426 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 | |
427 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 | |
428 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 | |
429 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 | |
430 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 | |
431 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 | |
432 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 | |
433 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 | |
5be03a7b SG |
434 | >; |
435 | }; | |
436 | }; | |
437 | ||
a1fff236 RS |
438 | can1 { |
439 | pinctrl_can1_1: can1grp-1 { | |
440 | fsl,pins = < | |
e1641531 SG |
441 | MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 |
442 | MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000 | |
a1fff236 RS |
443 | >; |
444 | }; | |
11ab21e9 ST |
445 | |
446 | pinctrl_can1_2: can1grp-2 { | |
447 | fsl,pins = < | |
e1641531 SG |
448 | MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 |
449 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 | |
11ab21e9 ST |
450 | >; |
451 | }; | |
0f14ac4e MV |
452 | |
453 | pinctrl_can1_3: can1grp-3 { | |
454 | fsl,pins = < | |
455 | MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 | |
456 | MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 | |
457 | >; | |
458 | }; | |
a1fff236 RS |
459 | }; |
460 | ||
461 | can2 { | |
462 | pinctrl_can2_1: can2grp-1 { | |
463 | fsl,pins = < | |
e1641531 SG |
464 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 |
465 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 | |
a1fff236 RS |
466 | >; |
467 | }; | |
468 | }; | |
469 | ||
5be03a7b SG |
470 | i2c1 { |
471 | pinctrl_i2c1_1: i2c1grp-1 { | |
472 | fsl,pins = < | |
e1641531 SG |
473 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 |
474 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 | |
5be03a7b SG |
475 | >; |
476 | }; | |
d7974714 MV |
477 | |
478 | pinctrl_i2c1_2: i2c1grp-2 { | |
479 | fsl,pins = < | |
480 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | |
481 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | |
482 | >; | |
483 | }; | |
5be03a7b SG |
484 | }; |
485 | ||
486 | i2c2 { | |
487 | pinctrl_i2c2_1: i2c2grp-1 { | |
488 | fsl,pins = < | |
e1641531 SG |
489 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 |
490 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | |
5be03a7b SG |
491 | >; |
492 | }; | |
ed5be465 MV |
493 | |
494 | pinctrl_i2c2_2: i2c2grp-2 { | |
495 | fsl,pins = < | |
496 | MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 | |
497 | MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 | |
498 | >; | |
499 | }; | |
5be03a7b SG |
500 | }; |
501 | ||
a1fff236 RS |
502 | i2c3 { |
503 | pinctrl_i2c3_1: i2c3grp-1 { | |
504 | fsl,pins = < | |
e1641531 SG |
505 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 |
506 | MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 | |
a1fff236 RS |
507 | >; |
508 | }; | |
509 | }; | |
510 | ||
9f7fbb15 MV |
511 | ipu_disp1 { |
512 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | |
513 | fsl,pins = < | |
514 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 | |
515 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 | |
516 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 | |
517 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 | |
518 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 | |
519 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 | |
520 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 | |
521 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 | |
522 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 | |
523 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 | |
524 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | |
525 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | |
526 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | |
527 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | |
528 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | |
529 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | |
530 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | |
531 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | |
532 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | |
533 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | |
534 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | |
535 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | |
536 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | |
537 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | |
538 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | |
539 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | |
540 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | |
541 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | |
542 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | |
543 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | |
544 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | |
545 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | |
546 | >; | |
547 | }; | |
548 | }; | |
549 | ||
550 | ipu_disp2 { | |
551 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | |
552 | fsl,pins = < | |
553 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | |
554 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | |
555 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | |
556 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | |
557 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | |
558 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | |
559 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | |
560 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | |
561 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | |
562 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | |
563 | >; | |
564 | }; | |
565 | }; | |
566 | ||
efee5e14 MV |
567 | nand { |
568 | pinctrl_nand_1: nandgrp-1 { | |
569 | fsl,pins = < | |
570 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | |
571 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | |
572 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | |
573 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | |
574 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | |
575 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | |
576 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | |
577 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 | |
578 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 | |
579 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 | |
580 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 | |
581 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 | |
582 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 | |
583 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 | |
584 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 | |
585 | >; | |
586 | }; | |
587 | }; | |
588 | ||
a82b7b9c MF |
589 | owire { |
590 | pinctrl_owire_1: owiregrp-1 { | |
591 | fsl,pins = < | |
e1641531 | 592 | MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000 |
a82b7b9c MF |
593 | >; |
594 | }; | |
595 | }; | |
596 | ||
95050497 MV |
597 | pwm1 { |
598 | pinctrl_pwm1_1: pwm1grp-1 { | |
599 | fsl,pins = < | |
600 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | |
601 | >; | |
602 | }; | |
603 | }; | |
604 | ||
5be03a7b SG |
605 | uart1 { |
606 | pinctrl_uart1_1: uart1grp-1 { | |
607 | fsl,pins = < | |
e1641531 SG |
608 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5 |
609 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5 | |
5be03a7b SG |
610 | >; |
611 | }; | |
4bb6143c SG |
612 | |
613 | pinctrl_uart1_2: uart1grp-2 { | |
614 | fsl,pins = < | |
e1641531 SG |
615 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5 |
616 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 | |
4bb6143c SG |
617 | >; |
618 | }; | |
5be03a7b | 619 | }; |
07248042 SG |
620 | |
621 | uart2 { | |
622 | pinctrl_uart2_1: uart2grp-1 { | |
623 | fsl,pins = < | |
e1641531 SG |
624 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 |
625 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | |
07248042 SG |
626 | >; |
627 | }; | |
628 | }; | |
629 | ||
630 | uart3 { | |
631 | pinctrl_uart3_1: uart3grp-1 { | |
632 | fsl,pins = < | |
e1641531 SG |
633 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 |
634 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 | |
635 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5 | |
636 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5 | |
07248042 SG |
637 | >; |
638 | }; | |
11ab21e9 ST |
639 | |
640 | pinctrl_uart3_2: uart3grp-2 { | |
641 | fsl,pins = < | |
e1641531 SG |
642 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 |
643 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 | |
11ab21e9 ST |
644 | >; |
645 | }; | |
646 | ||
07248042 | 647 | }; |
a1fff236 RS |
648 | |
649 | uart4 { | |
650 | pinctrl_uart4_1: uart4grp-1 { | |
651 | fsl,pins = < | |
e1641531 SG |
652 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5 |
653 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5 | |
a1fff236 RS |
654 | >; |
655 | }; | |
656 | }; | |
657 | ||
658 | uart5 { | |
659 | pinctrl_uart5_1: uart5grp-1 { | |
660 | fsl,pins = < | |
e1641531 SG |
661 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5 |
662 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5 | |
a1fff236 RS |
663 | >; |
664 | }; | |
665 | }; | |
5be03a7b SG |
666 | }; |
667 | ||
5af9f143 PZ |
668 | gpr: iomuxc-gpr@53fa8000 { |
669 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
670 | reg = <0x53fa8000 0xc>; | |
671 | }; | |
672 | ||
420714aa PZ |
673 | ldb: ldb@53fa8008 { |
674 | #address-cells = <1>; | |
675 | #size-cells = <0>; | |
676 | compatible = "fsl,imx53-ldb"; | |
677 | reg = <0x53fa8008 0x4>; | |
678 | gpr = <&gpr>; | |
679 | clocks = <&clks 122>, <&clks 120>, | |
680 | <&clks 115>, <&clks 116>, | |
681 | <&clks 123>, <&clks 85>; | |
682 | clock-names = "di0_pll", "di1_pll", | |
683 | "di0_sel", "di1_sel", | |
684 | "di0", "di1"; | |
685 | status = "disabled"; | |
686 | ||
687 | lvds-channel@0 { | |
688 | reg = <0>; | |
689 | crtcs = <&ipu 0>; | |
690 | status = "disabled"; | |
691 | }; | |
692 | ||
693 | lvds-channel@1 { | |
694 | reg = <1>; | |
695 | crtcs = <&ipu 1>; | |
696 | status = "disabled"; | |
697 | }; | |
698 | }; | |
699 | ||
9ae90afa SH |
700 | pwm1: pwm@53fb4000 { |
701 | #pwm-cells = <2>; | |
702 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
703 | reg = <0x53fb4000 0x4000>; | |
704 | clocks = <&clks 37>, <&clks 38>; | |
705 | clock-names = "ipg", "per"; | |
706 | interrupts = <61>; | |
707 | }; | |
708 | ||
709 | pwm2: pwm@53fb8000 { | |
710 | #pwm-cells = <2>; | |
711 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
712 | reg = <0x53fb8000 0x4000>; | |
713 | clocks = <&clks 39>, <&clks 40>; | |
714 | clock-names = "ipg", "per"; | |
715 | interrupts = <94>; | |
716 | }; | |
717 | ||
0c456cfa | 718 | uart1: serial@53fbc000 { |
73d2b4cd SG |
719 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
720 | reg = <0x53fbc000 0x4000>; | |
721 | interrupts = <31>; | |
f40f38d1 FE |
722 | clocks = <&clks 28>, <&clks 29>; |
723 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
724 | status = "disabled"; |
725 | }; | |
726 | ||
0c456cfa | 727 | uart2: serial@53fc0000 { |
73d2b4cd SG |
728 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
729 | reg = <0x53fc0000 0x4000>; | |
730 | interrupts = <32>; | |
f40f38d1 FE |
731 | clocks = <&clks 30>, <&clks 31>; |
732 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
733 | status = "disabled"; |
734 | }; | |
735 | ||
a9d1f924 ST |
736 | can1: can@53fc8000 { |
737 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
738 | reg = <0x53fc8000 0x4000>; | |
739 | interrupts = <82>; | |
f40f38d1 FE |
740 | clocks = <&clks 158>, <&clks 157>; |
741 | clock-names = "ipg", "per"; | |
a9d1f924 ST |
742 | status = "disabled"; |
743 | }; | |
744 | ||
745 | can2: can@53fcc000 { | |
746 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
747 | reg = <0x53fcc000 0x4000>; | |
748 | interrupts = <83>; | |
e37f0d5b | 749 | clocks = <&clks 87>, <&clks 86>; |
f40f38d1 | 750 | clock-names = "ipg", "per"; |
a9d1f924 ST |
751 | status = "disabled"; |
752 | }; | |
753 | ||
8d84c374 PZ |
754 | src: src@53fd0000 { |
755 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
756 | reg = <0x53fd0000 0x4000>; | |
757 | #reset-cells = <1>; | |
758 | }; | |
759 | ||
f40f38d1 FE |
760 | clks: ccm@53fd4000{ |
761 | compatible = "fsl,imx53-ccm"; | |
762 | reg = <0x53fd4000 0x4000>; | |
763 | interrupts = <0 71 0x04 0 72 0x04>; | |
764 | #clock-cells = <1>; | |
765 | }; | |
766 | ||
4d191868 | 767 | gpio5: gpio@53fdc000 { |
aeb27748 | 768 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
769 | reg = <0x53fdc000 0x4000>; |
770 | interrupts = <103 104>; | |
771 | gpio-controller; | |
772 | #gpio-cells = <2>; | |
773 | interrupt-controller; | |
88cde8b7 | 774 | #interrupt-cells = <2>; |
73d2b4cd SG |
775 | }; |
776 | ||
4d191868 | 777 | gpio6: gpio@53fe0000 { |
aeb27748 | 778 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
779 | reg = <0x53fe0000 0x4000>; |
780 | interrupts = <105 106>; | |
781 | gpio-controller; | |
782 | #gpio-cells = <2>; | |
783 | interrupt-controller; | |
88cde8b7 | 784 | #interrupt-cells = <2>; |
73d2b4cd SG |
785 | }; |
786 | ||
4d191868 | 787 | gpio7: gpio@53fe4000 { |
aeb27748 | 788 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
73d2b4cd SG |
789 | reg = <0x53fe4000 0x4000>; |
790 | interrupts = <107 108>; | |
791 | gpio-controller; | |
792 | #gpio-cells = <2>; | |
793 | interrupt-controller; | |
88cde8b7 | 794 | #interrupt-cells = <2>; |
73d2b4cd SG |
795 | }; |
796 | ||
7b7d6727 | 797 | i2c3: i2c@53fec000 { |
73d2b4cd SG |
798 | #address-cells = <1>; |
799 | #size-cells = <0>; | |
5bdfba29 | 800 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
801 | reg = <0x53fec000 0x4000>; |
802 | interrupts = <64>; | |
f40f38d1 | 803 | clocks = <&clks 88>; |
73d2b4cd SG |
804 | status = "disabled"; |
805 | }; | |
806 | ||
0c456cfa | 807 | uart4: serial@53ff0000 { |
73d2b4cd SG |
808 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
809 | reg = <0x53ff0000 0x4000>; | |
810 | interrupts = <13>; | |
f40f38d1 FE |
811 | clocks = <&clks 65>, <&clks 66>; |
812 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
813 | status = "disabled"; |
814 | }; | |
815 | }; | |
816 | ||
817 | aips@60000000 { /* AIPS2 */ | |
818 | compatible = "fsl,aips-bus", "simple-bus"; | |
819 | #address-cells = <1>; | |
820 | #size-cells = <1>; | |
821 | reg = <0x60000000 0x10000000>; | |
822 | ranges; | |
823 | ||
0c456cfa | 824 | uart5: serial@63f90000 { |
73d2b4cd SG |
825 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
826 | reg = <0x63f90000 0x4000>; | |
827 | interrupts = <86>; | |
f40f38d1 FE |
828 | clocks = <&clks 67>, <&clks 68>; |
829 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
830 | status = "disabled"; |
831 | }; | |
832 | ||
a82b7b9c MF |
833 | owire: owire@63fa4000 { |
834 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
835 | reg = <0x63fa4000 0x4000>; | |
836 | clocks = <&clks 159>; | |
837 | status = "disabled"; | |
838 | }; | |
839 | ||
7b7d6727 | 840 | ecspi2: ecspi@63fac000 { |
73d2b4cd SG |
841 | #address-cells = <1>; |
842 | #size-cells = <0>; | |
843 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
844 | reg = <0x63fac000 0x4000>; | |
845 | interrupts = <37>; | |
f40f38d1 FE |
846 | clocks = <&clks 53>, <&clks 54>; |
847 | clock-names = "ipg", "per"; | |
73d2b4cd SG |
848 | status = "disabled"; |
849 | }; | |
850 | ||
7b7d6727 | 851 | sdma: sdma@63fb0000 { |
73d2b4cd SG |
852 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
853 | reg = <0x63fb0000 0x4000>; | |
854 | interrupts = <6>; | |
f40f38d1 FE |
855 | clocks = <&clks 56>, <&clks 56>; |
856 | clock-names = "ipg", "ahb"; | |
7e4f0365 | 857 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
73d2b4cd SG |
858 | }; |
859 | ||
7b7d6727 | 860 | cspi: cspi@63fc0000 { |
73d2b4cd SG |
861 | #address-cells = <1>; |
862 | #size-cells = <0>; | |
863 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
864 | reg = <0x63fc0000 0x4000>; | |
865 | interrupts = <38>; | |
37523dc5 | 866 | clocks = <&clks 55>, <&clks 55>; |
f40f38d1 | 867 | clock-names = "ipg", "per"; |
73d2b4cd SG |
868 | status = "disabled"; |
869 | }; | |
870 | ||
7b7d6727 | 871 | i2c2: i2c@63fc4000 { |
73d2b4cd SG |
872 | #address-cells = <1>; |
873 | #size-cells = <0>; | |
5bdfba29 | 874 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
875 | reg = <0x63fc4000 0x4000>; |
876 | interrupts = <63>; | |
f40f38d1 | 877 | clocks = <&clks 35>; |
73d2b4cd SG |
878 | status = "disabled"; |
879 | }; | |
880 | ||
7b7d6727 | 881 | i2c1: i2c@63fc8000 { |
73d2b4cd SG |
882 | #address-cells = <1>; |
883 | #size-cells = <0>; | |
5bdfba29 | 884 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
73d2b4cd SG |
885 | reg = <0x63fc8000 0x4000>; |
886 | interrupts = <62>; | |
f40f38d1 | 887 | clocks = <&clks 34>; |
73d2b4cd SG |
888 | status = "disabled"; |
889 | }; | |
890 | ||
ffc505c0 SG |
891 | ssi1: ssi@63fcc000 { |
892 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
893 | reg = <0x63fcc000 0x4000>; | |
894 | interrupts = <29>; | |
f40f38d1 | 895 | clocks = <&clks 48>; |
ffc505c0 SG |
896 | fsl,fifo-depth = <15>; |
897 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
898 | status = "disabled"; | |
899 | }; | |
900 | ||
7b7d6727 | 901 | audmux: audmux@63fd0000 { |
ffc505c0 SG |
902 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
903 | reg = <0x63fd0000 0x4000>; | |
904 | status = "disabled"; | |
905 | }; | |
906 | ||
7b7d6727 | 907 | nfc: nand@63fdb000 { |
75453a08 SH |
908 | compatible = "fsl,imx53-nand"; |
909 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
910 | interrupts = <8>; | |
f40f38d1 | 911 | clocks = <&clks 60>; |
75453a08 SH |
912 | status = "disabled"; |
913 | }; | |
914 | ||
ffc505c0 SG |
915 | ssi3: ssi@63fe8000 { |
916 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | |
917 | reg = <0x63fe8000 0x4000>; | |
918 | interrupts = <96>; | |
f40f38d1 | 919 | clocks = <&clks 50>; |
ffc505c0 SG |
920 | fsl,fifo-depth = <15>; |
921 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ | |
922 | status = "disabled"; | |
923 | }; | |
924 | ||
7b7d6727 | 925 | fec: ethernet@63fec000 { |
73d2b4cd SG |
926 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
927 | reg = <0x63fec000 0x4000>; | |
928 | interrupts = <87>; | |
f40f38d1 FE |
929 | clocks = <&clks 42>, <&clks 42>, <&clks 42>; |
930 | clock-names = "ipg", "ahb", "ptp"; | |
73d2b4cd SG |
931 | status = "disabled"; |
932 | }; | |
933 | }; | |
934 | }; | |
935 | }; |