[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		mmc0 = &esdhc1;
		mmc1 = &esdhc2;
		mmc2 = &esdhc3;
		mmc3 = &esdhc4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &cspi;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		sata: sata@10000000 {
			compatible = "fsl,imx53-ahci";
			reg = <0x10000000 0x1000>;
			interrupts = <28>;
			clocks = <&clks IMX5_CLK_SATA_GATE>,
				 <&clks IMX5_CLK_SATA_REF>,
				 <&clks IMX5_CLK_AHB>;
			clock-names = "sata_gate", "sata_ref", "ahb";
			status = "disabled";
		};

		ipu: ipu@18000000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx53-ipu";
			reg = <0x18000000 0x080000000>;
			interrupts = <11 10>;
			clocks = <&clks IMX5_CLK_IPU_GATE>,
			         <&clks IMX5_CLK_IPU_DI0_GATE>,
			         <&clks IMX5_CLK_IPU_DI1_GATE>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 2>;
		};

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx53-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
					         <&clks IMX5_CLK_UART3_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
					dmas = <&sdma 24 1 0>,
					       <&sdma 25 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbphy0: usbphy@0 {
				compatible = "usb-nop-xceiv";
				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
				clock-names = "main_clk";
				status = "okay";
			};

			usbphy1: usbphy@1 {
				compatible = "usb-nop-xceiv";
				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
				clock-names = "main_clk";
				status = "okay";
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				fsl,usbmisc = <&usbmisc 0>;
				fsl,usbphy = <&usbphy0>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				fsl,usbmisc = <&usbmisc 1>;
				fsl,usbphy = <&usbphy1>;
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				fsl,usbmisc = <&usbmisc 2>;
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				fsl,usbmisc = <&usbmisc 3>;
				status = "disabled";
			};

			usbmisc: usbmisc@53f80800 {
				#index-cells = <1>;
				compatible = "fsl,imx53-usbmisc";
				reg = <0x53f80800 0x200>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			kpp: kpp@53f94000 {
				compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
				reg = <0x53f94000 0x4000>;
				interrupts = <60>;
				clocks = <&clks IMX5_CLK_DUMMY>;
				status = "disabled";
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks IMX5_CLK_DUMMY>;
			};

			wdog2: wdog@53f9c000 {
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f9c000 0x4000>;
				interrupts = <59>;
				clocks = <&clks IMX5_CLK_DUMMY>;
				status = "disabled";
			};

			gpt: timer@53fa0000 {
				compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
				reg = <0x53fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
				         <&clks IMX5_CLK_GPT_HF_GATE>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;
			};

			gpr: iomuxc-gpr@53fa8000 {
				compatible = "fsl,imx53-iomuxc-gpr", "syscon";
				reg = <0x53fa8000 0xc>;
			};

			ldb: ldb@53fa8008 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-ldb";
				reg = <0x53fa8008 0x4>;
				gpr = <&gpr>;
				clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
				         <&clks IMX5_CLK_LDB_DI1_SEL>,
				         <&clks IMX5_CLK_IPU_DI0_SEL>,
				         <&clks IMX5_CLK_IPU_DI1_SEL>,
				         <&clks IMX5_CLK_LDB_DI0_GATE>,
				         <&clks IMX5_CLK_LDB_DI1_GATE>;
				clock-names = "di0_pll", "di1_pll",
					      "di0_sel", "di1_sel",
					      "di0", "di1";
				status = "disabled";

				lvds-channel@0 {
					reg = <0>;
					crtcs = <&ipu 0>;
					status = "disabled";
				};

				lvds-channel@1 {
					reg = <1>;
					crtcs = <&ipu 1>;
					status = "disabled";
				};
			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
				         <&clks IMX5_CLK_PWM1_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
				         <&clks IMX5_CLK_PWM2_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
				         <&clks IMX5_CLK_UART1_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
				         <&clks IMX5_CLK_UART2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			can1: can@53fc8000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fc8000 0x4000>;
				interrupts = <82>;
				clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
				         <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			can2: can@53fcc000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fcc000 0x4000>;
				interrupts = <83>;
				clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
				         <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@53fd0000 {
				compatible = "fsl,imx53-src", "fsl,imx51-src";
				reg = <0x53fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx53-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@53fe4000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe4000 0x4000>;
				interrupts = <107 108>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks IMX5_CLK_I2C3_GATE>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
				         <&clks IMX5_CLK_UART4_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			iim: iim@63f98000 {
				compatible = "fsl,imx53-iim", "fsl,imx27-iim";
				reg = <0x63f98000 0x4000>;
				interrupts = <69>;
				clocks = <&clks IMX5_CLK_IIM_GATE>;
			};

			uart5: serial@63f90000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
				         <&clks IMX5_CLK_UART5_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx53-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks IMX5_CLK_SDMA_GATE>,
				         <&clks IMX5_CLK_SDMA_GATE>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks IMX5_CLK_I2C2_GATE>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks IMX5_CLK_I2C1_GATE>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
				dmas = <&sdma 28 0 0>,
				       <&sdma 29 0 0>;
				dma-names = "rx", "tx";
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			nfc: nand@63fdb000 {
				compatible = "fsl,imx53-nand";
				reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
				interrupts = <8>;
				clocks = <&clks IMX5_CLK_NFC_GATE>;
				status = "disabled";
			};

			ssi3: ssi@63fe8000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fe8000 0x4000>;
				interrupts = <96>;
				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
				dmas = <&sdma 46 0 0>,
				       <&sdma 47 0 0>;
				dma-names = "rx", "tx";
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};

			tve: tve@63ff0000 {
				compatible = "fsl,imx53-tve";
				reg = <0x63ff0000 0x1000>;
				interrupts = <92>;
				clocks = <&clks IMX5_CLK_TVE_GATE>,
				         <&clks IMX5_CLK_IPU_DI1_SEL>;
				clock-names = "tve", "di_sel";
				crtcs = <&ipu 1>;
				status = "disabled";
			};

			vpu: vpu@63ff4000 {
				compatible = "fsl,imx53-vpu";
				reg = <0x63ff4000 0x1000>;
				interrupts = <9>;
				clocks = <&clks IMX5_CLK_VPU_GATE>,
				         <&clks IMX5_CLK_VPU_GATE>;
				clock-names = "per", "ahb";
				iram = <&ocram>;
				status = "disabled";
			};
		};

		ocram: sram@f8000000 {
			compatible = "mmio-sram";
			reg = <0xf8000000 0x20000>;
			clocks = <&clks IMX5_CLK_OCRAM>;
		};
	};
};
Commit	Line	Data
73d2b4cd SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
36dffd8f	13	#include "skeleton.dtsi"
e1641531	14	#include "imx53-pinfunc.h"
564695dd	15	#include <dt-bindings/clock/imx5-clock.h>
4e05a7af DC	16	#include <dt-bindings/gpio/gpio.h>
4e05a7af DC	17	#include <dt-bindings/input/input.h>
73d2b4cd SG	18
	19	/ {
	20	aliases {
5230f8fe SG	21	gpio0 = &gpio1;
	22	gpio1 = &gpio2;
	23	gpio2 = &gpio3;
	24	gpio3 = &gpio4;
	25	gpio4 = &gpio5;
	26	gpio5 = &gpio6;
	27	gpio6 = &gpio7;
c60dc1d1 PZ	28	i2c0 = &i2c1;
	29	i2c1 = &i2c2;
	30	i2c2 = &i2c3;
c63d06de SH	31	mmc0 = &esdhc1;
	32	mmc1 = &esdhc2;
	33	mmc2 = &esdhc3;
	34	mmc3 = &esdhc4;
cf4e577e SH	35	serial0 = &uart1;
	36	serial1 = &uart2;
	37	serial2 = &uart3;
	38	serial3 = &uart4;
	39	serial4 = &uart5;
	40	spi0 = &ecspi1;
	41	spi1 = &ecspi2;
	42	spi2 = &cspi;
73d2b4cd SG	43	};
73d2b4cd SG	44
070bd7e4 FE	45	cpus {
	46	#address-cells = <1>;
	47	#size-cells = <0>;
	48	cpu@0 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a8";
	51	reg = <0x0>;
	52	};
	53	};
	54
73d2b4cd SG	55	tzic: tz-interrupt-controller@0fffc000 {
	56	compatible = "fsl,imx53-tzic", "fsl,tzic";
	57	interrupt-controller;
	58	#interrupt-cells = <1>;
	59	reg = <0x0fffc000 0x4000>;
	60	};
	61
	62	clocks {
	63	#address-cells = <1>;
	64	#size-cells = <0>;
	65
	66	ckil {
	67	compatible = "fsl,imx-ckil", "fixed-clock";
	68	clock-frequency = <32768>;
	69	};
	70
	71	ckih1 {
	72	compatible = "fsl,imx-ckih1", "fixed-clock";
	73	clock-frequency = <22579200>;
	74	};
	75
	76	ckih2 {
	77	compatible = "fsl,imx-ckih2", "fixed-clock";
	78	clock-frequency = <0>;
	79	};
	80
	81	osc {
	82	compatible = "fsl,imx-osc", "fixed-clock";
	83	clock-frequency = <24000000>;
	84	};
	85	};
	86
	87	soc {
	88	#address-cells = <1>;
	89	#size-cells = <1>;
	90	compatible = "simple-bus";
	91	interrupt-parent = <&tzic>;
	92	ranges;
	93
7affee43 MV	94	sata: sata@10000000 {
	95	compatible = "fsl,imx53-ahci";
	96	reg = <0x10000000 0x1000>;
	97	interrupts = <28>;
	98	clocks = <&clks IMX5_CLK_SATA_GATE>,
	99	<&clks IMX5_CLK_SATA_REF>,
	100	<&clks IMX5_CLK_AHB>;
	101	clock-names = "sata_gate", "sata_ref", "ahb";
	102	status = "disabled";
	103	};
	104
abed9a6b SH	105	ipu: ipu@18000000 {
	106	#crtc-cells = <1>;
	107	compatible = "fsl,imx53-ipu";
	108	reg = <0x18000000 0x080000000>;
	109	interrupts = <11 10>;
564695dd LS	110	clocks = <&clks IMX5_CLK_IPU_GATE>,
	111	<&clks IMX5_CLK_IPU_DI0_GATE>,
	112	<&clks IMX5_CLK_IPU_DI1_GATE>;
4438a6a1	113	clock-names = "bus", "di0", "di1";
8d84c374	114	resets = <&src 2>;
abed9a6b SH	115	};
abed9a6b SH	116
73d2b4cd SG	117	aips@50000000 { /* AIPS1 */
	118	compatible = "fsl,aips-bus", "simple-bus";
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	reg = <0x50000000 0x10000000>;
	122	ranges;
	123
	124	spba@50000000 {
	125	compatible = "fsl,spba-bus", "simple-bus";
	126	#address-cells = <1>;
	127	#size-cells = <1>;
	128	reg = <0x50000000 0x40000>;
	129	ranges;
	130
7b7d6727	131	esdhc1: esdhc@50004000 {
73d2b4cd SG	132	compatible = "fsl,imx53-esdhc";
	133	reg = <0x50004000 0x4000>;
	134	interrupts = <1>;
564695dd LS	135	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	136	<&clks IMX5_CLK_DUMMY>,
	137	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
f40f38d1	138	clock-names = "ipg", "ahb", "per";
c104b6a2	139	bus-width = <4>;
73d2b4cd SG	140	status = "disabled";
	141	};
	142
7b7d6727	143	esdhc2: esdhc@50008000 {
73d2b4cd SG	144	compatible = "fsl,imx53-esdhc";
	145	reg = <0x50008000 0x4000>;
	146	interrupts = <2>;
564695dd LS	147	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	148	<&clks IMX5_CLK_DUMMY>,
	149	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
f40f38d1	150	clock-names = "ipg", "ahb", "per";
c104b6a2	151	bus-width = <4>;
73d2b4cd SG	152	status = "disabled";
	153	};
	154
0c456cfa	155	uart3: serial@5000c000 {
73d2b4cd SG	156	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	157	reg = <0x5000c000 0x4000>;
	158	interrupts = <33>;
564695dd LS	159	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
564695dd LS	160	<&clks IMX5_CLK_UART3_PER_GATE>;
f40f38d1	161	clock-names = "ipg", "per";
73d2b4cd SG	162	status = "disabled";
	163	};
	164
7b7d6727	165	ecspi1: ecspi@50010000 {
73d2b4cd SG	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	169	reg = <0x50010000 0x4000>;
	170	interrupts = <36>;
564695dd LS	171	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
564695dd LS	172	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
f40f38d1	173	clock-names = "ipg", "per";
73d2b4cd SG	174	status = "disabled";
	175	};
	176
ffc505c0 SG	177	ssi2: ssi@50014000 {
	178	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	179	reg = <0x50014000 0x4000>;
	180	interrupts = <30>;
564695dd	181	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
5da826ab SG	182	dmas = <&sdma 24 1 0>,
	183	<&sdma 25 1 0>;
	184	dma-names = "rx", "tx";
ffc505c0 SG	185	fsl,fifo-depth = <15>;
	186	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	187	status = "disabled";
	188	};
	189
7b7d6727	190	esdhc3: esdhc@50020000 {
73d2b4cd SG	191	compatible = "fsl,imx53-esdhc";
	192	reg = <0x50020000 0x4000>;
	193	interrupts = <3>;
564695dd LS	194	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	195	<&clks IMX5_CLK_DUMMY>,
	196	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
f40f38d1	197	clock-names = "ipg", "ahb", "per";
c104b6a2	198	bus-width = <4>;
73d2b4cd SG	199	status = "disabled";
	200	};
	201
7b7d6727	202	esdhc4: esdhc@50024000 {
73d2b4cd SG	203	compatible = "fsl,imx53-esdhc";
	204	reg = <0x50024000 0x4000>;
	205	interrupts = <4>;
564695dd LS	206	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	207	<&clks IMX5_CLK_DUMMY>,
	208	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
f40f38d1	209	clock-names = "ipg", "ahb", "per";
c104b6a2	210	bus-width = <4>;
73d2b4cd SG	211	status = "disabled";
	212	};
	213	};
	214
a79025c4 MG	215	usbphy0: usbphy@0 {
a79025c4 MG	216	compatible = "usb-nop-xceiv";
564695dd	217	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
a79025c4 MG	218	clock-names = "main_clk";
	219	status = "okay";
	220	};
	221
	222	usbphy1: usbphy@1 {
	223	compatible = "usb-nop-xceiv";
564695dd	224	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
a79025c4 MG	225	clock-names = "main_clk";
	226	status = "okay";
	227	};
	228
7b7d6727	229	usbotg: usb@53f80000 {
212d0b83 MG	230	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	231	reg = <0x53f80000 0x0200>;
	232	interrupts = <18>;
564695dd	233	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021	234	fsl,usbmisc = <&usbmisc 0>;
a79025c4	235	fsl,usbphy = <&usbphy0>;
212d0b83 MG	236	status = "disabled";
	237	};
	238
7b7d6727	239	usbh1: usb@53f80200 {
212d0b83 MG	240	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	241	reg = <0x53f80200 0x0200>;
	242	interrupts = <14>;
564695dd	243	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021	244	fsl,usbmisc = <&usbmisc 1>;
a79025c4	245	fsl,usbphy = <&usbphy1>;
212d0b83 MG	246	status = "disabled";
	247	};
	248
7b7d6727	249	usbh2: usb@53f80400 {
212d0b83 MG	250	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	251	reg = <0x53f80400 0x0200>;
	252	interrupts = <16>;
564695dd	253	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021	254	fsl,usbmisc = <&usbmisc 2>;
212d0b83 MG	255	status = "disabled";
	256	};
	257
7b7d6727	258	usbh3: usb@53f80600 {
212d0b83 MG	259	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	260	reg = <0x53f80600 0x0200>;
	261	interrupts = <17>;
564695dd	262	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021	263	fsl,usbmisc = <&usbmisc 3>;
212d0b83 MG	264	status = "disabled";
	265	};
	266
a5735021 MG	267	usbmisc: usbmisc@53f80800 {
	268	#index-cells = <1>;
	269	compatible = "fsl,imx53-usbmisc";
	270	reg = <0x53f80800 0x200>;
564695dd	271	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 MG	272	};
a5735021 MG	273
4d191868	274	gpio1: gpio@53f84000 {
aeb27748	275	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	276	reg = <0x53f84000 0x4000>;
	277	interrupts = <50 51>;
	278	gpio-controller;
	279	#gpio-cells = <2>;
	280	interrupt-controller;
88cde8b7	281	#interrupt-cells = <2>;
73d2b4cd SG	282	};
73d2b4cd SG	283
4d191868	284	gpio2: gpio@53f88000 {
aeb27748	285	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	286	reg = <0x53f88000 0x4000>;
	287	interrupts = <52 53>;
	288	gpio-controller;
	289	#gpio-cells = <2>;
	290	interrupt-controller;
88cde8b7	291	#interrupt-cells = <2>;
73d2b4cd SG	292	};
73d2b4cd SG	293
4d191868	294	gpio3: gpio@53f8c000 {
aeb27748	295	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	296	reg = <0x53f8c000 0x4000>;
	297	interrupts = <54 55>;
	298	gpio-controller;
	299	#gpio-cells = <2>;
	300	interrupt-controller;
88cde8b7	301	#interrupt-cells = <2>;
73d2b4cd SG	302	};
73d2b4cd SG	303
4d191868	304	gpio4: gpio@53f90000 {
aeb27748	305	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	306	reg = <0x53f90000 0x4000>;
	307	interrupts = <56 57>;
	308	gpio-controller;
	309	#gpio-cells = <2>;
	310	interrupt-controller;
88cde8b7	311	#interrupt-cells = <2>;
73d2b4cd SG	312	};
73d2b4cd SG	313
675e4d03 RL	314	kpp: kpp@53f94000 {
	315	compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
	316	reg = <0x53f94000 0x4000>;
	317	interrupts = <60>;
564695dd	318	clocks = <&clks IMX5_CLK_DUMMY>;
675e4d03 RL	319	status = "disabled";
	320	};
	321
7b7d6727	322	wdog1: wdog@53f98000 {
73d2b4cd SG	323	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	324	reg = <0x53f98000 0x4000>;
	325	interrupts = <58>;
564695dd	326	clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd SG	327	};
73d2b4cd SG	328
7b7d6727	329	wdog2: wdog@53f9c000 {
73d2b4cd SG	330	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	331	reg = <0x53f9c000 0x4000>;
	332	interrupts = <59>;
564695dd	333	clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd SG	334	status = "disabled";
	335	};
	336
cc8aae9b SH	337	gpt: timer@53fa0000 {
	338	compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
	339	reg = <0x53fa0000 0x4000>;
	340	interrupts = <39>;
564695dd LS	341	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
564695dd LS	342	<&clks IMX5_CLK_GPT_HF_GATE>;
cc8aae9b SH	343	clock-names = "ipg", "per";
	344	};
	345
7b7d6727	346	iomuxc: iomuxc@53fa8000 {
5be03a7b SG	347	compatible = "fsl,imx53-iomuxc";
5be03a7b SG	348	reg = <0x53fa8000 0x4000>;
5be03a7b SG	349	};
5be03a7b SG	350
5af9f143 PZ	351	gpr: iomuxc-gpr@53fa8000 {
	352	compatible = "fsl,imx53-iomuxc-gpr", "syscon";
	353	reg = <0x53fa8000 0xc>;
	354	};
	355
420714aa PZ	356	ldb: ldb@53fa8008 {
	357	#address-cells = <1>;
	358	#size-cells = <0>;
	359	compatible = "fsl,imx53-ldb";
	360	reg = <0x53fa8008 0x4>;
	361	gpr = <&gpr>;
564695dd LS	362	clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
	363	<&clks IMX5_CLK_LDB_DI1_SEL>,
	364	<&clks IMX5_CLK_IPU_DI0_SEL>,
	365	<&clks IMX5_CLK_IPU_DI1_SEL>,
	366	<&clks IMX5_CLK_LDB_DI0_GATE>,
	367	<&clks IMX5_CLK_LDB_DI1_GATE>;
420714aa PZ	368	clock-names = "di0_pll", "di1_pll",
	369	"di0_sel", "di1_sel",
	370	"di0", "di1";
	371	status = "disabled";
	372
	373	lvds-channel@0 {
	374	reg = <0>;
	375	crtcs = <&ipu 0>;
	376	status = "disabled";
	377	};
	378
	379	lvds-channel@1 {
	380	reg = <1>;
	381	crtcs = <&ipu 1>;
	382	status = "disabled";
	383	};
	384	};
	385
9ae90afa SH	386	pwm1: pwm@53fb4000 {
	387	#pwm-cells = <2>;
	388	compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
	389	reg = <0x53fb4000 0x4000>;
564695dd LS	390	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
564695dd LS	391	<&clks IMX5_CLK_PWM1_HF_GATE>;
9ae90afa SH	392	clock-names = "ipg", "per";
	393	interrupts = <61>;
	394	};
	395
	396	pwm2: pwm@53fb8000 {
	397	#pwm-cells = <2>;
	398	compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
	399	reg = <0x53fb8000 0x4000>;
564695dd LS	400	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
564695dd LS	401	<&clks IMX5_CLK_PWM2_HF_GATE>;
9ae90afa SH	402	clock-names = "ipg", "per";
	403	interrupts = <94>;
	404	};
	405
0c456cfa	406	uart1: serial@53fbc000 {
73d2b4cd SG	407	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	408	reg = <0x53fbc000 0x4000>;
	409	interrupts = <31>;
564695dd LS	410	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
564695dd LS	411	<&clks IMX5_CLK_UART1_PER_GATE>;
f40f38d1	412	clock-names = "ipg", "per";
73d2b4cd SG	413	status = "disabled";
	414	};
	415
0c456cfa	416	uart2: serial@53fc0000 {
73d2b4cd SG	417	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	418	reg = <0x53fc0000 0x4000>;
	419	interrupts = <32>;
564695dd LS	420	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
564695dd LS	421	<&clks IMX5_CLK_UART2_PER_GATE>;
f40f38d1	422	clock-names = "ipg", "per";
73d2b4cd SG	423	status = "disabled";
	424	};
	425
a9d1f924 ST	426	can1: can@53fc8000 {
	427	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	428	reg = <0x53fc8000 0x4000>;
	429	interrupts = <82>;
564695dd LS	430	clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
564695dd LS	431	<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
f40f38d1	432	clock-names = "ipg", "per";
a9d1f924 ST	433	status = "disabled";
	434	};
	435
	436	can2: can@53fcc000 {
	437	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	438	reg = <0x53fcc000 0x4000>;
	439	interrupts = <83>;
564695dd LS	440	clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
564695dd LS	441	<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
f40f38d1	442	clock-names = "ipg", "per";
a9d1f924 ST	443	status = "disabled";
	444	};
	445
8d84c374 PZ	446	src: src@53fd0000 {
	447	compatible = "fsl,imx53-src", "fsl,imx51-src";
	448	reg = <0x53fd0000 0x4000>;
	449	#reset-cells = <1>;
	450	};
	451
f40f38d1 FE	452	clks: ccm@53fd4000{
	453	compatible = "fsl,imx53-ccm";
	454	reg = <0x53fd4000 0x4000>;
	455	interrupts = <0 71 0x04 0 72 0x04>;
	456	#clock-cells = <1>;
	457	};
	458
4d191868	459	gpio5: gpio@53fdc000 {
aeb27748	460	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	461	reg = <0x53fdc000 0x4000>;
	462	interrupts = <103 104>;
	463	gpio-controller;
	464	#gpio-cells = <2>;
	465	interrupt-controller;
88cde8b7	466	#interrupt-cells = <2>;
73d2b4cd SG	467	};
73d2b4cd SG	468
4d191868	469	gpio6: gpio@53fe0000 {
aeb27748	470	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	471	reg = <0x53fe0000 0x4000>;
	472	interrupts = <105 106>;
	473	gpio-controller;
	474	#gpio-cells = <2>;
	475	interrupt-controller;
88cde8b7	476	#interrupt-cells = <2>;
73d2b4cd SG	477	};
73d2b4cd SG	478
4d191868	479	gpio7: gpio@53fe4000 {
aeb27748	480	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	481	reg = <0x53fe4000 0x4000>;
	482	interrupts = <107 108>;
	483	gpio-controller;
	484	#gpio-cells = <2>;
	485	interrupt-controller;
88cde8b7	486	#interrupt-cells = <2>;
73d2b4cd SG	487	};
73d2b4cd SG	488
7b7d6727	489	i2c3: i2c@53fec000 {
73d2b4cd SG	490	#address-cells = <1>;
73d2b4cd SG	491	#size-cells = <0>;
5bdfba29	492	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd SG	493	reg = <0x53fec000 0x4000>;
73d2b4cd SG	494	interrupts = <64>;
564695dd	495	clocks = <&clks IMX5_CLK_I2C3_GATE>;
73d2b4cd SG	496	status = "disabled";
	497	};
	498
0c456cfa	499	uart4: serial@53ff0000 {
73d2b4cd SG	500	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	501	reg = <0x53ff0000 0x4000>;
	502	interrupts = <13>;
564695dd LS	503	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
564695dd LS	504	<&clks IMX5_CLK_UART4_PER_GATE>;
f40f38d1	505	clock-names = "ipg", "per";
73d2b4cd SG	506	status = "disabled";
	507	};
	508	};
	509
	510	aips@60000000 { /* AIPS2 */
	511	compatible = "fsl,aips-bus", "simple-bus";
	512	#address-cells = <1>;
	513	#size-cells = <1>;
	514	reg = <0x60000000 0x10000000>;
	515	ranges;
	516
4f3b2a41 SH	517	iim: iim@63f98000 {
	518	compatible = "fsl,imx53-iim", "fsl,imx27-iim";
	519	reg = <0x63f98000 0x4000>;
	520	interrupts = <69>;
564695dd	521	clocks = <&clks IMX5_CLK_IIM_GATE>;
4f3b2a41 SH	522	};
4f3b2a41 SH	523
0c456cfa	524	uart5: serial@63f90000 {
73d2b4cd SG	525	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	526	reg = <0x63f90000 0x4000>;
	527	interrupts = <86>;
564695dd LS	528	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
564695dd LS	529	<&clks IMX5_CLK_UART5_PER_GATE>;
f40f38d1	530	clock-names = "ipg", "per";
73d2b4cd SG	531	status = "disabled";
	532	};
	533
a82b7b9c MF	534	owire: owire@63fa4000 {
	535	compatible = "fsl,imx53-owire", "fsl,imx21-owire";
	536	reg = <0x63fa4000 0x4000>;
564695dd	537	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
a82b7b9c MF	538	status = "disabled";
	539	};
	540
7b7d6727	541	ecspi2: ecspi@63fac000 {
73d2b4cd SG	542	#address-cells = <1>;
	543	#size-cells = <0>;
	544	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	545	reg = <0x63fac000 0x4000>;
	546	interrupts = <37>;
564695dd LS	547	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
564695dd LS	548	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
f40f38d1	549	clock-names = "ipg", "per";
73d2b4cd SG	550	status = "disabled";
	551	};
	552
7b7d6727	553	sdma: sdma@63fb0000 {
73d2b4cd SG	554	compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
	555	reg = <0x63fb0000 0x4000>;
	556	interrupts = <6>;
564695dd LS	557	clocks = <&clks IMX5_CLK_SDMA_GATE>,
564695dd LS	558	<&clks IMX5_CLK_SDMA_GATE>;
f40f38d1	559	clock-names = "ipg", "ahb";
fb72bb21	560	#dma-cells = <3>;
7e4f0365	561	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd SG	562	};
73d2b4cd SG	563
7b7d6727	564	cspi: cspi@63fc0000 {
73d2b4cd SG	565	#address-cells = <1>;
	566	#size-cells = <0>;
	567	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
	568	reg = <0x63fc0000 0x4000>;
	569	interrupts = <38>;
564695dd LS	570	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
564695dd LS	571	<&clks IMX5_CLK_CSPI_IPG_GATE>;
f40f38d1	572	clock-names = "ipg", "per";
73d2b4cd SG	573	status = "disabled";
	574	};
	575
7b7d6727	576	i2c2: i2c@63fc4000 {
73d2b4cd SG	577	#address-cells = <1>;
73d2b4cd SG	578	#size-cells = <0>;
5bdfba29	579	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd SG	580	reg = <0x63fc4000 0x4000>;
73d2b4cd SG	581	interrupts = <63>;
564695dd	582	clocks = <&clks IMX5_CLK_I2C2_GATE>;
73d2b4cd SG	583	status = "disabled";
	584	};
	585
7b7d6727	586	i2c1: i2c@63fc8000 {
73d2b4cd SG	587	#address-cells = <1>;
73d2b4cd SG	588	#size-cells = <0>;
5bdfba29	589	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd SG	590	reg = <0x63fc8000 0x4000>;
73d2b4cd SG	591	interrupts = <62>;
564695dd	592	clocks = <&clks IMX5_CLK_I2C1_GATE>;
73d2b4cd SG	593	status = "disabled";
	594	};
	595
ffc505c0 SG	596	ssi1: ssi@63fcc000 {
	597	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	598	reg = <0x63fcc000 0x4000>;
	599	interrupts = <29>;
564695dd	600	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
5da826ab SG	601	dmas = <&sdma 28 0 0>,
	602	<&sdma 29 0 0>;
	603	dma-names = "rx", "tx";
ffc505c0 SG	604	fsl,fifo-depth = <15>;
	605	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	606	status = "disabled";
	607	};
	608
7b7d6727	609	audmux: audmux@63fd0000 {
ffc505c0 SG	610	compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
	611	reg = <0x63fd0000 0x4000>;
	612	status = "disabled";
	613	};
	614
7b7d6727	615	nfc: nand@63fdb000 {
75453a08 SH	616	compatible = "fsl,imx53-nand";
	617	reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
	618	interrupts = <8>;
564695dd	619	clocks = <&clks IMX5_CLK_NFC_GATE>;
75453a08 SH	620	status = "disabled";
	621	};
	622
ffc505c0 SG	623	ssi3: ssi@63fe8000 {
	624	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	625	reg = <0x63fe8000 0x4000>;
	626	interrupts = <96>;
564695dd	627	clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
5da826ab SG	628	dmas = <&sdma 46 0 0>,
	629	<&sdma 47 0 0>;
	630	dma-names = "rx", "tx";
ffc505c0 SG	631	fsl,fifo-depth = <15>;
	632	fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
	633	status = "disabled";
	634	};
	635
7b7d6727	636	fec: ethernet@63fec000 {
73d2b4cd SG	637	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	638	reg = <0x63fec000 0x4000>;
	639	interrupts = <87>;
564695dd LS	640	clocks = <&clks IMX5_CLK_FEC_GATE>,
	641	<&clks IMX5_CLK_FEC_GATE>,
	642	<&clks IMX5_CLK_FEC_GATE>;
f40f38d1	643	clock-names = "ipg", "ahb", "ptp";
73d2b4cd SG	644	status = "disabled";
73d2b4cd SG	645	};
19194c2b PZ	646
	647	tve: tve@63ff0000 {
	648	compatible = "fsl,imx53-tve";
	649	reg = <0x63ff0000 0x1000>;
	650	interrupts = <92>;
564695dd LS	651	clocks = <&clks IMX5_CLK_TVE_GATE>,
564695dd LS	652	<&clks IMX5_CLK_IPU_DI1_SEL>;
19194c2b PZ	653	clock-names = "tve", "di_sel";
	654	crtcs = <&ipu 1>;
	655	status = "disabled";
	656	};
fbf970f6 FE	657
	658	vpu: vpu@63ff4000 {
	659	compatible = "fsl,imx53-vpu";
	660	reg = <0x63ff4000 0x1000>;
	661	interrupts = <9>;
564695dd LS	662	clocks = <&clks IMX5_CLK_VPU_GATE>,
564695dd LS	663	<&clks IMX5_CLK_VPU_GATE>;
fbf970f6 FE	664	clock-names = "per", "ahb";
	665	iram = <&ocram>;
	666	status = "disabled";
	667	};
73d2b4cd	668	};
481fbe13 PZ	669
	670	ocram: sram@f8000000 {
	671	compatible = "mmio-sram";
	672	reg = <0xf8000000 0x20000>;
564695dd	673	clocks = <&clks IMX5_CLK_OCRAM>;
481fbe13	674	};
73d2b4cd SG	675	};
73d2b4cd SG	676	};