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ARM: dts: i.MX53: Enable CODA7541 VPU
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
CommitLineData
73d2b4cd
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
e1641531 14#include "imx53-pinfunc.h"
564695dd 15#include <dt-bindings/clock/imx5-clock.h>
4e05a7af
DC		 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
73d2b4cd
SG		 18
19/ {
20 aliases {
22970070 21 ethernet0 = &fec;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
c60dc1d1
PZ		 29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
c63d06de
SH		 32 mmc0 = &esdhc1;
33 mmc1 = &esdhc2;
34 mmc2 = &esdhc3;
35 mmc3 = &esdhc4;
cf4e577e
SH		 36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 spi0 = &ecspi1;
42 spi1 = &ecspi2;
43 spi2 = &cspi;
73d2b4cd
SG		 44 };
45
070bd7e4
FE		 46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a8";
52 reg = <0x0>;
53 };
54 };
55
e05c8c9a
PZ		 56 display-subsystem {
57 compatible = "fsl,imx-display-subsystem";
58 ports = <&ipu_di0>, <&ipu_di1>;
59 };
60
73d2b4cd
SG		 61 tzic: tz-interrupt-controller@0fffc000 {
62 compatible = "fsl,imx53-tzic", "fsl,tzic";
63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x0fffc000 0x4000>;
66 };
67
68 clocks {
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 ckil {
73 compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043 74 #clock-cells = <0>;
73d2b4cd
SG		 75 clock-frequency = <32768>;
76 };
77
78 ckih1 {
79 compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043 80 #clock-cells = <0>;
73d2b4cd
SG		 81 clock-frequency = <22579200>;
82 };
83
84 ckih2 {
85 compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043 86 #clock-cells = <0>;
73d2b4cd
SG		 87 clock-frequency = <0>;
88 };
89
90 osc {
91 compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043 92 #clock-cells = <0>;
73d2b4cd
SG		 93 clock-frequency = <24000000>;
94 };
95 };
96
97 soc {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>;
102 ranges;
103
7affee43
MV		 104 sata: sata@10000000 {
105 compatible = "fsl,imx53-ahci";
106 reg = <0x10000000 0x1000>;
107 interrupts = <28>;
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
111 clock-names = "sata_gate", "sata_ref", "ahb";
112 status = "disabled";
113 };
114
abed9a6b 115 ipu: ipu@18000000 {
e05c8c9a
PZ		 116 #address-cells = <1>;
117 #size-cells = <0>;
abed9a6b
SH		 118 compatible = "fsl,imx53-ipu";
119 reg = <0x18000000 0x080000000>;
120 interrupts = <11 10>;
564695dd
LS		 121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
4438a6a1 124 clock-names = "bus", "di0", "di1";
8d84c374 125 resets = <&src 2>;
e05c8c9a
PZ		 126
127 ipu_di0: port@2 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <2>;
131
132 ipu_di0_disp0: endpoint@0 {
133 reg = <0>;
134 };
135
136 ipu_di0_lvds0: endpoint@1 {
137 reg = <1>;
138 remote-endpoint = <&lvds0_in>;
139 };
140 };
141
142 ipu_di1: port@3 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <3>;
146
147 ipu_di1_disp1: endpoint@0 {
148 reg = <0>;
149 };
150
151 ipu_di1_lvds1: endpoint@1 {
152 reg = <1>;
153 remote-endpoint = <&lvds1_in>;
154 };
155
156 ipu_di1_tve: endpoint@2 {
157 reg = <2>;
158 remote-endpoint = <&tve_in>;
159 };
160 };
abed9a6b
SH		 161 };
162
73d2b4cd
SG		 163 aips@50000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 reg = <0x50000000 0x10000000>;
168 ranges;
169
170 spba@50000000 {
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x50000000 0x40000>;
175 ranges;
176
7b7d6727 177 esdhc1: esdhc@50004000 {
73d2b4cd
SG		 178 compatible = "fsl,imx53-esdhc";
179 reg = <0x50004000 0x4000>;
180 interrupts = <1>;
564695dd
LS		 181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
f40f38d1 184 clock-names = "ipg", "ahb", "per";
c104b6a2 185 bus-width = <4>;
73d2b4cd
SG		 186 status = "disabled";
187 };
188
7b7d6727 189 esdhc2: esdhc@50008000 {
73d2b4cd
SG		 190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50008000 0x4000>;
192 interrupts = <2>;
564695dd
LS		 193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
f40f38d1 196 clock-names = "ipg", "ahb", "per";
c104b6a2 197 bus-width = <4>;
73d2b4cd
SG		 198 status = "disabled";
199 };
200
0c456cfa 201 uart3: serial@5000c000 {
73d2b4cd
SG		 202 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
203 reg = <0x5000c000 0x4000>;
204 interrupts = <33>;
564695dd
LS		 205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
f40f38d1 207 clock-names = "ipg", "per";
73d2b4cd
SG		 208 status = "disabled";
209 };
210
7b7d6727 211 ecspi1: ecspi@50010000 {
73d2b4cd
SG		 212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
215 reg = <0x50010000 0x4000>;
216 interrupts = <36>;
564695dd
LS		 217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
f40f38d1 219 clock-names = "ipg", "per";
73d2b4cd
SG		 220 status = "disabled";
221 };
222
ffc505c0 223 ssi2: ssi@50014000 {
28f93d0b
MP		 224 compatible = "fsl,imx53-ssi",
225 "fsl,imx51-ssi",
226 "fsl,imx21-ssi";
ffc505c0
SG		 227 reg = <0x50014000 0x4000>;
228 interrupts = <30>;
564695dd 229 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
5da826ab
SG		 230 dmas = <&sdma 24 1 0>,
231 <&sdma 25 1 0>;
232 dma-names = "rx", "tx";
ffc505c0
SG		 233 fsl,fifo-depth = <15>;
234 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
235 status = "disabled";
236 };
237
7b7d6727 238 esdhc3: esdhc@50020000 {
73d2b4cd
SG		 239 compatible = "fsl,imx53-esdhc";
240 reg = <0x50020000 0x4000>;
241 interrupts = <3>;
564695dd
LS		 242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
f40f38d1 245 clock-names = "ipg", "ahb", "per";
c104b6a2 246 bus-width = <4>;
73d2b4cd
SG		 247 status = "disabled";
248 };
249
7b7d6727 250 esdhc4: esdhc@50024000 {
73d2b4cd
SG		 251 compatible = "fsl,imx53-esdhc";
252 reg = <0x50024000 0x4000>;
253 interrupts = <4>;
564695dd
LS		 254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
f40f38d1 257 clock-names = "ipg", "ahb", "per";
c104b6a2 258 bus-width = <4>;
73d2b4cd
SG		 259 status = "disabled";
260 };
261 };
262
a79025c4
MG		 263 usbphy0: usbphy@0 {
264 compatible = "usb-nop-xceiv";
564695dd 265 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
a79025c4
MG		 266 clock-names = "main_clk";
267 status = "okay";
268 };
269
270 usbphy1: usbphy@1 {
271 compatible = "usb-nop-xceiv";
564695dd 272 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
a79025c4
MG		 273 clock-names = "main_clk";
274 status = "okay";
275 };
276
7b7d6727 277 usbotg: usb@53f80000 {
212d0b83
MG		 278 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
279 reg = <0x53f80000 0x0200>;
280 interrupts = <18>;
564695dd 281 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 282 fsl,usbmisc = <&usbmisc 0>;
a79025c4 283 fsl,usbphy = <&usbphy0>;
212d0b83
MG		 284 status = "disabled";
285 };
286
7b7d6727 287 usbh1: usb@53f80200 {
212d0b83
MG		 288 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
289 reg = <0x53f80200 0x0200>;
290 interrupts = <14>;
564695dd 291 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 292 fsl,usbmisc = <&usbmisc 1>;
a79025c4 293 fsl,usbphy = <&usbphy1>;
212d0b83
MG		 294 status = "disabled";
295 };
296
7b7d6727 297 usbh2: usb@53f80400 {
212d0b83
MG		 298 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
299 reg = <0x53f80400 0x0200>;
300 interrupts = <16>;
564695dd 301 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 302 fsl,usbmisc = <&usbmisc 2>;
212d0b83
MG		 303 status = "disabled";
304 };
305
7b7d6727 306 usbh3: usb@53f80600 {
212d0b83
MG		 307 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
308 reg = <0x53f80600 0x0200>;
309 interrupts = <17>;
564695dd 310 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 311 fsl,usbmisc = <&usbmisc 3>;
212d0b83
MG		 312 status = "disabled";
313 };
314
a5735021
MG		 315 usbmisc: usbmisc@53f80800 {
316 #index-cells = <1>;
317 compatible = "fsl,imx53-usbmisc";
318 reg = <0x53f80800 0x200>;
564695dd 319 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021
MG		 320 };
321
4d191868 322 gpio1: gpio@53f84000 {
aeb27748 323 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 324 reg = <0x53f84000 0x4000>;
325 interrupts = <50 51>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
88cde8b7 329 #interrupt-cells = <2>;
73d2b4cd
SG		 330 };
331
4d191868 332 gpio2: gpio@53f88000 {
aeb27748 333 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 334 reg = <0x53f88000 0x4000>;
335 interrupts = <52 53>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
88cde8b7 339 #interrupt-cells = <2>;
73d2b4cd
SG		 340 };
341
4d191868 342 gpio3: gpio@53f8c000 {
aeb27748 343 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 344 reg = <0x53f8c000 0x4000>;
345 interrupts = <54 55>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
88cde8b7 349 #interrupt-cells = <2>;
73d2b4cd
SG		 350 };
351
4d191868 352 gpio4: gpio@53f90000 {
aeb27748 353 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 354 reg = <0x53f90000 0x4000>;
355 interrupts = <56 57>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-controller;
88cde8b7 359 #interrupt-cells = <2>;
73d2b4cd
SG		 360 };
361
675e4d03
RL		 362 kpp: kpp@53f94000 {
363 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
364 reg = <0x53f94000 0x4000>;
365 interrupts = <60>;
564695dd 366 clocks = <&clks IMX5_CLK_DUMMY>;
675e4d03
RL		 367 status = "disabled";
368 };
369
7b7d6727 370 wdog1: wdog@53f98000 {
73d2b4cd
SG		 371 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
372 reg = <0x53f98000 0x4000>;
373 interrupts = <58>;
564695dd 374 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 375 };
376
7b7d6727 377 wdog2: wdog@53f9c000 {
73d2b4cd
SG		 378 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
379 reg = <0x53f9c000 0x4000>;
380 interrupts = <59>;
564695dd 381 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 382 status = "disabled";
383 };
384
cc8aae9b
SH		 385 gpt: timer@53fa0000 {
386 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
387 reg = <0x53fa0000 0x4000>;
388 interrupts = <39>;
564695dd
LS		 389 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
390 <&clks IMX5_CLK_GPT_HF_GATE>;
cc8aae9b
SH		 391 clock-names = "ipg", "per";
392 };
393
7b7d6727 394 iomuxc: iomuxc@53fa8000 {
5be03a7b
SG		 395 compatible = "fsl,imx53-iomuxc";
396 reg = <0x53fa8000 0x4000>;
5be03a7b
SG		 397 };
398
5af9f143
PZ		 399 gpr: iomuxc-gpr@53fa8000 {
400 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
401 reg = <0x53fa8000 0xc>;
402 };
403
420714aa
PZ		 404 ldb: ldb@53fa8008 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "fsl,imx53-ldb";
408 reg = <0x53fa8008 0x4>;
409 gpr = <&gpr>;
564695dd
LS		 410 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
411 <&clks IMX5_CLK_LDB_DI1_SEL>,
412 <&clks IMX5_CLK_IPU_DI0_SEL>,
413 <&clks IMX5_CLK_IPU_DI1_SEL>,
414 <&clks IMX5_CLK_LDB_DI0_GATE>,
415 <&clks IMX5_CLK_LDB_DI1_GATE>;
420714aa
PZ		 416 clock-names = "di0_pll", "di1_pll",
417 "di0_sel", "di1_sel",
418 "di0", "di1";
419 status = "disabled";
420
421 lvds-channel@0 {
422 reg = <0>;
420714aa 423 status = "disabled";
e05c8c9a
PZ		 424
425 port {
426 lvds0_in: endpoint {
427 remote-endpoint = <&ipu_di0_lvds0>;
428 };
429 };
420714aa
PZ		 430 };
431
432 lvds-channel@1 {
433 reg = <1>;
420714aa 434 status = "disabled";
e05c8c9a
PZ		 435
436 port {
437 lvds1_in: endpoint {
fa1746ae 438 remote-endpoint = <&ipu_di1_lvds1>;
e05c8c9a
PZ		 439 };
440 };
420714aa
PZ		 441 };
442 };
443
9ae90afa
SH		 444 pwm1: pwm@53fb4000 {
445 #pwm-cells = <2>;
446 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
447 reg = <0x53fb4000 0x4000>;
564695dd
LS		 448 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
449 <&clks IMX5_CLK_PWM1_HF_GATE>;
9ae90afa
SH		 450 clock-names = "ipg", "per";
451 interrupts = <61>;
452 };
453
454 pwm2: pwm@53fb8000 {
455 #pwm-cells = <2>;
456 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
457 reg = <0x53fb8000 0x4000>;
564695dd
LS		 458 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
459 <&clks IMX5_CLK_PWM2_HF_GATE>;
9ae90afa
SH		 460 clock-names = "ipg", "per";
461 interrupts = <94>;
462 };
463
0c456cfa 464 uart1: serial@53fbc000 {
73d2b4cd
SG		 465 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
466 reg = <0x53fbc000 0x4000>;
467 interrupts = <31>;
564695dd
LS		 468 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
469 <&clks IMX5_CLK_UART1_PER_GATE>;
f40f38d1 470 clock-names = "ipg", "per";
73d2b4cd
SG		 471 status = "disabled";
472 };
473
0c456cfa 474 uart2: serial@53fc0000 {
73d2b4cd
SG		 475 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
476 reg = <0x53fc0000 0x4000>;
477 interrupts = <32>;
564695dd
LS		 478 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
479 <&clks IMX5_CLK_UART2_PER_GATE>;
f40f38d1 480 clock-names = "ipg", "per";
73d2b4cd
SG		 481 status = "disabled";
482 };
483
a9d1f924
ST		 484 can1: can@53fc8000 {
485 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
486 reg = <0x53fc8000 0x4000>;
487 interrupts = <82>;
564695dd
LS		 488 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
489 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
f40f38d1 490 clock-names = "ipg", "per";
a9d1f924
ST		 491 status = "disabled";
492 };
493
494 can2: can@53fcc000 {
495 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
496 reg = <0x53fcc000 0x4000>;
497 interrupts = <83>;
564695dd
LS		 498 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
499 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
f40f38d1 500 clock-names = "ipg", "per";
a9d1f924
ST		 501 status = "disabled";
502 };
503
8d84c374
PZ		 504 src: src@53fd0000 {
505 compatible = "fsl,imx53-src", "fsl,imx51-src";
506 reg = <0x53fd0000 0x4000>;
507 #reset-cells = <1>;
508 };
509
f40f38d1
FE		 510 clks: ccm@53fd4000{
511 compatible = "fsl,imx53-ccm";
512 reg = <0x53fd4000 0x4000>;
513 interrupts = <0 71 0x04 0 72 0x04>;
514 #clock-cells = <1>;
515 };
516
4d191868 517 gpio5: gpio@53fdc000 {
aeb27748 518 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 519 reg = <0x53fdc000 0x4000>;
520 interrupts = <103 104>;
521 gpio-controller;
522 #gpio-cells = <2>;
523 interrupt-controller;
88cde8b7 524 #interrupt-cells = <2>;
73d2b4cd
SG		 525 };
526
4d191868 527 gpio6: gpio@53fe0000 {
aeb27748 528 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 529 reg = <0x53fe0000 0x4000>;
530 interrupts = <105 106>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 interrupt-controller;
88cde8b7 534 #interrupt-cells = <2>;
73d2b4cd
SG		 535 };
536
4d191868 537 gpio7: gpio@53fe4000 {
aeb27748 538 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 539 reg = <0x53fe4000 0x4000>;
540 interrupts = <107 108>;
541 gpio-controller;
542 #gpio-cells = <2>;
543 interrupt-controller;
88cde8b7 544 #interrupt-cells = <2>;
73d2b4cd
SG		 545 };
546
7b7d6727 547 i2c3: i2c@53fec000 {
73d2b4cd
SG		 548 #address-cells = <1>;
549 #size-cells = <0>;
5bdfba29 550 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 551 reg = <0x53fec000 0x4000>;
552 interrupts = <64>;
564695dd 553 clocks = <&clks IMX5_CLK_I2C3_GATE>;
73d2b4cd
SG		 554 status = "disabled";
555 };
556
0c456cfa 557 uart4: serial@53ff0000 {
73d2b4cd
SG		 558 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
559 reg = <0x53ff0000 0x4000>;
560 interrupts = <13>;
564695dd
LS		 561 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
562 <&clks IMX5_CLK_UART4_PER_GATE>;
f40f38d1 563 clock-names = "ipg", "per";
73d2b4cd
SG		 564 status = "disabled";
565 };
566 };
567
568 aips@60000000 { /* AIPS2 */
569 compatible = "fsl,aips-bus", "simple-bus";
570 #address-cells = <1>;
571 #size-cells = <1>;
572 reg = <0x60000000 0x10000000>;
573 ranges;
574
4f3b2a41
SH		 575 iim: iim@63f98000 {
576 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
577 reg = <0x63f98000 0x4000>;
578 interrupts = <69>;
564695dd 579 clocks = <&clks IMX5_CLK_IIM_GATE>;
4f3b2a41
SH		 580 };
581
0c456cfa 582 uart5: serial@63f90000 {
73d2b4cd
SG		 583 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
584 reg = <0x63f90000 0x4000>;
585 interrupts = <86>;
564695dd
LS		 586 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
587 <&clks IMX5_CLK_UART5_PER_GATE>;
f40f38d1 588 clock-names = "ipg", "per";
73d2b4cd
SG		 589 status = "disabled";
590 };
591
a82b7b9c
MF		 592 owire: owire@63fa4000 {
593 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
594 reg = <0x63fa4000 0x4000>;
564695dd 595 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
a82b7b9c
MF		 596 status = "disabled";
597 };
598
7b7d6727 599 ecspi2: ecspi@63fac000 {
73d2b4cd
SG		 600 #address-cells = <1>;
601 #size-cells = <0>;
602 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
603 reg = <0x63fac000 0x4000>;
604 interrupts = <37>;
564695dd
LS		 605 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
606 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
f40f38d1 607 clock-names = "ipg", "per";
73d2b4cd
SG		 608 status = "disabled";
609 };
610
7b7d6727 611 sdma: sdma@63fb0000 {
73d2b4cd
SG		 612 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
613 reg = <0x63fb0000 0x4000>;
614 interrupts = <6>;
564695dd
LS		 615 clocks = <&clks IMX5_CLK_SDMA_GATE>,
616 <&clks IMX5_CLK_SDMA_GATE>;
f40f38d1 617 clock-names = "ipg", "ahb";
fb72bb21 618 #dma-cells = <3>;
7e4f0365 619 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd
SG		 620 };
621
7b7d6727 622 cspi: cspi@63fc0000 {
73d2b4cd
SG		 623 #address-cells = <1>;
624 #size-cells = <0>;
625 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
626 reg = <0x63fc0000 0x4000>;
627 interrupts = <38>;
564695dd
LS		 628 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
629 <&clks IMX5_CLK_CSPI_IPG_GATE>;
f40f38d1 630 clock-names = "ipg", "per";
73d2b4cd
SG		 631 status = "disabled";
632 };
633
7b7d6727 634 i2c2: i2c@63fc4000 {
73d2b4cd
SG		 635 #address-cells = <1>;
636 #size-cells = <0>;
5bdfba29 637 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 638 reg = <0x63fc4000 0x4000>;
639 interrupts = <63>;
564695dd 640 clocks = <&clks IMX5_CLK_I2C2_GATE>;
73d2b4cd
SG		 641 status = "disabled";
642 };
643
7b7d6727 644 i2c1: i2c@63fc8000 {
73d2b4cd
SG		 645 #address-cells = <1>;
646 #size-cells = <0>;
5bdfba29 647 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 648 reg = <0x63fc8000 0x4000>;
649 interrupts = <62>;
564695dd 650 clocks = <&clks IMX5_CLK_I2C1_GATE>;
73d2b4cd
SG		 651 status = "disabled";
652 };
653
ffc505c0 654 ssi1: ssi@63fcc000 {
28f93d0b
MP		 655 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
656 "fsl,imx21-ssi";
ffc505c0
SG		 657 reg = <0x63fcc000 0x4000>;
658 interrupts = <29>;
564695dd 659 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
5da826ab
SG		 660 dmas = <&sdma 28 0 0>,
661 <&sdma 29 0 0>;
662 dma-names = "rx", "tx";
ffc505c0
SG		 663 fsl,fifo-depth = <15>;
664 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
665 status = "disabled";
666 };
667
7b7d6727 668 audmux: audmux@63fd0000 {
ffc505c0
SG		 669 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
670 reg = <0x63fd0000 0x4000>;
671 status = "disabled";
672 };
673
7b7d6727 674 nfc: nand@63fdb000 {
75453a08
SH		 675 compatible = "fsl,imx53-nand";
676 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
677 interrupts = <8>;
564695dd 678 clocks = <&clks IMX5_CLK_NFC_GATE>;
75453a08
SH		 679 status = "disabled";
680 };
681
ffc505c0 682 ssi3: ssi@63fe8000 {
28f93d0b
MP		 683 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
684 "fsl,imx21-ssi";
ffc505c0
SG		 685 reg = <0x63fe8000 0x4000>;
686 interrupts = <96>;
564695dd 687 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
5da826ab
SG		 688 dmas = <&sdma 46 0 0>,
689 <&sdma 47 0 0>;
690 dma-names = "rx", "tx";
ffc505c0
SG		 691 fsl,fifo-depth = <15>;
692 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
693 status = "disabled";
694 };
695
7b7d6727 696 fec: ethernet@63fec000 {
73d2b4cd
SG		 697 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
698 reg = <0x63fec000 0x4000>;
699 interrupts = <87>;
564695dd
LS		 700 clocks = <&clks IMX5_CLK_FEC_GATE>,
701 <&clks IMX5_CLK_FEC_GATE>,
702 <&clks IMX5_CLK_FEC_GATE>;
f40f38d1 703 clock-names = "ipg", "ahb", "ptp";
73d2b4cd
SG		 704 status = "disabled";
705 };
19194c2b
PZ		 706
707 tve: tve@63ff0000 {
708 compatible = "fsl,imx53-tve";
709 reg = <0x63ff0000 0x1000>;
710 interrupts = <92>;
564695dd
LS		 711 clocks = <&clks IMX5_CLK_TVE_GATE>,
712 <&clks IMX5_CLK_IPU_DI1_SEL>;
19194c2b 713 clock-names = "tve", "di_sel";
19194c2b 714 status = "disabled";
e05c8c9a
PZ		 715
716 port {
717 tve_in: endpoint {
718 remote-endpoint = <&ipu_di1_tve>;
719 };
720 };
19194c2b 721 };
fbf970f6
FE		 722
723 vpu: vpu@63ff4000 {
724 compatible = "fsl,imx53-vpu";
725 reg = <0x63ff4000 0x1000>;
726 interrupts = <9>;
564695dd
LS		 727 clocks = <&clks IMX5_CLK_VPU_GATE>,
728 <&clks IMX5_CLK_VPU_GATE>;
fbf970f6
FE		 729 clock-names = "per", "ahb";
730 iram = <&ocram>;
fbf970f6 731 };
73d2b4cd 732 };
481fbe13
PZ		 733
734 ocram: sram@f8000000 {
735 compatible = "mmio-sram";
736 reg = <0xf8000000 0x20000>;
564695dd 737 clocks = <&clks IMX5_CLK_OCRAM>;
481fbe13 738 };
73d2b4cd
SG		 739 };
740};
Linux kernel - Deliverables
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