projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9a8d6d55 | 1 | |
| 7c1da585 SG |
2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | */ | |
| 10 | ||
| 9a8d6d55 | 11 | #include "imx6dl-pinfunc.h" |
| c56009b2 | 12 | #include "imx6qdl.dtsi" |
| 7c1da585 SG |
13 | |
| 14 | / { | |
| 15 | cpus { | |
| 16 | #address-cells = <1>; | |
| 17 | #size-cells = <0>; | |
| 18 | ||
| 19 | cpu@0 { | |
| 20 | compatible = "arm,cortex-a9"; | |
| 7925e89f | 21 | device_type = "cpu"; |
| 7c1da585 SG |
22 | reg = <0>; |
| 23 | next-level-cache = <&L2>; | |
| 24 | }; | |
| 25 | ||
| 26 | cpu@1 { | |
| 27 | compatible = "arm,cortex-a9"; | |
| 7925e89f | 28 | device_type = "cpu"; |
| 7c1da585 SG |
29 | reg = <1>; |
| 30 | next-level-cache = <&L2>; | |
| 31 | }; | |
| 32 | }; | |
| 33 | ||
| 34 | soc { | |
| 35 | aips1: aips-bus@02000000 { | |
| 9a8d6d55 SG |
36 | iomuxc: iomuxc@020e0000 { |
| 37 | compatible = "fsl,imx6dl-iomuxc"; | |
| 9a8d6d55 SG |
38 | }; |
| 39 | ||
| 7c1da585 SG |
40 | pxp: pxp@020f0000 { |
| 41 | reg = <0x020f0000 0x4000>; | |
| 42 | interrupts = <0 98 0x04>; | |
| 43 | }; | |
| 44 | ||
| 45 | epdc: epdc@020f4000 { | |
| 46 | reg = <0x020f4000 0x4000>; | |
| 47 | interrupts = <0 97 0x04>; | |
| 48 | }; | |
| 49 | ||
| 50 | lcdif: lcdif@020f8000 { | |
| 51 | reg = <0x020f8000 0x4000>; | |
| 52 | interrupts = <0 39 0x04>; | |
| 53 | }; | |
| 54 | }; | |
| 55 | ||
| 56 | aips2: aips-bus@02100000 { | |
| 57 | i2c4: i2c@021f8000 { | |
| 58 | #address-cells = <1>; | |
| 59 | #size-cells = <0>; | |
| 60 | compatible = "fsl,imx1-i2c"; | |
| 61 | reg = <0x021f8000 0x4000>; | |
| 62 | interrupts = <0 35 0x04>; | |
| 63 | status = "disabled"; | |
| 64 | }; | |
| 65 | }; | |
| 66 | }; | |
| 67 | }; | |
| 964c847a PZ |
68 | |
| 69 | &ldb { | |
| 70 | clocks = <&clks 33>, <&clks 34>, | |
| 71 | <&clks 39>, <&clks 40>, | |
| 72 | <&clks 135>, <&clks 136>; | |
| 73 | clock-names = "di0_pll", "di1_pll", | |
| 74 | "di0_sel", "di1_sel", | |
| 75 | "di0", "di1"; | |
| 76 | ||
| 77 | lvds-channel@0 { | |
| 78 | crtcs = <&ipu1 0>, <&ipu1 1>; | |
| 79 | }; | |
| 80 | ||
| 81 | lvds-channel@1 { | |
| 82 | crtcs = <&ipu1 0>, <&ipu1 1>; | |
| 83 | }; | |
| 84 | }; |