projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9a8d6d55 | 1 | |
| 7c1da585 SG |
2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | */ | |
| 10 | ||
| f89f5b46 | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 9a8d6d55 | 12 | #include "imx6dl-pinfunc.h" |
| c56009b2 | 13 | #include "imx6qdl.dtsi" |
| 7c1da585 SG |
14 | |
| 15 | / { | |
| 16 | cpus { | |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| 19 | ||
| 20 | cpu@0 { | |
| 21 | compatible = "arm,cortex-a9"; | |
| 7925e89f | 22 | device_type = "cpu"; |
| 7c1da585 SG |
23 | reg = <0>; |
| 24 | next-level-cache = <&L2>; | |
| 978ed904 AH |
25 | operating-points = < |
| 26 | /* kHz uV */ | |
| 27 | 996000 1275000 | |
| 28 | 792000 1175000 | |
| 29 | 396000 1075000 | |
| 30 | >; | |
| 31 | fsl,soc-operating-points = < | |
| 32 | /* ARM kHz SOC-PU uV */ | |
| 33 | 996000 1175000 | |
| 34 | 792000 1175000 | |
| 35 | 396000 1175000 | |
| 36 | >; | |
| 37 | clock-latency = <61036>; /* two CLK32 periods */ | |
| 38 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, | |
| 39 | <&clks 17>, <&clks 170>; | |
| 40 | clock-names = "arm", "pll2_pfd2_396m", "step", | |
| 41 | "pll1_sw", "pll1_sys"; | |
| 42 | arm-supply = <®_arm>; | |
| 43 | pu-supply = <®_pu>; | |
| 44 | soc-supply = <®_soc>; | |
| 7c1da585 SG |
45 | }; |
| 46 | ||
| 47 | cpu@1 { | |
| 48 | compatible = "arm,cortex-a9"; | |
| 7925e89f | 49 | device_type = "cpu"; |
| 7c1da585 SG |
50 | reg = <1>; |
| 51 | next-level-cache = <&L2>; | |
| 52 | }; | |
| 53 | }; | |
| 54 | ||
| 55 | soc { | |
| 951ebf58 SG |
56 | ocram: sram@00900000 { |
| 57 | compatible = "mmio-sram"; | |
| 58 | reg = <0x00900000 0x20000>; | |
| 59 | clocks = <&clks 142>; | |
| 60 | }; | |
| 61 | ||
| 7c1da585 | 62 | aips1: aips-bus@02000000 { |
| 9a8d6d55 SG |
63 | iomuxc: iomuxc@020e0000 { |
| 64 | compatible = "fsl,imx6dl-iomuxc"; | |
| 9a8d6d55 SG |
65 | }; |
| 66 | ||
| 7c1da585 SG |
67 | pxp: pxp@020f0000 { |
| 68 | reg = <0x020f0000 0x4000>; | |
| f89f5b46 | 69 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| 7c1da585 SG |
70 | }; |
| 71 | ||
| 72 | epdc: epdc@020f4000 { | |
| 73 | reg = <0x020f4000 0x4000>; | |
| f89f5b46 | 74 | interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| 7c1da585 SG |
75 | }; |
| 76 | ||
| 77 | lcdif: lcdif@020f8000 { | |
| 78 | reg = <0x020f8000 0x4000>; | |
| f89f5b46 | 79 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| 7c1da585 SG |
80 | }; |
| 81 | }; | |
| 82 | ||
| 83 | aips2: aips-bus@02100000 { | |
| 84 | i2c4: i2c@021f8000 { | |
| 85 | #address-cells = <1>; | |
| 86 | #size-cells = <0>; | |
| 87 | compatible = "fsl,imx1-i2c"; | |
| 88 | reg = <0x021f8000 0x4000>; | |
| f89f5b46 | 89 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| 7c1da585 SG |
90 | status = "disabled"; |
| 91 | }; | |
| 92 | }; | |
| 93 | }; | |
| 4520e692 PZ |
94 | |
| 95 | display-subsystem { | |
| 96 | compatible = "fsl,imx-display-subsystem"; | |
| 97 | ports = <&ipu1_di0>, <&ipu1_di1>; | |
| 98 | }; | |
| 99 | }; | |
| 100 | ||
| 101 | &hdmi { | |
| 102 | compatible = "fsl,imx6dl-hdmi"; | |
| 7c1da585 | 103 | }; |
| 964c847a PZ |
104 | |
| 105 | &ldb { | |
| 106 | clocks = <&clks 33>, <&clks 34>, | |
| 107 | <&clks 39>, <&clks 40>, | |
| 108 | <&clks 135>, <&clks 136>; | |
| 109 | clock-names = "di0_pll", "di1_pll", | |
| 110 | "di0_sel", "di1_sel", | |
| 111 | "di0", "di1"; | |
| cf83eb24 | 112 | }; |