projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9a8d6d55 | 1 | |
| 7c1da585 SG |
2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | */ | |
| 10 | ||
| 36dffd8f | 11 | #include "imx6qdl.dtsi" |
| 9a8d6d55 | 12 | #include "imx6dl-pinfunc.h" |
| 7c1da585 SG |
13 | |
| 14 | / { | |
| 15 | cpus { | |
| 16 | #address-cells = <1>; | |
| 17 | #size-cells = <0>; | |
| 18 | ||
| 19 | cpu@0 { | |
| 20 | compatible = "arm,cortex-a9"; | |
| 21 | reg = <0>; | |
| 22 | next-level-cache = <&L2>; | |
| 23 | }; | |
| 24 | ||
| 25 | cpu@1 { | |
| 26 | compatible = "arm,cortex-a9"; | |
| 27 | reg = <1>; | |
| 28 | next-level-cache = <&L2>; | |
| 29 | }; | |
| 30 | }; | |
| 31 | ||
| 32 | soc { | |
| 33 | aips1: aips-bus@02000000 { | |
| 9a8d6d55 SG |
34 | iomuxc: iomuxc@020e0000 { |
| 35 | compatible = "fsl,imx6dl-iomuxc"; | |
| 36 | reg = <0x020e0000 0x4000>; | |
| 37 | ||
| 32d77d11 HS |
38 | ecspi1 { |
| 39 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
| 40 | fsl,pins = < | |
| 41 | MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | |
| 42 | MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | |
| 43 | MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | |
| 44 | >; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 9a8d6d55 SG |
48 | enet { |
| 49 | pinctrl_enet_1: enetgrp-1 { | |
| 50 | fsl,pins = < | |
| 51 | MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
| 52 | MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
| 53 | MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
| 54 | MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
| 55 | MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
| 56 | MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
| 57 | MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
| 58 | MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
| 59 | MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
| 60 | MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
| 61 | MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
| 62 | MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
| 63 | MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
| 64 | MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
| 65 | MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
| 66 | MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | |
| 67 | >; | |
| 68 | }; | |
| 1aa8b3e0 SG |
69 | |
| 70 | pinctrl_enet_2: enetgrp-2 { | |
| 71 | fsl,pins = < | |
| 72 | MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | |
| 73 | MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | |
| 74 | MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
| 75 | MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
| 76 | MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
| 77 | MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
| 78 | MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
| 79 | MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
| 80 | MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
| 81 | MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
| 82 | MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
| 83 | MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
| 84 | MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
| 85 | MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
| 86 | MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
| 87 | >; | |
| 88 | }; | |
| 9a8d6d55 SG |
89 | }; |
| 90 | ||
| db37242c HS |
91 | gpmi-nand { |
| 92 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | |
| 93 | fsl,pins = < | |
| 94 | MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | |
| 95 | MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | |
| 96 | MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | |
| 97 | MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | |
| 98 | MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | |
| 99 | MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | |
| 100 | MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | |
| 101 | MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | |
| 102 | MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | |
| 103 | MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | |
| 104 | MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | |
| 105 | MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | |
| 106 | MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | |
| 107 | MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | |
| 108 | MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | |
| 109 | MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | |
| 110 | MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | |
| 111 | >; | |
| 112 | }; | |
| 113 | }; | |
| 114 | ||
| ee531435 NC |
115 | i2c1 { |
| 116 | pinctrl_i2c1_2: i2c1grp-2 { | |
| 117 | fsl,pins = < | |
| 118 | MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | |
| 119 | MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | |
| 120 | >; | |
| 121 | }; | |
| 122 | }; | |
| 123 | ||
| 9a8d6d55 SG |
124 | uart1 { |
| 125 | pinctrl_uart1_1: uart1grp-1 { | |
| 126 | fsl,pins = < | |
| 127 | MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | |
| 128 | MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | |
| 129 | >; | |
| 130 | }; | |
| 131 | }; | |
| 132 | ||
| 1aa8b3e0 SG |
133 | uart4 { |
| 134 | pinctrl_uart4_1: uart4grp-1 { | |
| 135 | fsl,pins = < | |
| 136 | MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | |
| 137 | MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | |
| 138 | >; | |
| 139 | }; | |
| 140 | }; | |
| 141 | ||
| 9a8d6d55 SG |
142 | usbotg { |
| 143 | pinctrl_usbotg_2: usbotggrp-2 { | |
| 144 | fsl,pins = < | |
| 145 | MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | |
| 146 | >; | |
| 147 | }; | |
| 148 | }; | |
| 149 | ||
| 150 | usdhc2 { | |
| 151 | pinctrl_usdhc2_1: usdhc2grp-1 { | |
| 152 | fsl,pins = < | |
| 153 | MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
| 154 | MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059 | |
| 155 | MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
| 156 | MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
| 157 | MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
| 158 | MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
| 159 | MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059 | |
| 160 | MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059 | |
| 161 | MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059 | |
| 162 | MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 | |
| 163 | >; | |
| 164 | }; | |
| 165 | }; | |
| 166 | ||
| 167 | usdhc3 { | |
| 168 | pinctrl_usdhc3_1: usdhc3grp-1 { | |
| 169 | fsl,pins = < | |
| 170 | MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
| 171 | MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
| 172 | MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
| 173 | MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
| 174 | MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
| 175 | MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
| 176 | MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | |
| 177 | MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | |
| 178 | MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | |
| 179 | MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | |
| 180 | >; | |
| 181 | }; | |
| 89b82915 FE |
182 | |
| 183 | pinctrl_usdhc3_2: usdhc3grp_2 { | |
| 184 | fsl,pins = < | |
| 185 | MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
| 186 | MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
| 187 | MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
| 188 | MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
| 189 | MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
| 190 | MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
| 191 | >; | |
| 192 | }; | |
| 9a8d6d55 SG |
193 | }; |
| 194 | ||
| 9feded1e HS |
195 | weim { |
| 196 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | |
| 197 | fsl,pins = < | |
| 198 | MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | |
| 199 | >; | |
| 200 | }; | |
| 201 | ||
| 202 | pinctrl_weim_nor_1: weim_norgrp-1 { | |
| 203 | fsl,pins = < | |
| 204 | MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | |
| 205 | MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 | |
| 206 | MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | |
| 207 | /* data */ | |
| 208 | MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | |
| 209 | MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | |
| 210 | MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | |
| 211 | MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | |
| 212 | MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | |
| 213 | MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | |
| 214 | MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | |
| 215 | MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | |
| 216 | MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | |
| 217 | MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | |
| 218 | MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | |
| 219 | MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | |
| 220 | MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | |
| 221 | MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | |
| 222 | MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | |
| 223 | MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | |
| 224 | /* address */ | |
| 225 | MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | |
| 226 | MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | |
| 227 | MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | |
| 228 | MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | |
| 229 | MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | |
| 230 | MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | |
| 231 | MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | |
| 232 | MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | |
| 233 | MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | |
| 234 | MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | |
| 235 | MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | |
| 236 | MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | |
| 237 | MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | |
| 238 | MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | |
| 239 | MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | |
| 240 | MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | |
| 241 | MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | |
| 242 | MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | |
| 243 | MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | |
| 244 | MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | |
| 245 | MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | |
| 246 | MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | |
| 247 | MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | |
| 248 | MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | |
| 249 | >; | |
| 250 | }; | |
| 251 | ||
| 252 | }; | |
| 9a8d6d55 SG |
253 | |
| 254 | }; | |
| 255 | ||
| 7c1da585 SG |
256 | pxp: pxp@020f0000 { |
| 257 | reg = <0x020f0000 0x4000>; | |
| 258 | interrupts = <0 98 0x04>; | |
| 259 | }; | |
| 260 | ||
| 261 | epdc: epdc@020f4000 { | |
| 262 | reg = <0x020f4000 0x4000>; | |
| 263 | interrupts = <0 97 0x04>; | |
| 264 | }; | |
| 265 | ||
| 266 | lcdif: lcdif@020f8000 { | |
| 267 | reg = <0x020f8000 0x4000>; | |
| 268 | interrupts = <0 39 0x04>; | |
| 269 | }; | |
| 270 | }; | |
| 271 | ||
| 272 | aips2: aips-bus@02100000 { | |
| 273 | i2c4: i2c@021f8000 { | |
| 274 | #address-cells = <1>; | |
| 275 | #size-cells = <0>; | |
| 276 | compatible = "fsl,imx1-i2c"; | |
| 277 | reg = <0x021f8000 0x4000>; | |
| 278 | interrupts = <0 35 0x04>; | |
| 279 | status = "disabled"; | |
| 280 | }; | |
| 281 | }; | |
| 282 | }; | |
| 283 | }; |