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ARM: dts: imx: Always enable the watchdog
[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
8f9ffecf
RZ		 17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
7d740f87
SG		 29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a9";
49 reg = <2>;
50 next-level-cache = <&L2>;
51 };
52
53 cpu@3 {
54 compatible = "arm,cortex-a9";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 interrupt-controller;
66 reg = <0x00a01000 0x1000>,
67 <0x00a00100 0x100>;
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 ckil {
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
77 };
78
79 ckih1 {
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
95 ranges;
96
e5d0f9f5
HS		 97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
100 };
101
cf922fa8
HS		 102 gpmi-nand@00112000 {
103 compatible = "fsl,imx6q-gpmi-nand";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
107 reg-names = "gpmi-nand", "bch";
108 interrupts = <0 13 0x04>, <0 15 0x04>;
109 interrupt-names = "gpmi-dma", "bch";
110 fsl,gpmi-dma-channel = <0>;
111 status = "disabled";
112 };
113
7d740f87 114 timer@00a00600 {
58458e03
MZ		 115 compatible = "arm,cortex-a9-twd-timer";
116 reg = <0x00a00600 0x20>;
117 interrupts = <1 13 0xf01>;
7d740f87
SG		 118 };
119
120 L2: l2-cache@00a02000 {
121 compatible = "arm,pl310-cache";
122 reg = <0x00a02000 0x1000>;
123 interrupts = <0 92 0x04>;
124 cache-unified;
125 cache-level = <2>;
126 };
127
128 aips-bus@02000000 { /* AIPS1 */
129 compatible = "fsl,aips-bus", "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0x02000000 0x100000>;
133 ranges;
134
135 spba-bus@02000000 {
136 compatible = "fsl,spba-bus", "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 reg = <0x02000000 0x40000>;
140 ranges;
141
142 spdif@02004000 {
143 reg = <0x02004000 0x4000>;
144 interrupts = <0 52 0x04>;
145 };
146
147 ecspi@02008000 { /* eCSPI1 */
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
151 reg = <0x02008000 0x4000>;
152 interrupts = <0 31 0x04>;
153 status = "disabled";
154 };
155
156 ecspi@0200c000 { /* eCSPI2 */
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
160 reg = <0x0200c000 0x4000>;
161 interrupts = <0 32 0x04>;
162 status = "disabled";
163 };
164
165 ecspi@02010000 { /* eCSPI3 */
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 0x04>;
171 status = "disabled";
172 };
173
174 ecspi@02014000 { /* eCSPI4 */
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02014000 0x4000>;
179 interrupts = <0 34 0x04>;
180 status = "disabled";
181 };
182
183 ecspi@02018000 { /* eCSPI5 */
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
187 reg = <0x02018000 0x4000>;
188 interrupts = <0 35 0x04>;
189 status = "disabled";
190 };
191
0c456cfa 192 uart1: serial@02020000 {
7d740f87
SG		 193 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
194 reg = <0x02020000 0x4000>;
195 interrupts = <0 26 0x04>;
196 status = "disabled";
197 };
198
199 esai@02024000 {
200 reg = <0x02024000 0x4000>;
201 interrupts = <0 51 0x04>;
202 };
203
b1a5da8e
RZ		 204 ssi1: ssi@02028000 {
205 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 206 reg = <0x02028000 0x4000>;
207 interrupts = <0 46 0x04>;
b1a5da8e
RZ		 208 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <38 37>;
210 status = "disabled";
7d740f87
SG		 211 };
212
b1a5da8e
RZ		 213 ssi2: ssi@0202c000 {
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 215 reg = <0x0202c000 0x4000>;
216 interrupts = <0 47 0x04>;
b1a5da8e
RZ		 217 fsl,fifo-depth = <15>;
218 fsl,ssi-dma-events = <42 41>;
219 status = "disabled";
7d740f87
SG		 220 };
221
b1a5da8e
RZ		 222 ssi3: ssi@02030000 {
223 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 224 reg = <0x02030000 0x4000>;
225 interrupts = <0 48 0x04>;
b1a5da8e
RZ		 226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <46 45>;
228 status = "disabled";
7d740f87
SG		 229 };
230
231 asrc@02034000 {
232 reg = <0x02034000 0x4000>;
233 interrupts = <0 50 0x04>;
234 };
235
236 spba@0203c000 {
237 reg = <0x0203c000 0x4000>;
238 };
239 };
240
241 vpu@02040000 {
242 reg = <0x02040000 0x3c000>;
243 interrupts = <0 3 0x04 0 12 0x04>;
244 };
245
246 aipstz@0207c000 { /* AIPSTZ1 */
247 reg = <0x0207c000 0x4000>;
248 };
249
250 pwm@02080000 { /* PWM1 */
251 reg = <0x02080000 0x4000>;
252 interrupts = <0 83 0x04>;
253 };
254
255 pwm@02084000 { /* PWM2 */
256 reg = <0x02084000 0x4000>;
257 interrupts = <0 84 0x04>;
258 };
259
260 pwm@02088000 { /* PWM3 */
261 reg = <0x02088000 0x4000>;
262 interrupts = <0 85 0x04>;
263 };
264
265 pwm@0208c000 { /* PWM4 */
266 reg = <0x0208c000 0x4000>;
267 interrupts = <0 86 0x04>;
268 };
269
270 flexcan@02090000 { /* CAN1 */
271 reg = <0x02090000 0x4000>;
272 interrupts = <0 110 0x04>;
273 };
274
275 flexcan@02094000 { /* CAN2 */
276 reg = <0x02094000 0x4000>;
277 interrupts = <0 111 0x04>;
278 };
279
280 gpt@02098000 {
281 compatible = "fsl,imx6q-gpt";
282 reg = <0x02098000 0x4000>;
283 interrupts = <0 55 0x04>;
284 };
285
4d191868 286 gpio1: gpio@0209c000 {
aeb27748 287 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 288 reg = <0x0209c000 0x4000>;
289 interrupts = <0 66 0x04 0 67 0x04>;
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
88cde8b7 293 #interrupt-cells = <2>;
7d740f87
SG		 294 };
295
4d191868 296 gpio2: gpio@020a0000 {
aeb27748 297 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 298 reg = <0x020a0000 0x4000>;
299 interrupts = <0 68 0x04 0 69 0x04>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
88cde8b7 303 #interrupt-cells = <2>;
7d740f87
SG		 304 };
305
4d191868 306 gpio3: gpio@020a4000 {
aeb27748 307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 308 reg = <0x020a4000 0x4000>;
309 interrupts = <0 70 0x04 0 71 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
88cde8b7 313 #interrupt-cells = <2>;
7d740f87
SG		 314 };
315
4d191868 316 gpio4: gpio@020a8000 {
aeb27748 317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 318 reg = <0x020a8000 0x4000>;
319 interrupts = <0 72 0x04 0 73 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
88cde8b7 323 #interrupt-cells = <2>;
7d740f87
SG		 324 };
325
4d191868 326 gpio5: gpio@020ac000 {
aeb27748 327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 328 reg = <0x020ac000 0x4000>;
329 interrupts = <0 74 0x04 0 75 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
88cde8b7 333 #interrupt-cells = <2>;
7d740f87
SG		 334 };
335
4d191868 336 gpio6: gpio@020b0000 {
aeb27748 337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 338 reg = <0x020b0000 0x4000>;
339 interrupts = <0 76 0x04 0 77 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
88cde8b7 343 #interrupt-cells = <2>;
7d740f87
SG		 344 };
345
4d191868 346 gpio7: gpio@020b4000 {
aeb27748 347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 348 reg = <0x020b4000 0x4000>;
349 interrupts = <0 78 0x04 0 79 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
88cde8b7 353 #interrupt-cells = <2>;
7d740f87
SG		 354 };
355
356 kpp@020b8000 {
357 reg = <0x020b8000 0x4000>;
358 interrupts = <0 82 0x04>;
359 };
360
361 wdog@020bc000 { /* WDOG1 */
362 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
363 reg = <0x020bc000 0x4000>;
364 interrupts = <0 80 0x04>;
7d740f87
SG		 365 };
366
367 wdog@020c0000 { /* WDOG2 */
368 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
369 reg = <0x020c0000 0x4000>;
370 interrupts = <0 81 0x04>;
371 status = "disabled";
372 };
373
374 ccm@020c4000 {
375 compatible = "fsl,imx6q-ccm";
376 reg = <0x020c4000 0x4000>;
377 interrupts = <0 87 0x04 0 88 0x04>;
378 };
379
380 anatop@020c8000 {
381 compatible = "fsl,imx6q-anatop";
382 reg = <0x020c8000 0x1000>;
383 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
a1e327e6
YCLP		 384
385 regulator-1p1@110 {
386 compatible = "fsl,anatop-regulator";
387 regulator-name = "vdd1p1";
388 regulator-min-microvolt = <800000>;
389 regulator-max-microvolt = <1375000>;
390 regulator-always-on;
391 anatop-reg-offset = <0x110>;
392 anatop-vol-bit-shift = <8>;
393 anatop-vol-bit-width = <5>;
394 anatop-min-bit-val = <4>;
395 anatop-min-voltage = <800000>;
396 anatop-max-voltage = <1375000>;
397 };
398
399 regulator-3p0@120 {
400 compatible = "fsl,anatop-regulator";
401 regulator-name = "vdd3p0";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <3150000>;
404 regulator-always-on;
405 anatop-reg-offset = <0x120>;
406 anatop-vol-bit-shift = <8>;
407 anatop-vol-bit-width = <5>;
408 anatop-min-bit-val = <0>;
409 anatop-min-voltage = <2625000>;
410 anatop-max-voltage = <3400000>;
411 };
412
413 regulator-2p5@130 {
414 compatible = "fsl,anatop-regulator";
415 regulator-name = "vdd2p5";
416 regulator-min-microvolt = <2000000>;
417 regulator-max-microvolt = <2750000>;
418 regulator-always-on;
419 anatop-reg-offset = <0x130>;
420 anatop-vol-bit-shift = <8>;
421 anatop-vol-bit-width = <5>;
422 anatop-min-bit-val = <0>;
423 anatop-min-voltage = <2000000>;
424 anatop-max-voltage = <2750000>;
425 };
426
427 regulator-vddcore@140 {
428 compatible = "fsl,anatop-regulator";
429 regulator-name = "cpu";
430 regulator-min-microvolt = <725000>;
431 regulator-max-microvolt = <1450000>;
432 regulator-always-on;
433 anatop-reg-offset = <0x140>;
434 anatop-vol-bit-shift = <0>;
435 anatop-vol-bit-width = <5>;
436 anatop-min-bit-val = <1>;
437 anatop-min-voltage = <725000>;
438 anatop-max-voltage = <1450000>;
439 };
440
441 regulator-vddpu@140 {
442 compatible = "fsl,anatop-regulator";
443 regulator-name = "vddpu";
444 regulator-min-microvolt = <725000>;
445 regulator-max-microvolt = <1450000>;
446 regulator-always-on;
447 anatop-reg-offset = <0x140>;
448 anatop-vol-bit-shift = <9>;
449 anatop-vol-bit-width = <5>;
450 anatop-min-bit-val = <1>;
451 anatop-min-voltage = <725000>;
452 anatop-max-voltage = <1450000>;
453 };
454
455 regulator-vddsoc@140 {
456 compatible = "fsl,anatop-regulator";
457 regulator-name = "vddsoc";
458 regulator-min-microvolt = <725000>;
459 regulator-max-microvolt = <1450000>;
460 regulator-always-on;
461 anatop-reg-offset = <0x140>;
462 anatop-vol-bit-shift = <18>;
463 anatop-vol-bit-width = <5>;
464 anatop-min-bit-val = <1>;
465 anatop-min-voltage = <725000>;
466 anatop-max-voltage = <1450000>;
467 };
7d740f87
SG		 468 };
469
74bd88f7
RZ		 470 usbphy1: usbphy@020c9000 {
471 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 472 reg = <0x020c9000 0x1000>;
473 interrupts = <0 44 0x04>;
474 };
475
74bd88f7
RZ		 476 usbphy2: usbphy@020ca000 {
477 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 478 reg = <0x020ca000 0x1000>;
479 interrupts = <0 45 0x04>;
480 };
481
482 snvs@020cc000 {
483 reg = <0x020cc000 0x4000>;
484 interrupts = <0 19 0x04 0 20 0x04>;
485 };
486
487 epit@020d0000 { /* EPIT1 */
488 reg = <0x020d0000 0x4000>;
489 interrupts = <0 56 0x04>;
490 };
491
492 epit@020d4000 { /* EPIT2 */
493 reg = <0x020d4000 0x4000>;
494 interrupts = <0 57 0x04>;
495 };
496
497 src@020d8000 {
498 compatible = "fsl,imx6q-src";
499 reg = <0x020d8000 0x4000>;
500 interrupts = <0 91 0x04 0 96 0x04>;
501 };
502
503 gpc@020dc000 {
504 compatible = "fsl,imx6q-gpc";
505 reg = <0x020dc000 0x4000>;
506 interrupts = <0 89 0x04 0 90 0x04>;
507 };
508
509 iomuxc@020e0000 {
551fd208 510 compatible = "fsl,imx6q-iomuxc";
7d740f87 511 reg = <0x020e0000 0x4000>;
551fd208
DA		 512
513 /* shared pinctrl settings */
5ca65c18
RZ		 514 audmux {
515 pinctrl_audmux_1: audmux-1 {
516 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
517 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
518 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
519 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
520 };
521 };
522
cf922fa8
HS		 523 gpmi-nand {
524 pinctrl_gpmi_nand_1: gpmi-nand-1 {
525 fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
526 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
527 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
528 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
529 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
530 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
531 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
532 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
533 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
534 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
535 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
536 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
537 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
538 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
539 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
540 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
541 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
542 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
543 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
544 };
545 };
546
d99a79fc
RZ		 547 i2c1 {
548 pinctrl_i2c1_1: i2c1grp-1 {
549 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
550 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
551 };
552 };
553
c3001b2a
RZ		 554 serial2 {
555 pinctrl_serial2_1: serial2grp-1 {
556 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
557 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
558 };
559 };
560
551fd208
DA		 561 usdhc3 {
562 pinctrl_usdhc3_1: usdhc3grp-1 {
563 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
564 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
565 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
566 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
567 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
568 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
569 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
570 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
571 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
572 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
573 };
574 };
575
576 usdhc4 {
577 pinctrl_usdhc4_1: usdhc4grp-1 {
578 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
579 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
580 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
581 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
582 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
583 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
584 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
585 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
586 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
587 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
588 };
589 };
8ad7a305
HW		 590
591 ecspi1 {
592 pinctrl_ecspi1_1: ecspi1grp-1 {
593 fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
594 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
595 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
596 };
597 };
7d740f87
SG		 598 };
599
600 dcic@020e4000 { /* DCIC1 */
601 reg = <0x020e4000 0x4000>;
602 interrupts = <0 124 0x04>;
603 };
604
605 dcic@020e8000 { /* DCIC2 */
606 reg = <0x020e8000 0x4000>;
607 interrupts = <0 125 0x04>;
608 };
609
610 sdma@020ec000 {
611 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
612 reg = <0x020ec000 0x4000>;
613 interrupts = <0 2 0x04>;
614 };
615 };
616
617 aips-bus@02100000 { /* AIPS2 */
618 compatible = "fsl,aips-bus", "simple-bus";
619 #address-cells = <1>;
620 #size-cells = <1>;
621 reg = <0x02100000 0x100000>;
622 ranges;
623
624 caam@02100000 {
625 reg = <0x02100000 0x40000>;
626 interrupts = <0 105 0x04 0 106 0x04>;
627 };
628
629 aipstz@0217c000 { /* AIPSTZ2 */
630 reg = <0x0217c000 0x4000>;
631 };
632
74bd88f7
RZ		 633 usb@02184000 { /* USB OTG */
634 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
635 reg = <0x02184000 0x200>;
636 interrupts = <0 43 0x04>;
637 fsl,usbphy = <&usbphy1>;
638 status = "disabled";
639 };
640
641 usb@02184200 { /* USB1 */
642 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
643 reg = <0x02184200 0x200>;
644 interrupts = <0 40 0x04>;
645 fsl,usbphy = <&usbphy2>;
646 status = "disabled";
647 };
648
649 usb@02184400 { /* USB2 */
650 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
651 reg = <0x02184400 0x200>;
652 interrupts = <0 41 0x04>;
653 status = "disabled";
654 };
655
656 usb@02184600 { /* USB3 */
657 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
658 reg = <0x02184600 0x200>;
659 interrupts = <0 42 0x04>;
660 status = "disabled";
661 };
662
0c456cfa 663 ethernet@02188000 {
7d740f87
SG		 664 compatible = "fsl,imx6q-fec";
665 reg = <0x02188000 0x4000>;
666 interrupts = <0 118 0x04 0 119 0x04>;
667 status = "disabled";
668 };
669
670 mlb@0218c000 {
671 reg = <0x0218c000 0x4000>;
672 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
673 };
674
675 usdhc@02190000 { /* uSDHC1 */
676 compatible = "fsl,imx6q-usdhc";
677 reg = <0x02190000 0x4000>;
678 interrupts = <0 22 0x04>;
679 status = "disabled";
680 };
681
682 usdhc@02194000 { /* uSDHC2 */
683 compatible = "fsl,imx6q-usdhc";
684 reg = <0x02194000 0x4000>;
685 interrupts = <0 23 0x04>;
686 status = "disabled";
687 };
688
689 usdhc@02198000 { /* uSDHC3 */
690 compatible = "fsl,imx6q-usdhc";
691 reg = <0x02198000 0x4000>;
692 interrupts = <0 24 0x04>;
693 status = "disabled";
694 };
695
696 usdhc@0219c000 { /* uSDHC4 */
697 compatible = "fsl,imx6q-usdhc";
698 reg = <0x0219c000 0x4000>;
699 interrupts = <0 25 0x04>;
700 status = "disabled";
701 };
702
703 i2c@021a0000 { /* I2C1 */
704 #address-cells = <1>;
705 #size-cells = <0>;
706 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
707 reg = <0x021a0000 0x4000>;
708 interrupts = <0 36 0x04>;
709 status = "disabled";
710 };
711
712 i2c@021a4000 { /* I2C2 */
713 #address-cells = <1>;
714 #size-cells = <0>;
715 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
716 reg = <0x021a4000 0x4000>;
717 interrupts = <0 37 0x04>;
718 status = "disabled";
719 };
720
721 i2c@021a8000 { /* I2C3 */
722 #address-cells = <1>;
723 #size-cells = <0>;
724 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
725 reg = <0x021a8000 0x4000>;
726 interrupts = <0 38 0x04>;
727 status = "disabled";
728 };
729
730 romcp@021ac000 {
731 reg = <0x021ac000 0x4000>;
732 };
733
734 mmdc@021b0000 { /* MMDC0 */
735 compatible = "fsl,imx6q-mmdc";
736 reg = <0x021b0000 0x4000>;
737 };
738
739 mmdc@021b4000 { /* MMDC1 */
740 reg = <0x021b4000 0x4000>;
741 };
742
743 weim@021b8000 {
744 reg = <0x021b8000 0x4000>;
745 interrupts = <0 14 0x04>;
746 };
747
748 ocotp@021bc000 {
749 reg = <0x021bc000 0x4000>;
750 };
751
752 ocotp@021c0000 {
753 reg = <0x021c0000 0x4000>;
754 interrupts = <0 21 0x04>;
755 };
756
757 tzasc@021d0000 { /* TZASC1 */
758 reg = <0x021d0000 0x4000>;
759 interrupts = <0 108 0x04>;
760 };
761
762 tzasc@021d4000 { /* TZASC2 */
763 reg = <0x021d4000 0x4000>;
764 interrupts = <0 109 0x04>;
765 };
766
767 audmux@021d8000 {
f965cd55 768 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 769 reg = <0x021d8000 0x4000>;
f965cd55 770 status = "disabled";
7d740f87
SG		 771 };
772
773 mipi@021dc000 { /* MIPI-CSI */
774 reg = <0x021dc000 0x4000>;
775 };
776
777 mipi@021e0000 { /* MIPI-DSI */
778 reg = <0x021e0000 0x4000>;
779 };
780
781 vdoa@021e4000 {
782 reg = <0x021e4000 0x4000>;
783 interrupts = <0 18 0x04>;
784 };
785
0c456cfa 786 uart2: serial@021e8000 {
7d740f87
SG		 787 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
788 reg = <0x021e8000 0x4000>;
789 interrupts = <0 27 0x04>;
790 status = "disabled";
791 };
792
0c456cfa 793 uart3: serial@021ec000 {
7d740f87
SG		 794 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
795 reg = <0x021ec000 0x4000>;
796 interrupts = <0 28 0x04>;
797 status = "disabled";
798 };
799
0c456cfa 800 uart4: serial@021f0000 {
7d740f87
SG		 801 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
802 reg = <0x021f0000 0x4000>;
803 interrupts = <0 29 0x04>;
804 status = "disabled";
805 };
806
0c456cfa 807 uart5: serial@021f4000 {
7d740f87
SG		 808 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
809 reg = <0x021f4000 0x4000>;
810 interrupts = <0 30 0x04>;
811 status = "disabled";
812 };
813 };
814 };
815};
Linux kernel - Deliverables
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