Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /include/ "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
8f9ffecf RZ |
17 | serial0 = &uart1; |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
20 | serial3 = &uart4; | |
21 | serial4 = &uart5; | |
5230f8fe SG |
22 | gpio0 = &gpio1; |
23 | gpio1 = &gpio2; | |
24 | gpio2 = &gpio3; | |
25 | gpio3 = &gpio4; | |
26 | gpio4 = &gpio5; | |
27 | gpio5 = &gpio6; | |
28 | gpio6 = &gpio7; | |
7d740f87 SG |
29 | }; |
30 | ||
31 | cpus { | |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | ||
35 | cpu@0 { | |
36 | compatible = "arm,cortex-a9"; | |
37 | reg = <0>; | |
38 | next-level-cache = <&L2>; | |
d90df978 SG |
39 | operating-points = < |
40 | /* kHz uV */ | |
41 | 792000 1100000 | |
42 | 396000 950000 | |
43 | 198000 850000 | |
44 | >; | |
45 | clock-latency = <61036>; /* two CLK32 periods */ | |
46 | cpu0-supply = <®_cpu>; | |
7d740f87 SG |
47 | }; |
48 | ||
49 | cpu@1 { | |
50 | compatible = "arm,cortex-a9"; | |
51 | reg = <1>; | |
52 | next-level-cache = <&L2>; | |
53 | }; | |
54 | ||
55 | cpu@2 { | |
56 | compatible = "arm,cortex-a9"; | |
57 | reg = <2>; | |
58 | next-level-cache = <&L2>; | |
59 | }; | |
60 | ||
61 | cpu@3 { | |
62 | compatible = "arm,cortex-a9"; | |
63 | reg = <3>; | |
64 | next-level-cache = <&L2>; | |
65 | }; | |
66 | }; | |
67 | ||
68 | intc: interrupt-controller@00a01000 { | |
69 | compatible = "arm,cortex-a9-gic"; | |
70 | #interrupt-cells = <3>; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | interrupt-controller; | |
74 | reg = <0x00a01000 0x1000>, | |
75 | <0x00a00100 0x100>; | |
76 | }; | |
77 | ||
78 | clocks { | |
79 | #address-cells = <1>; | |
80 | #size-cells = <0>; | |
81 | ||
82 | ckil { | |
83 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
84 | clock-frequency = <32768>; | |
85 | }; | |
86 | ||
87 | ckih1 { | |
88 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
89 | clock-frequency = <0>; | |
90 | }; | |
91 | ||
92 | osc { | |
93 | compatible = "fsl,imx-osc", "fixed-clock"; | |
94 | clock-frequency = <24000000>; | |
95 | }; | |
96 | }; | |
97 | ||
98 | soc { | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | compatible = "simple-bus"; | |
102 | interrupt-parent = <&intc>; | |
103 | ranges; | |
104 | ||
e5d0f9f5 HS |
105 | dma-apbh@00110000 { |
106 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | |
107 | reg = <0x00110000 0x2000>; | |
0e87e043 | 108 | clocks = <&clks 106>; |
e5d0f9f5 HS |
109 | }; |
110 | ||
be4ccfce | 111 | gpmi: gpmi-nand@00112000 { |
0e87e043 SG |
112 | compatible = "fsl,imx6q-gpmi-nand"; |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
116 | reg-names = "gpmi-nand", "bch"; | |
117 | interrupts = <0 13 0x04>, <0 15 0x04>; | |
118 | interrupt-names = "gpmi-dma", "bch"; | |
119 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, | |
120 | <&clks 150>, <&clks 149>; | |
121 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
122 | "gpmi_bch_apb", "per1_bch"; | |
123 | fsl,gpmi-dma-channel = <0>; | |
124 | status = "disabled"; | |
cf922fa8 HS |
125 | }; |
126 | ||
7d740f87 | 127 | timer@00a00600 { |
58458e03 MZ |
128 | compatible = "arm,cortex-a9-twd-timer"; |
129 | reg = <0x00a00600 0x20>; | |
130 | interrupts = <1 13 0xf01>; | |
7d740f87 SG |
131 | }; |
132 | ||
133 | L2: l2-cache@00a02000 { | |
134 | compatible = "arm,pl310-cache"; | |
135 | reg = <0x00a02000 0x1000>; | |
136 | interrupts = <0 92 0x04>; | |
137 | cache-unified; | |
138 | cache-level = <2>; | |
139 | }; | |
140 | ||
141 | aips-bus@02000000 { /* AIPS1 */ | |
142 | compatible = "fsl,aips-bus", "simple-bus"; | |
143 | #address-cells = <1>; | |
144 | #size-cells = <1>; | |
145 | reg = <0x02000000 0x100000>; | |
146 | ranges; | |
147 | ||
148 | spba-bus@02000000 { | |
149 | compatible = "fsl,spba-bus", "simple-bus"; | |
150 | #address-cells = <1>; | |
151 | #size-cells = <1>; | |
152 | reg = <0x02000000 0x40000>; | |
153 | ranges; | |
154 | ||
7b7d6727 | 155 | spdif: spdif@02004000 { |
7d740f87 SG |
156 | reg = <0x02004000 0x4000>; |
157 | interrupts = <0 52 0x04>; | |
158 | }; | |
159 | ||
7b7d6727 | 160 | ecspi1: ecspi@02008000 { |
7d740f87 SG |
161 | #address-cells = <1>; |
162 | #size-cells = <0>; | |
163 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
164 | reg = <0x02008000 0x4000>; | |
165 | interrupts = <0 31 0x04>; | |
0e87e043 SG |
166 | clocks = <&clks 112>, <&clks 112>; |
167 | clock-names = "ipg", "per"; | |
7d740f87 SG |
168 | status = "disabled"; |
169 | }; | |
170 | ||
7b7d6727 | 171 | ecspi2: ecspi@0200c000 { |
7d740f87 SG |
172 | #address-cells = <1>; |
173 | #size-cells = <0>; | |
174 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
175 | reg = <0x0200c000 0x4000>; | |
176 | interrupts = <0 32 0x04>; | |
0e87e043 SG |
177 | clocks = <&clks 113>, <&clks 113>; |
178 | clock-names = "ipg", "per"; | |
7d740f87 SG |
179 | status = "disabled"; |
180 | }; | |
181 | ||
7b7d6727 | 182 | ecspi3: ecspi@02010000 { |
7d740f87 SG |
183 | #address-cells = <1>; |
184 | #size-cells = <0>; | |
185 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
186 | reg = <0x02010000 0x4000>; | |
187 | interrupts = <0 33 0x04>; | |
0e87e043 SG |
188 | clocks = <&clks 114>, <&clks 114>; |
189 | clock-names = "ipg", "per"; | |
7d740f87 SG |
190 | status = "disabled"; |
191 | }; | |
192 | ||
7b7d6727 | 193 | ecspi4: ecspi@02014000 { |
7d740f87 SG |
194 | #address-cells = <1>; |
195 | #size-cells = <0>; | |
196 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
197 | reg = <0x02014000 0x4000>; | |
198 | interrupts = <0 34 0x04>; | |
0e87e043 SG |
199 | clocks = <&clks 115>, <&clks 115>; |
200 | clock-names = "ipg", "per"; | |
7d740f87 SG |
201 | status = "disabled"; |
202 | }; | |
203 | ||
7b7d6727 | 204 | ecspi5: ecspi@02018000 { |
7d740f87 SG |
205 | #address-cells = <1>; |
206 | #size-cells = <0>; | |
207 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
208 | reg = <0x02018000 0x4000>; | |
209 | interrupts = <0 35 0x04>; | |
0e87e043 SG |
210 | clocks = <&clks 116>, <&clks 116>; |
211 | clock-names = "ipg", "per"; | |
7d740f87 SG |
212 | status = "disabled"; |
213 | }; | |
214 | ||
0c456cfa | 215 | uart1: serial@02020000 { |
7d740f87 SG |
216 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
217 | reg = <0x02020000 0x4000>; | |
218 | interrupts = <0 26 0x04>; | |
0e87e043 SG |
219 | clocks = <&clks 160>, <&clks 161>; |
220 | clock-names = "ipg", "per"; | |
7d740f87 SG |
221 | status = "disabled"; |
222 | }; | |
223 | ||
7b7d6727 | 224 | esai: esai@02024000 { |
7d740f87 SG |
225 | reg = <0x02024000 0x4000>; |
226 | interrupts = <0 51 0x04>; | |
227 | }; | |
228 | ||
b1a5da8e RZ |
229 | ssi1: ssi@02028000 { |
230 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
231 | reg = <0x02028000 0x4000>; |
232 | interrupts = <0 46 0x04>; | |
0e87e043 | 233 | clocks = <&clks 178>; |
b1a5da8e RZ |
234 | fsl,fifo-depth = <15>; |
235 | fsl,ssi-dma-events = <38 37>; | |
236 | status = "disabled"; | |
7d740f87 SG |
237 | }; |
238 | ||
b1a5da8e RZ |
239 | ssi2: ssi@0202c000 { |
240 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
241 | reg = <0x0202c000 0x4000>; |
242 | interrupts = <0 47 0x04>; | |
0e87e043 | 243 | clocks = <&clks 179>; |
b1a5da8e RZ |
244 | fsl,fifo-depth = <15>; |
245 | fsl,ssi-dma-events = <42 41>; | |
246 | status = "disabled"; | |
7d740f87 SG |
247 | }; |
248 | ||
b1a5da8e RZ |
249 | ssi3: ssi@02030000 { |
250 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
251 | reg = <0x02030000 0x4000>; |
252 | interrupts = <0 48 0x04>; | |
0e87e043 | 253 | clocks = <&clks 180>; |
b1a5da8e RZ |
254 | fsl,fifo-depth = <15>; |
255 | fsl,ssi-dma-events = <46 45>; | |
256 | status = "disabled"; | |
7d740f87 SG |
257 | }; |
258 | ||
7b7d6727 | 259 | asrc: asrc@02034000 { |
7d740f87 SG |
260 | reg = <0x02034000 0x4000>; |
261 | interrupts = <0 50 0x04>; | |
262 | }; | |
263 | ||
264 | spba@0203c000 { | |
265 | reg = <0x0203c000 0x4000>; | |
266 | }; | |
267 | }; | |
268 | ||
7b7d6727 | 269 | vpu: vpu@02040000 { |
7d740f87 SG |
270 | reg = <0x02040000 0x3c000>; |
271 | interrupts = <0 3 0x04 0 12 0x04>; | |
272 | }; | |
273 | ||
274 | aipstz@0207c000 { /* AIPSTZ1 */ | |
275 | reg = <0x0207c000 0x4000>; | |
276 | }; | |
277 | ||
7b7d6727 | 278 | pwm1: pwm@02080000 { |
33b38587 SH |
279 | #pwm-cells = <2>; |
280 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
281 | reg = <0x02080000 0x4000>; |
282 | interrupts = <0 83 0x04>; | |
33b38587 SH |
283 | clocks = <&clks 62>, <&clks 145>; |
284 | clock-names = "ipg", "per"; | |
7d740f87 SG |
285 | }; |
286 | ||
7b7d6727 | 287 | pwm2: pwm@02084000 { |
33b38587 SH |
288 | #pwm-cells = <2>; |
289 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
290 | reg = <0x02084000 0x4000>; |
291 | interrupts = <0 84 0x04>; | |
33b38587 SH |
292 | clocks = <&clks 62>, <&clks 146>; |
293 | clock-names = "ipg", "per"; | |
7d740f87 SG |
294 | }; |
295 | ||
7b7d6727 | 296 | pwm3: pwm@02088000 { |
33b38587 SH |
297 | #pwm-cells = <2>; |
298 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
299 | reg = <0x02088000 0x4000>; |
300 | interrupts = <0 85 0x04>; | |
33b38587 SH |
301 | clocks = <&clks 62>, <&clks 147>; |
302 | clock-names = "ipg", "per"; | |
7d740f87 SG |
303 | }; |
304 | ||
7b7d6727 | 305 | pwm4: pwm@0208c000 { |
33b38587 SH |
306 | #pwm-cells = <2>; |
307 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
308 | reg = <0x0208c000 0x4000>; |
309 | interrupts = <0 86 0x04>; | |
33b38587 SH |
310 | clocks = <&clks 62>, <&clks 148>; |
311 | clock-names = "ipg", "per"; | |
7d740f87 SG |
312 | }; |
313 | ||
7b7d6727 | 314 | can1: flexcan@02090000 { |
7d740f87 SG |
315 | reg = <0x02090000 0x4000>; |
316 | interrupts = <0 110 0x04>; | |
317 | }; | |
318 | ||
7b7d6727 | 319 | can2: flexcan@02094000 { |
7d740f87 SG |
320 | reg = <0x02094000 0x4000>; |
321 | interrupts = <0 111 0x04>; | |
322 | }; | |
323 | ||
7b7d6727 | 324 | gpt: gpt@02098000 { |
7d740f87 SG |
325 | compatible = "fsl,imx6q-gpt"; |
326 | reg = <0x02098000 0x4000>; | |
327 | interrupts = <0 55 0x04>; | |
328 | }; | |
329 | ||
4d191868 | 330 | gpio1: gpio@0209c000 { |
aeb27748 | 331 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
332 | reg = <0x0209c000 0x4000>; |
333 | interrupts = <0 66 0x04 0 67 0x04>; | |
334 | gpio-controller; | |
335 | #gpio-cells = <2>; | |
336 | interrupt-controller; | |
88cde8b7 | 337 | #interrupt-cells = <2>; |
7d740f87 SG |
338 | }; |
339 | ||
4d191868 | 340 | gpio2: gpio@020a0000 { |
aeb27748 | 341 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
342 | reg = <0x020a0000 0x4000>; |
343 | interrupts = <0 68 0x04 0 69 0x04>; | |
344 | gpio-controller; | |
345 | #gpio-cells = <2>; | |
346 | interrupt-controller; | |
88cde8b7 | 347 | #interrupt-cells = <2>; |
7d740f87 SG |
348 | }; |
349 | ||
4d191868 | 350 | gpio3: gpio@020a4000 { |
aeb27748 | 351 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
352 | reg = <0x020a4000 0x4000>; |
353 | interrupts = <0 70 0x04 0 71 0x04>; | |
354 | gpio-controller; | |
355 | #gpio-cells = <2>; | |
356 | interrupt-controller; | |
88cde8b7 | 357 | #interrupt-cells = <2>; |
7d740f87 SG |
358 | }; |
359 | ||
4d191868 | 360 | gpio4: gpio@020a8000 { |
aeb27748 | 361 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
362 | reg = <0x020a8000 0x4000>; |
363 | interrupts = <0 72 0x04 0 73 0x04>; | |
364 | gpio-controller; | |
365 | #gpio-cells = <2>; | |
366 | interrupt-controller; | |
88cde8b7 | 367 | #interrupt-cells = <2>; |
7d740f87 SG |
368 | }; |
369 | ||
4d191868 | 370 | gpio5: gpio@020ac000 { |
aeb27748 | 371 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
372 | reg = <0x020ac000 0x4000>; |
373 | interrupts = <0 74 0x04 0 75 0x04>; | |
374 | gpio-controller; | |
375 | #gpio-cells = <2>; | |
376 | interrupt-controller; | |
88cde8b7 | 377 | #interrupt-cells = <2>; |
7d740f87 SG |
378 | }; |
379 | ||
4d191868 | 380 | gpio6: gpio@020b0000 { |
aeb27748 | 381 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
382 | reg = <0x020b0000 0x4000>; |
383 | interrupts = <0 76 0x04 0 77 0x04>; | |
384 | gpio-controller; | |
385 | #gpio-cells = <2>; | |
386 | interrupt-controller; | |
88cde8b7 | 387 | #interrupt-cells = <2>; |
7d740f87 SG |
388 | }; |
389 | ||
4d191868 | 390 | gpio7: gpio@020b4000 { |
aeb27748 | 391 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
392 | reg = <0x020b4000 0x4000>; |
393 | interrupts = <0 78 0x04 0 79 0x04>; | |
394 | gpio-controller; | |
395 | #gpio-cells = <2>; | |
396 | interrupt-controller; | |
88cde8b7 | 397 | #interrupt-cells = <2>; |
7d740f87 SG |
398 | }; |
399 | ||
7b7d6727 | 400 | kpp: kpp@020b8000 { |
7d740f87 SG |
401 | reg = <0x020b8000 0x4000>; |
402 | interrupts = <0 82 0x04>; | |
403 | }; | |
404 | ||
7b7d6727 | 405 | wdog1: wdog@020bc000 { |
7d740f87 SG |
406 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
407 | reg = <0x020bc000 0x4000>; | |
408 | interrupts = <0 80 0x04>; | |
0e87e043 | 409 | clocks = <&clks 0>; |
7d740f87 SG |
410 | }; |
411 | ||
7b7d6727 | 412 | wdog2: wdog@020c0000 { |
7d740f87 SG |
413 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
414 | reg = <0x020c0000 0x4000>; | |
415 | interrupts = <0 81 0x04>; | |
0e87e043 | 416 | clocks = <&clks 0>; |
7d740f87 SG |
417 | status = "disabled"; |
418 | }; | |
419 | ||
0e87e043 | 420 | clks: ccm@020c4000 { |
7d740f87 SG |
421 | compatible = "fsl,imx6q-ccm"; |
422 | reg = <0x020c4000 0x4000>; | |
423 | interrupts = <0 87 0x04 0 88 0x04>; | |
0e87e043 | 424 | #clock-cells = <1>; |
7d740f87 SG |
425 | }; |
426 | ||
baa64151 DA |
427 | anatop: anatop@020c8000 { |
428 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
7d740f87 SG |
429 | reg = <0x020c8000 0x1000>; |
430 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | |
a1e327e6 YCLP |
431 | |
432 | regulator-1p1@110 { | |
433 | compatible = "fsl,anatop-regulator"; | |
434 | regulator-name = "vdd1p1"; | |
435 | regulator-min-microvolt = <800000>; | |
436 | regulator-max-microvolt = <1375000>; | |
437 | regulator-always-on; | |
438 | anatop-reg-offset = <0x110>; | |
439 | anatop-vol-bit-shift = <8>; | |
440 | anatop-vol-bit-width = <5>; | |
441 | anatop-min-bit-val = <4>; | |
442 | anatop-min-voltage = <800000>; | |
443 | anatop-max-voltage = <1375000>; | |
444 | }; | |
445 | ||
446 | regulator-3p0@120 { | |
447 | compatible = "fsl,anatop-regulator"; | |
448 | regulator-name = "vdd3p0"; | |
449 | regulator-min-microvolt = <2800000>; | |
450 | regulator-max-microvolt = <3150000>; | |
451 | regulator-always-on; | |
452 | anatop-reg-offset = <0x120>; | |
453 | anatop-vol-bit-shift = <8>; | |
454 | anatop-vol-bit-width = <5>; | |
455 | anatop-min-bit-val = <0>; | |
456 | anatop-min-voltage = <2625000>; | |
457 | anatop-max-voltage = <3400000>; | |
458 | }; | |
459 | ||
460 | regulator-2p5@130 { | |
461 | compatible = "fsl,anatop-regulator"; | |
462 | regulator-name = "vdd2p5"; | |
463 | regulator-min-microvolt = <2000000>; | |
464 | regulator-max-microvolt = <2750000>; | |
465 | regulator-always-on; | |
466 | anatop-reg-offset = <0x130>; | |
467 | anatop-vol-bit-shift = <8>; | |
468 | anatop-vol-bit-width = <5>; | |
469 | anatop-min-bit-val = <0>; | |
470 | anatop-min-voltage = <2000000>; | |
471 | anatop-max-voltage = <2750000>; | |
472 | }; | |
473 | ||
d90df978 | 474 | reg_cpu: regulator-vddcore@140 { |
a1e327e6 YCLP |
475 | compatible = "fsl,anatop-regulator"; |
476 | regulator-name = "cpu"; | |
477 | regulator-min-microvolt = <725000>; | |
478 | regulator-max-microvolt = <1450000>; | |
479 | regulator-always-on; | |
480 | anatop-reg-offset = <0x140>; | |
481 | anatop-vol-bit-shift = <0>; | |
482 | anatop-vol-bit-width = <5>; | |
483 | anatop-min-bit-val = <1>; | |
484 | anatop-min-voltage = <725000>; | |
485 | anatop-max-voltage = <1450000>; | |
486 | }; | |
487 | ||
488 | regulator-vddpu@140 { | |
489 | compatible = "fsl,anatop-regulator"; | |
490 | regulator-name = "vddpu"; | |
491 | regulator-min-microvolt = <725000>; | |
492 | regulator-max-microvolt = <1450000>; | |
493 | regulator-always-on; | |
494 | anatop-reg-offset = <0x140>; | |
495 | anatop-vol-bit-shift = <9>; | |
496 | anatop-vol-bit-width = <5>; | |
497 | anatop-min-bit-val = <1>; | |
498 | anatop-min-voltage = <725000>; | |
499 | anatop-max-voltage = <1450000>; | |
500 | }; | |
501 | ||
502 | regulator-vddsoc@140 { | |
503 | compatible = "fsl,anatop-regulator"; | |
504 | regulator-name = "vddsoc"; | |
505 | regulator-min-microvolt = <725000>; | |
506 | regulator-max-microvolt = <1450000>; | |
507 | regulator-always-on; | |
508 | anatop-reg-offset = <0x140>; | |
509 | anatop-vol-bit-shift = <18>; | |
510 | anatop-vol-bit-width = <5>; | |
511 | anatop-min-bit-val = <1>; | |
512 | anatop-min-voltage = <725000>; | |
513 | anatop-max-voltage = <1450000>; | |
514 | }; | |
7d740f87 SG |
515 | }; |
516 | ||
74bd88f7 RZ |
517 | usbphy1: usbphy@020c9000 { |
518 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 SG |
519 | reg = <0x020c9000 0x1000>; |
520 | interrupts = <0 44 0x04>; | |
0e87e043 | 521 | clocks = <&clks 182>; |
7d740f87 SG |
522 | }; |
523 | ||
74bd88f7 RZ |
524 | usbphy2: usbphy@020ca000 { |
525 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 SG |
526 | reg = <0x020ca000 0x1000>; |
527 | interrupts = <0 45 0x04>; | |
0e87e043 | 528 | clocks = <&clks 183>; |
7d740f87 SG |
529 | }; |
530 | ||
531 | snvs@020cc000 { | |
c9250388 SG |
532 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
533 | #address-cells = <1>; | |
534 | #size-cells = <1>; | |
535 | ranges = <0 0x020cc000 0x4000>; | |
536 | ||
537 | snvs-rtc-lp@34 { | |
538 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
539 | reg = <0x34 0x58>; | |
540 | interrupts = <0 19 0x04 0 20 0x04>; | |
541 | }; | |
7d740f87 SG |
542 | }; |
543 | ||
7b7d6727 | 544 | epit1: epit@020d0000 { /* EPIT1 */ |
7d740f87 SG |
545 | reg = <0x020d0000 0x4000>; |
546 | interrupts = <0 56 0x04>; | |
547 | }; | |
548 | ||
7b7d6727 | 549 | epit2: epit@020d4000 { /* EPIT2 */ |
7d740f87 SG |
550 | reg = <0x020d4000 0x4000>; |
551 | interrupts = <0 57 0x04>; | |
552 | }; | |
553 | ||
7b7d6727 | 554 | src: src@020d8000 { |
7d740f87 SG |
555 | compatible = "fsl,imx6q-src"; |
556 | reg = <0x020d8000 0x4000>; | |
557 | interrupts = <0 91 0x04 0 96 0x04>; | |
558 | }; | |
559 | ||
7b7d6727 | 560 | gpc: gpc@020dc000 { |
7d740f87 SG |
561 | compatible = "fsl,imx6q-gpc"; |
562 | reg = <0x020dc000 0x4000>; | |
563 | interrupts = <0 89 0x04 0 90 0x04>; | |
564 | }; | |
565 | ||
df37e0c0 DA |
566 | gpr: iomuxc-gpr@020e0000 { |
567 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
568 | reg = <0x020e0000 0x38>; | |
569 | }; | |
570 | ||
7b7d6727 | 571 | iomuxc: iomuxc@020e0000 { |
551fd208 | 572 | compatible = "fsl,imx6q-iomuxc"; |
7d740f87 | 573 | reg = <0x020e0000 0x4000>; |
551fd208 DA |
574 | |
575 | /* shared pinctrl settings */ | |
5ca65c18 RZ |
576 | audmux { |
577 | pinctrl_audmux_1: audmux-1 { | |
44a509fc SG |
578 | fsl,pins = < |
579 | 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ | |
580 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ | |
581 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ | |
582 | 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ | |
583 | >; | |
5ca65c18 RZ |
584 | }; |
585 | }; | |
586 | ||
52ccd492 SG |
587 | ecspi1 { |
588 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
589 | fsl,pins = < | |
590 | 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | |
591 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | |
592 | 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | |
593 | >; | |
594 | }; | |
595 | }; | |
596 | ||
99d5f0cc SG |
597 | enet { |
598 | pinctrl_enet_1: enetgrp-1 { | |
599 | fsl,pins = < | |
600 | 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ | |
601 | 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ | |
602 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | |
603 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | |
604 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | |
605 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | |
606 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | |
607 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | |
608 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | |
609 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | |
610 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | |
611 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | |
612 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | |
613 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | |
614 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | |
7629838c | 615 | 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ |
99d5f0cc SG |
616 | >; |
617 | }; | |
9e3c0066 SG |
618 | |
619 | pinctrl_enet_2: enetgrp-2 { | |
620 | fsl,pins = < | |
621 | 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ | |
622 | 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ | |
623 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | |
624 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | |
625 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | |
626 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | |
627 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | |
628 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | |
629 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | |
630 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | |
631 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | |
632 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | |
633 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | |
634 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | |
635 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | |
636 | >; | |
637 | }; | |
99d5f0cc SG |
638 | }; |
639 | ||
cf922fa8 HS |
640 | gpmi-nand { |
641 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | |
44a509fc SG |
642 | fsl,pins = < |
643 | 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ | |
644 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ | |
645 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ | |
646 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ | |
647 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ | |
648 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ | |
649 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ | |
650 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ | |
651 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ | |
652 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ | |
653 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ | |
654 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ | |
655 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ | |
656 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ | |
657 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ | |
658 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ | |
659 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ | |
660 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ | |
661 | 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | |
662 | >; | |
cf922fa8 HS |
663 | }; |
664 | }; | |
665 | ||
d99a79fc RZ |
666 | i2c1 { |
667 | pinctrl_i2c1_1: i2c1grp-1 { | |
44a509fc SG |
668 | fsl,pins = < |
669 | 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ | |
670 | 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ | |
671 | >; | |
d99a79fc RZ |
672 | }; |
673 | }; | |
674 | ||
497ae174 SG |
675 | uart1 { |
676 | pinctrl_uart1_1: uart1grp-1 { | |
677 | fsl,pins = < | |
678 | 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ | |
679 | 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ | |
680 | >; | |
681 | }; | |
682 | }; | |
683 | ||
e30ba89f SG |
684 | uart2 { |
685 | pinctrl_uart2_1: uart2grp-1 { | |
44a509fc SG |
686 | fsl,pins = < |
687 | 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ | |
688 | 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ | |
689 | >; | |
c3001b2a RZ |
690 | }; |
691 | }; | |
692 | ||
9e3c0066 SG |
693 | uart4 { |
694 | pinctrl_uart4_1: uart4grp-1 { | |
695 | fsl,pins = < | |
696 | 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ | |
697 | 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ | |
698 | >; | |
699 | }; | |
700 | }; | |
701 | ||
97a53092 RZ |
702 | usbotg { |
703 | pinctrl_usbotg_1: usbotggrp-1 { | |
704 | fsl,pins = < | |
705 | 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ | |
706 | >; | |
707 | }; | |
708 | }; | |
709 | ||
497ae174 SG |
710 | usdhc2 { |
711 | pinctrl_usdhc2_1: usdhc2grp-1 { | |
712 | fsl,pins = < | |
713 | 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ | |
714 | 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ | |
715 | 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ | |
716 | 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ | |
717 | 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ | |
718 | 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ | |
719 | 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ | |
720 | 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ | |
721 | 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ | |
722 | 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ | |
723 | >; | |
724 | }; | |
725 | }; | |
726 | ||
551fd208 DA |
727 | usdhc3 { |
728 | pinctrl_usdhc3_1: usdhc3grp-1 { | |
44a509fc SG |
729 | fsl,pins = < |
730 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | |
731 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | |
732 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | |
733 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | |
734 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | |
735 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | |
736 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ | |
737 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ | |
738 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ | |
739 | 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | |
740 | >; | |
551fd208 | 741 | }; |
99d5f0cc SG |
742 | |
743 | pinctrl_usdhc3_2: usdhc3grp-2 { | |
744 | fsl,pins = < | |
745 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | |
746 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | |
747 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | |
748 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | |
749 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | |
750 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | |
751 | >; | |
752 | }; | |
551fd208 DA |
753 | }; |
754 | ||
755 | usdhc4 { | |
756 | pinctrl_usdhc4_1: usdhc4grp-1 { | |
44a509fc SG |
757 | fsl,pins = < |
758 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | |
759 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | |
760 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | |
761 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | |
762 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | |
763 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | |
764 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | |
765 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | |
766 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | |
767 | 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | |
768 | >; | |
551fd208 | 769 | }; |
99d5f0cc SG |
770 | |
771 | pinctrl_usdhc4_2: usdhc4grp-2 { | |
772 | fsl,pins = < | |
773 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | |
774 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | |
775 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | |
776 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | |
777 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | |
778 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | |
779 | >; | |
780 | }; | |
551fd208 | 781 | }; |
7d740f87 SG |
782 | }; |
783 | ||
7b7d6727 | 784 | dcic1: dcic@020e4000 { |
7d740f87 SG |
785 | reg = <0x020e4000 0x4000>; |
786 | interrupts = <0 124 0x04>; | |
787 | }; | |
788 | ||
7b7d6727 | 789 | dcic2: dcic@020e8000 { |
7d740f87 SG |
790 | reg = <0x020e8000 0x4000>; |
791 | interrupts = <0 125 0x04>; | |
792 | }; | |
793 | ||
7b7d6727 | 794 | sdma: sdma@020ec000 { |
7d740f87 SG |
795 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
796 | reg = <0x020ec000 0x4000>; | |
797 | interrupts = <0 2 0x04>; | |
0e87e043 SG |
798 | clocks = <&clks 155>, <&clks 155>; |
799 | clock-names = "ipg", "ahb"; | |
d6b9c591 | 800 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
801 | }; |
802 | }; | |
803 | ||
804 | aips-bus@02100000 { /* AIPS2 */ | |
805 | compatible = "fsl,aips-bus", "simple-bus"; | |
806 | #address-cells = <1>; | |
807 | #size-cells = <1>; | |
808 | reg = <0x02100000 0x100000>; | |
809 | ranges; | |
810 | ||
811 | caam@02100000 { | |
812 | reg = <0x02100000 0x40000>; | |
813 | interrupts = <0 105 0x04 0 106 0x04>; | |
814 | }; | |
815 | ||
816 | aipstz@0217c000 { /* AIPSTZ2 */ | |
817 | reg = <0x0217c000 0x4000>; | |
818 | }; | |
819 | ||
7b7d6727 | 820 | usbotg: usb@02184000 { |
74bd88f7 RZ |
821 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
822 | reg = <0x02184000 0x200>; | |
823 | interrupts = <0 43 0x04>; | |
0e87e043 | 824 | clocks = <&clks 162>; |
74bd88f7 | 825 | fsl,usbphy = <&usbphy1>; |
28342c61 | 826 | fsl,usbmisc = <&usbmisc 0>; |
74bd88f7 RZ |
827 | status = "disabled"; |
828 | }; | |
829 | ||
7b7d6727 | 830 | usbh1: usb@02184200 { |
74bd88f7 RZ |
831 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
832 | reg = <0x02184200 0x200>; | |
833 | interrupts = <0 40 0x04>; | |
0e87e043 | 834 | clocks = <&clks 162>; |
74bd88f7 | 835 | fsl,usbphy = <&usbphy2>; |
28342c61 | 836 | fsl,usbmisc = <&usbmisc 1>; |
74bd88f7 RZ |
837 | status = "disabled"; |
838 | }; | |
839 | ||
7b7d6727 | 840 | usbh2: usb@02184400 { |
74bd88f7 RZ |
841 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
842 | reg = <0x02184400 0x200>; | |
843 | interrupts = <0 41 0x04>; | |
0e87e043 | 844 | clocks = <&clks 162>; |
28342c61 | 845 | fsl,usbmisc = <&usbmisc 2>; |
74bd88f7 RZ |
846 | status = "disabled"; |
847 | }; | |
848 | ||
7b7d6727 | 849 | usbh3: usb@02184600 { |
74bd88f7 RZ |
850 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
851 | reg = <0x02184600 0x200>; | |
852 | interrupts = <0 42 0x04>; | |
0e87e043 | 853 | clocks = <&clks 162>; |
28342c61 | 854 | fsl,usbmisc = <&usbmisc 3>; |
74bd88f7 RZ |
855 | status = "disabled"; |
856 | }; | |
857 | ||
7b7d6727 | 858 | usbmisc: usbmisc: usbmisc@02184800 { |
28342c61 RZ |
859 | #index-cells = <1>; |
860 | compatible = "fsl,imx6q-usbmisc"; | |
861 | reg = <0x02184800 0x200>; | |
862 | clocks = <&clks 162>; | |
863 | }; | |
864 | ||
7b7d6727 | 865 | fec: ethernet@02188000 { |
7d740f87 SG |
866 | compatible = "fsl,imx6q-fec"; |
867 | reg = <0x02188000 0x4000>; | |
868 | interrupts = <0 118 0x04 0 119 0x04>; | |
8dd5c66b | 869 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
7629838c | 870 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
871 | status = "disabled"; |
872 | }; | |
873 | ||
874 | mlb@0218c000 { | |
875 | reg = <0x0218c000 0x4000>; | |
876 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; | |
877 | }; | |
878 | ||
7b7d6727 | 879 | usdhc1: usdhc@02190000 { |
7d740f87 SG |
880 | compatible = "fsl,imx6q-usdhc"; |
881 | reg = <0x02190000 0x4000>; | |
882 | interrupts = <0 22 0x04>; | |
0e87e043 SG |
883 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
884 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 885 | bus-width = <4>; |
7d740f87 SG |
886 | status = "disabled"; |
887 | }; | |
888 | ||
7b7d6727 | 889 | usdhc2: usdhc@02194000 { |
7d740f87 SG |
890 | compatible = "fsl,imx6q-usdhc"; |
891 | reg = <0x02194000 0x4000>; | |
892 | interrupts = <0 23 0x04>; | |
0e87e043 SG |
893 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
894 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 895 | bus-width = <4>; |
7d740f87 SG |
896 | status = "disabled"; |
897 | }; | |
898 | ||
7b7d6727 | 899 | usdhc3: usdhc@02198000 { |
7d740f87 SG |
900 | compatible = "fsl,imx6q-usdhc"; |
901 | reg = <0x02198000 0x4000>; | |
902 | interrupts = <0 24 0x04>; | |
0e87e043 SG |
903 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
904 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 905 | bus-width = <4>; |
7d740f87 SG |
906 | status = "disabled"; |
907 | }; | |
908 | ||
7b7d6727 | 909 | usdhc4: usdhc@0219c000 { |
7d740f87 SG |
910 | compatible = "fsl,imx6q-usdhc"; |
911 | reg = <0x0219c000 0x4000>; | |
912 | interrupts = <0 25 0x04>; | |
0e87e043 SG |
913 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
914 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 915 | bus-width = <4>; |
7d740f87 SG |
916 | status = "disabled"; |
917 | }; | |
918 | ||
7b7d6727 | 919 | i2c1: i2c@021a0000 { |
7d740f87 SG |
920 | #address-cells = <1>; |
921 | #size-cells = <0>; | |
5bdfba29 | 922 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
923 | reg = <0x021a0000 0x4000>; |
924 | interrupts = <0 36 0x04>; | |
0e87e043 | 925 | clocks = <&clks 125>; |
7d740f87 SG |
926 | status = "disabled"; |
927 | }; | |
928 | ||
7b7d6727 | 929 | i2c2: i2c@021a4000 { |
7d740f87 SG |
930 | #address-cells = <1>; |
931 | #size-cells = <0>; | |
5bdfba29 | 932 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
933 | reg = <0x021a4000 0x4000>; |
934 | interrupts = <0 37 0x04>; | |
0e87e043 | 935 | clocks = <&clks 126>; |
7d740f87 SG |
936 | status = "disabled"; |
937 | }; | |
938 | ||
7b7d6727 | 939 | i2c3: i2c@021a8000 { |
7d740f87 SG |
940 | #address-cells = <1>; |
941 | #size-cells = <0>; | |
5bdfba29 | 942 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
943 | reg = <0x021a8000 0x4000>; |
944 | interrupts = <0 38 0x04>; | |
0e87e043 | 945 | clocks = <&clks 127>; |
7d740f87 SG |
946 | status = "disabled"; |
947 | }; | |
948 | ||
949 | romcp@021ac000 { | |
950 | reg = <0x021ac000 0x4000>; | |
951 | }; | |
952 | ||
7b7d6727 | 953 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
7d740f87 SG |
954 | compatible = "fsl,imx6q-mmdc"; |
955 | reg = <0x021b0000 0x4000>; | |
956 | }; | |
957 | ||
7b7d6727 | 958 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
7d740f87 SG |
959 | reg = <0x021b4000 0x4000>; |
960 | }; | |
961 | ||
962 | weim@021b8000 { | |
963 | reg = <0x021b8000 0x4000>; | |
964 | interrupts = <0 14 0x04>; | |
965 | }; | |
966 | ||
967 | ocotp@021bc000 { | |
968 | reg = <0x021bc000 0x4000>; | |
969 | }; | |
970 | ||
971 | ocotp@021c0000 { | |
972 | reg = <0x021c0000 0x4000>; | |
973 | interrupts = <0 21 0x04>; | |
974 | }; | |
975 | ||
976 | tzasc@021d0000 { /* TZASC1 */ | |
977 | reg = <0x021d0000 0x4000>; | |
978 | interrupts = <0 108 0x04>; | |
979 | }; | |
980 | ||
981 | tzasc@021d4000 { /* TZASC2 */ | |
982 | reg = <0x021d4000 0x4000>; | |
983 | interrupts = <0 109 0x04>; | |
984 | }; | |
985 | ||
7b7d6727 | 986 | audmux: audmux@021d8000 { |
f965cd55 | 987 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 988 | reg = <0x021d8000 0x4000>; |
f965cd55 | 989 | status = "disabled"; |
7d740f87 SG |
990 | }; |
991 | ||
992 | mipi@021dc000 { /* MIPI-CSI */ | |
993 | reg = <0x021dc000 0x4000>; | |
994 | }; | |
995 | ||
996 | mipi@021e0000 { /* MIPI-DSI */ | |
997 | reg = <0x021e0000 0x4000>; | |
998 | }; | |
999 | ||
1000 | vdoa@021e4000 { | |
1001 | reg = <0x021e4000 0x4000>; | |
1002 | interrupts = <0 18 0x04>; | |
1003 | }; | |
1004 | ||
0c456cfa | 1005 | uart2: serial@021e8000 { |
7d740f87 SG |
1006 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1007 | reg = <0x021e8000 0x4000>; | |
1008 | interrupts = <0 27 0x04>; | |
0e87e043 SG |
1009 | clocks = <&clks 160>, <&clks 161>; |
1010 | clock-names = "ipg", "per"; | |
7d740f87 SG |
1011 | status = "disabled"; |
1012 | }; | |
1013 | ||
0c456cfa | 1014 | uart3: serial@021ec000 { |
7d740f87 SG |
1015 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1016 | reg = <0x021ec000 0x4000>; | |
1017 | interrupts = <0 28 0x04>; | |
0e87e043 SG |
1018 | clocks = <&clks 160>, <&clks 161>; |
1019 | clock-names = "ipg", "per"; | |
7d740f87 SG |
1020 | status = "disabled"; |
1021 | }; | |
1022 | ||
0c456cfa | 1023 | uart4: serial@021f0000 { |
7d740f87 SG |
1024 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1025 | reg = <0x021f0000 0x4000>; | |
1026 | interrupts = <0 29 0x04>; | |
0e87e043 SG |
1027 | clocks = <&clks 160>, <&clks 161>; |
1028 | clock-names = "ipg", "per"; | |
7d740f87 SG |
1029 | status = "disabled"; |
1030 | }; | |
1031 | ||
0c456cfa | 1032 | uart5: serial@021f4000 { |
7d740f87 SG |
1033 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1034 | reg = <0x021f4000 0x4000>; | |
1035 | interrupts = <0 30 0x04>; | |
0e87e043 SG |
1036 | clocks = <&clks 160>, <&clks 161>; |
1037 | clock-names = "ipg", "per"; | |
7d740f87 SG |
1038 | status = "disabled"; |
1039 | }; | |
1040 | }; | |
91660d74 SH |
1041 | |
1042 | ipu1: ipu@02400000 { | |
1043 | #crtc-cells = <1>; | |
1044 | compatible = "fsl,imx6q-ipu"; | |
1045 | reg = <0x02400000 0x400000>; | |
1046 | interrupts = <0 6 0x4 0 5 0x4>; | |
1047 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; | |
1048 | clock-names = "bus", "di0", "di1"; | |
1049 | }; | |
1050 | ||
1051 | ipu2: ipu@02800000 { | |
1052 | #crtc-cells = <1>; | |
1053 | compatible = "fsl,imx6q-ipu"; | |
1054 | reg = <0x02800000 0x400000>; | |
1055 | interrupts = <0 8 0x4 0 7 0x4>; | |
1056 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; | |
1057 | clock-names = "bus", "di0", "di1"; | |
1058 | }; | |
7d740f87 SG |
1059 | }; |
1060 | }; |