[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi


/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
#include "imx6qdl.dtsi"

/ {
	aliases {
		ipu1 = &ipu2;
		spi4 = &ecspi5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				1200000 1275000
				996000  1250000
				852000  1250000
				792000  1175000
				396000  975000
			>;
			fsl,soc-operating-points = <
				/* ARM kHz  SOC-PU uV */
				1200000 1275000
				996000	1250000
				852000	1250000
				792000	1175000
				396000	1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks IMX6QDL_CLK_ARM>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
				 <&clks IMX6QDL_CLK_STEP>,
				 <&clks IMX6QDL_CLK_PLL1_SW>,
				 <&clks IMX6QDL_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			pu-supply = <&reg_pu>;
			soc-supply = <&reg_soc>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		ocram: sram@00900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x40000>;
			clocks = <&clks IMX6QDL_CLK_OCRAM>;
		};

		aips-bus@02000000 { /* AIPS1 */
			spba-bus@02000000 {
				ecspi5: ecspi@02018000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02018000 0x4000>;
					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6Q_CLK_ECSPI5>,
						 <&clks IMX6Q_CLK_ECSPI5>;
					clock-names = "ipg", "per";
					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};
			};

			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6q-iomuxc";

				ipu2 {
					pinctrl_ipu2_1: ipu2grp-1 {
						fsl,pins = <
							MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
							MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
							MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
							MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
							MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
							MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
							MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
							MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
							MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
							MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
							MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
							MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
							MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
							MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
							MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
							MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
							MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
							MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
							MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
							MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
							MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
							MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
							MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
							MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
							MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
							MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
							MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
							MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
							MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
						>;
					};
				};
			};
		};

		sata: sata@02200000 {
			compatible = "fsl,imx6q-ahci";
			reg = <0x02200000 0x4000>;
			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_SATA>,
				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
				 <&clks IMX6QDL_CLK_AHB>;
			clock-names = "sata", "sata_ref", "ahb";
			status = "disabled";
		};

		ipu2: ipu@02800000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02800000 0x400000>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_IPU2>,
				 <&clks IMX6QDL_CLK_IPU2_DI0>,
				 <&clks IMX6QDL_CLK_IPU2_DI1>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 4>;

			ipu2_csi0: port@0 {
				reg = <0>;
			};

			ipu2_csi1: port@1 {
				reg = <1>;
			};

			ipu2_di0: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;

				ipu2_di0_disp0: endpoint@0 {
				};

				ipu2_di0_hdmi: endpoint@1 {
					remote-endpoint = <&hdmi_mux_2>;
				};

				ipu2_di0_mipi: endpoint@2 {
				};

				ipu2_di0_lvds0: endpoint@3 {
					remote-endpoint = <&lvds0_mux_2>;
				};

				ipu2_di0_lvds1: endpoint@4 {
					remote-endpoint = <&lvds1_mux_2>;
				};
			};

			ipu2_di1: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;

				ipu2_di1_hdmi: endpoint@1 {
					remote-endpoint = <&hdmi_mux_3>;
				};

				ipu2_di1_mipi: endpoint@2 {
				};

				ipu2_di1_lvds0: endpoint@3 {
					remote-endpoint = <&lvds0_mux_3>;
				};

				ipu2_di1_lvds1: endpoint@4 {
					remote-endpoint = <&lvds1_mux_3>;
				};
			};
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	};
};

&hdmi {
	compatible = "fsl,imx6q-hdmi";

	port@2 {
		reg = <2>;

		hdmi_mux_2: endpoint {
			remote-endpoint = <&ipu2_di0_hdmi>;
		};
	};

	port@3 {
		reg = <3>;

		hdmi_mux_3: endpoint {
			remote-endpoint = <&ipu2_di1_hdmi>;
		};
	};
};

&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
		      "di0", "di1";

	lvds-channel@0 {
		port@2 {
			reg = <2>;

			lvds0_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_lvds0>;
			};
		};

		port@3 {
			reg = <3>;

			lvds0_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_lvds0>;
			};
		};
	};

	lvds-channel@1 {
		port@2 {
			reg = <2>;

			lvds1_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_lvds1>;
			};
		};

		port@3 {
			reg = <3>;

			lvds1_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_lvds1>;
			};
		};
	};
};

&mipi_dsi {
	ports {
		port@2 {
			reg = <2>;

			mipi_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_mipi>;
			};
		};

		port@3 {
			reg = <3>;

			mipi_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_mipi>;
			};
		};
	};
};

&vpu {
	compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
Commit	Line	Data
7c1da585 SG	1
	2	/*
	3	* Copyright 2013 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	*/
	10
e6117ff3	11	#include <dt-bindings/interrupt-controller/irq.h>
e1641531	12	#include "imx6q-pinfunc.h"
c56009b2	13	#include "imx6qdl.dtsi"
7c1da585 SG	14
7c1da585 SG	15	/ {
a26be0f0	16	aliases {
41beef39	17	ipu1 = &ipu2;
a26be0f0 SH	18	spi4 = &ecspi5;
	19	};
	20
7c1da585 SG	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu@0 {
	26	compatible = "arm,cortex-a9";
7925e89f	27	device_type = "cpu";
7c1da585 SG	28	reg = <0>;
	29	next-level-cache = <&L2>;
	30	operating-points = <
	31	/* kHz uV */
	32	1200000 1275000
	33	996000 1250000
89ef8ef4	34	852000 1250000
eabb3227	35	792000 1175000
26ea5801	36	396000 975000
7c1da585	37	>;
69171eda AH	38	fsl,soc-operating-points = <
	39	/* ARM kHz SOC-PU uV */
	40	1200000 1275000
	41	996000 1250000
89ef8ef4	42	852000 1250000
69171eda AH	43	792000 1175000
69171eda AH	44	396000 1175000
7c1da585 SG	45	>;
7c1da585 SG	46	clock-latency = <61036>; /* two CLK32 periods */
8888f651 SG	47	clocks = <&clks IMX6QDL_CLK_ARM>,
	48	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	49	<&clks IMX6QDL_CLK_STEP>,
	50	<&clks IMX6QDL_CLK_PLL1_SW>,
	51	<&clks IMX6QDL_CLK_PLL1_SYS>;
7c1da585 SG	52	clock-names = "arm", "pll2_pfd2_396m", "step",
	53	"pll1_sw", "pll1_sys";
	54	arm-supply = <&reg_arm>;
	55	pu-supply = <&reg_pu>;
	56	soc-supply = <&reg_soc>;
	57	};
	58
	59	cpu@1 {
	60	compatible = "arm,cortex-a9";
7925e89f	61	device_type = "cpu";
7c1da585 SG	62	reg = <1>;
	63	next-level-cache = <&L2>;
	64	};
	65
	66	cpu@2 {
	67	compatible = "arm,cortex-a9";
7925e89f	68	device_type = "cpu";
7c1da585 SG	69	reg = <2>;
	70	next-level-cache = <&L2>;
	71	};
	72
	73	cpu@3 {
	74	compatible = "arm,cortex-a9";
7925e89f	75	device_type = "cpu";
7c1da585 SG	76	reg = <3>;
	77	next-level-cache = <&L2>;
	78	};
	79	};
	80
	81	soc {
951ebf58 SG	82	ocram: sram@00900000 {
	83	compatible = "mmio-sram";
	84	reg = <0x00900000 0x40000>;
8888f651	85	clocks = <&clks IMX6QDL_CLK_OCRAM>;
951ebf58 SG	86	};
951ebf58 SG	87
7c1da585 SG	88	aips-bus@02000000 { /* AIPS1 */
	89	spba-bus@02000000 {
	90	ecspi5: ecspi@02018000 {
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	94	reg = <0x02018000 0x4000>;
e6117ff3	95	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
8888f651 SG	96	clocks = <&clks IMX6Q_CLK_ECSPI5>,
8888f651 SG	97	<&clks IMX6Q_CLK_ECSPI5>;
7c1da585	98	clock-names = "ipg", "per";
67794025 AB	99	dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
67794025 AB	100	dma-names = "rx", "tx";
7c1da585 SG	101	status = "disabled";
	102	};
	103	};
	104
	105	iomuxc: iomuxc@020e0000 {
	106	compatible = "fsl,imx6q-iomuxc";
b72ce929 SG	107
	108	ipu2 {
	109	pinctrl_ipu2_1: ipu2grp-1 {
	110	fsl,pins = <
	111	MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
	112	MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
	113	MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
	114	MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
	115	MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
	116	MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
	117	MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
	118	MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
	119	MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
	120	MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
	121	MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
	122	MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
	123	MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
	124	MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
	125	MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
	126	MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
	127	MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
	128	MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
	129	MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
	130	MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
	131	MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
	132	MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
	133	MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
	134	MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
	135	MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
	136	MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
	137	MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
	138	MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
	139	MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
	140	>;
	141	};
	142	};
7c1da585 SG	143	};
	144	};
	145
0fb1f804 RZ	146	sata: sata@02200000 {
	147	compatible = "fsl,imx6q-ahci";
	148	reg = <0x02200000 0x4000>;
e6117ff3	149	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
8888f651 SG	150	clocks = <&clks IMX6QDL_CLK_SATA>,
	151	<&clks IMX6QDL_CLK_SATA_REF_100M>,
	152	<&clks IMX6QDL_CLK_AHB>;
0fb1f804 RZ	153	clock-names = "sata", "sata_ref", "ahb";
	154	status = "disabled";
	155	};
	156
7c1da585	157	ipu2: ipu@02800000 {
4520e692 PZ	158	#address-cells = <1>;
4520e692 PZ	159	#size-cells = <0>;
7c1da585 SG	160	compatible = "fsl,imx6q-ipu";
7c1da585 SG	161	reg = <0x02800000 0x400000>;
e6117ff3 TK	162	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
e6117ff3 TK	163	<0 7 IRQ_TYPE_LEVEL_HIGH>;
8888f651 SG	164	clocks = <&clks IMX6QDL_CLK_IPU2>,
	165	<&clks IMX6QDL_CLK_IPU2_DI0>,
	166	<&clks IMX6QDL_CLK_IPU2_DI1>;
7c1da585	167	clock-names = "bus", "di0", "di1";
09ebf366	168	resets = <&src 4>;
4520e692	169
c0470c38 PZ	170	ipu2_csi0: port@0 {
	171	reg = <0>;
	172	};
	173
	174	ipu2_csi1: port@1 {
	175	reg = <1>;
	176	};
	177
4520e692 PZ	178	ipu2_di0: port@2 {
	179	#address-cells = <1>;
	180	#size-cells = <0>;
	181	reg = <2>;
	182
	183	ipu2_di0_disp0: endpoint@0 {
	184	};
	185
	186	ipu2_di0_hdmi: endpoint@1 {
	187	remote-endpoint = <&hdmi_mux_2>;
	188	};
	189
	190	ipu2_di0_mipi: endpoint@2 {
	191	};
	192
	193	ipu2_di0_lvds0: endpoint@3 {
	194	remote-endpoint = <&lvds0_mux_2>;
	195	};
	196
	197	ipu2_di0_lvds1: endpoint@4 {
	198	remote-endpoint = <&lvds1_mux_2>;
	199	};
	200	};
	201
	202	ipu2_di1: port@3 {
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	reg = <3>;
	206
	207	ipu2_di1_hdmi: endpoint@1 {
	208	remote-endpoint = <&hdmi_mux_3>;
	209	};
	210
	211	ipu2_di1_mipi: endpoint@2 {
	212	};
	213
	214	ipu2_di1_lvds0: endpoint@3 {
	215	remote-endpoint = <&lvds0_mux_3>;
	216	};
	217
	218	ipu2_di1_lvds1: endpoint@4 {
	219	remote-endpoint = <&lvds1_mux_3>;
	220	};
	221	};
	222	};
	223	};
	224
	225	display-subsystem {
	226	compatible = "fsl,imx-display-subsystem";
	227	ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	228	};
	229	};
	230
	231	&hdmi {
	232	compatible = "fsl,imx6q-hdmi";
	233
	234	port@2 {
	235	reg = <2>;
	236
	237	hdmi_mux_2: endpoint {
	238	remote-endpoint = <&ipu2_di0_hdmi>;
	239	};
	240	};
	241
242	port@3 {
243	reg = <3>;
244
245	hdmi_mux_3: endpoint {
246	remote-endpoint = <&ipu2_di1_hdmi>;
7c1da585 SG	247	};
	248	};
	249	};
41c04342 ST	250
41c04342 ST	251	&ldb {
8888f651 SG	252	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	253	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	254	<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
	255	<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
41c04342 ST	256	clock-names = "di0_pll", "di1_pll",
	257	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	258	"di0", "di1";
	259
	260	lvds-channel@0 {
4520e692 PZ	261	port@2 {
	262	reg = <2>;
	263
	264	lvds0_mux_2: endpoint {
	265	remote-endpoint = <&ipu2_di0_lvds0>;
	266	};
	267	};
	268
	269	port@3 {
	270	reg = <3>;
	271
	272	lvds0_mux_3: endpoint {
	273	remote-endpoint = <&ipu2_di1_lvds0>;
	274	};
	275	};
41c04342 ST	276	};
	277
	278	lvds-channel@1 {
4520e692 PZ	279	port@2 {
	280	reg = <2>;
	281
	282	lvds1_mux_2: endpoint {
	283	remote-endpoint = <&ipu2_di0_lvds1>;
	284	};
	285	};
	286
	287	port@3 {
	288	reg = <3>;
	289
	290	lvds1_mux_3: endpoint {
	291	remote-endpoint = <&ipu2_di1_lvds1>;
	292	};
	293	};
41c04342 ST	294	};
41c04342 ST	295	};
04cec1a2	296
4520e692	297	&mipi_dsi {
70c2652c LY	298	ports {
	299	port@2 {
	300	reg = <2>;
4520e692	301
70c2652c LY	302	mipi_mux_2: endpoint {
	303	remote-endpoint = <&ipu2_di0_mipi>;
	304	};
4520e692	305	};
4520e692	306
70c2652c LY	307	port@3 {
70c2652c LY	308	reg = <3>;
4520e692	309
70c2652c LY	310	mipi_mux_3: endpoint {
	311	remote-endpoint = <&ipu2_di1_mipi>;
	312	};
4520e692 PZ	313	};
4520e692 PZ	314	};
04cec1a2	315	};
a04a0b6f PZ	316
	317	&vpu {
	318	compatible = "fsl,imx6q-vpu", "cnm,coda960";
	319	};