projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d740f87 SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 13 | /include/ "skeleton.dtsi" | |
| 14 | ||
| 15 | / { | |
| 16 | aliases { | |
| 8f9ffecf RZ |
17 | serial0 = &uart1; |
| 18 | serial1 = &uart2; | |
| 19 | serial2 = &uart3; | |
| 20 | serial3 = &uart4; | |
| 21 | serial4 = &uart5; | |
| 7d740f87 SG |
22 | }; |
| 23 | ||
| 24 | cpus { | |
| 25 | #address-cells = <1>; | |
| 26 | #size-cells = <0>; | |
| 27 | ||
| 28 | cpu@0 { | |
| 29 | compatible = "arm,cortex-a9"; | |
| 30 | reg = <0>; | |
| 31 | next-level-cache = <&L2>; | |
| 32 | }; | |
| 33 | ||
| 34 | cpu@1 { | |
| 35 | compatible = "arm,cortex-a9"; | |
| 36 | reg = <1>; | |
| 37 | next-level-cache = <&L2>; | |
| 38 | }; | |
| 39 | ||
| 40 | cpu@2 { | |
| 41 | compatible = "arm,cortex-a9"; | |
| 42 | reg = <2>; | |
| 43 | next-level-cache = <&L2>; | |
| 44 | }; | |
| 45 | ||
| 46 | cpu@3 { | |
| 47 | compatible = "arm,cortex-a9"; | |
| 48 | reg = <3>; | |
| 49 | next-level-cache = <&L2>; | |
| 50 | }; | |
| 51 | }; | |
| 52 | ||
| 53 | intc: interrupt-controller@00a01000 { | |
| 54 | compatible = "arm,cortex-a9-gic"; | |
| 55 | #interrupt-cells = <3>; | |
| 56 | #address-cells = <1>; | |
| 57 | #size-cells = <1>; | |
| 58 | interrupt-controller; | |
| 59 | reg = <0x00a01000 0x1000>, | |
| 60 | <0x00a00100 0x100>; | |
| 61 | }; | |
| 62 | ||
| 63 | clocks { | |
| 64 | #address-cells = <1>; | |
| 65 | #size-cells = <0>; | |
| 66 | ||
| 67 | ckil { | |
| 68 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 69 | clock-frequency = <32768>; | |
| 70 | }; | |
| 71 | ||
| 72 | ckih1 { | |
| 73 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 74 | clock-frequency = <0>; | |
| 75 | }; | |
| 76 | ||
| 77 | osc { | |
| 78 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 79 | clock-frequency = <24000000>; | |
| 80 | }; | |
| 81 | }; | |
| 82 | ||
| 83 | soc { | |
| 84 | #address-cells = <1>; | |
| 85 | #size-cells = <1>; | |
| 86 | compatible = "simple-bus"; | |
| 87 | interrupt-parent = <&intc>; | |
| 88 | ranges; | |
| 89 | ||
| 90 | timer@00a00600 { | |
| 58458e03 MZ |
91 | compatible = "arm,cortex-a9-twd-timer"; |
| 92 | reg = <0x00a00600 0x20>; | |
| 93 | interrupts = <1 13 0xf01>; | |
| 7d740f87 SG |
94 | }; |
| 95 | ||
| 96 | L2: l2-cache@00a02000 { | |
| 97 | compatible = "arm,pl310-cache"; | |
| 98 | reg = <0x00a02000 0x1000>; | |
| 99 | interrupts = <0 92 0x04>; | |
| 100 | cache-unified; | |
| 101 | cache-level = <2>; | |
| 102 | }; | |
| 103 | ||
| 104 | aips-bus@02000000 { /* AIPS1 */ | |
| 105 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 106 | #address-cells = <1>; | |
| 107 | #size-cells = <1>; | |
| 108 | reg = <0x02000000 0x100000>; | |
| 109 | ranges; | |
| 110 | ||
| 111 | spba-bus@02000000 { | |
| 112 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 113 | #address-cells = <1>; | |
| 114 | #size-cells = <1>; | |
| 115 | reg = <0x02000000 0x40000>; | |
| 116 | ranges; | |
| 117 | ||
| 118 | spdif@02004000 { | |
| 119 | reg = <0x02004000 0x4000>; | |
| 120 | interrupts = <0 52 0x04>; | |
| 121 | }; | |
| 122 | ||
| 123 | ecspi@02008000 { /* eCSPI1 */ | |
| 124 | #address-cells = <1>; | |
| 125 | #size-cells = <0>; | |
| 126 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 127 | reg = <0x02008000 0x4000>; | |
| 128 | interrupts = <0 31 0x04>; | |
| 129 | status = "disabled"; | |
| 130 | }; | |
| 131 | ||
| 132 | ecspi@0200c000 { /* eCSPI2 */ | |
| 133 | #address-cells = <1>; | |
| 134 | #size-cells = <0>; | |
| 135 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 136 | reg = <0x0200c000 0x4000>; | |
| 137 | interrupts = <0 32 0x04>; | |
| 138 | status = "disabled"; | |
| 139 | }; | |
| 140 | ||
| 141 | ecspi@02010000 { /* eCSPI3 */ | |
| 142 | #address-cells = <1>; | |
| 143 | #size-cells = <0>; | |
| 144 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 145 | reg = <0x02010000 0x4000>; | |
| 146 | interrupts = <0 33 0x04>; | |
| 147 | status = "disabled"; | |
| 148 | }; | |
| 149 | ||
| 150 | ecspi@02014000 { /* eCSPI4 */ | |
| 151 | #address-cells = <1>; | |
| 152 | #size-cells = <0>; | |
| 153 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 154 | reg = <0x02014000 0x4000>; | |
| 155 | interrupts = <0 34 0x04>; | |
| 156 | status = "disabled"; | |
| 157 | }; | |
| 158 | ||
| 159 | ecspi@02018000 { /* eCSPI5 */ | |
| 160 | #address-cells = <1>; | |
| 161 | #size-cells = <0>; | |
| 162 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 163 | reg = <0x02018000 0x4000>; | |
| 164 | interrupts = <0 35 0x04>; | |
| 165 | status = "disabled"; | |
| 166 | }; | |
| 167 | ||
| 8f9ffecf | 168 | uart1: uart@02020000 { |
| 7d740f87 SG |
169 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 170 | reg = <0x02020000 0x4000>; | |
| 171 | interrupts = <0 26 0x04>; | |
| 172 | status = "disabled"; | |
| 173 | }; | |
| 174 | ||
| 175 | esai@02024000 { | |
| 176 | reg = <0x02024000 0x4000>; | |
| 177 | interrupts = <0 51 0x04>; | |
| 178 | }; | |
| 179 | ||
| 180 | ssi@02028000 { /* SSI1 */ | |
| 181 | reg = <0x02028000 0x4000>; | |
| 182 | interrupts = <0 46 0x04>; | |
| 183 | }; | |
| 184 | ||
| 185 | ssi@0202c000 { /* SSI2 */ | |
| 186 | reg = <0x0202c000 0x4000>; | |
| 187 | interrupts = <0 47 0x04>; | |
| 188 | }; | |
| 189 | ||
| 190 | ssi@02030000 { /* SSI3 */ | |
| 191 | reg = <0x02030000 0x4000>; | |
| 192 | interrupts = <0 48 0x04>; | |
| 193 | }; | |
| 194 | ||
| 195 | asrc@02034000 { | |
| 196 | reg = <0x02034000 0x4000>; | |
| 197 | interrupts = <0 50 0x04>; | |
| 198 | }; | |
| 199 | ||
| 200 | spba@0203c000 { | |
| 201 | reg = <0x0203c000 0x4000>; | |
| 202 | }; | |
| 203 | }; | |
| 204 | ||
| 205 | vpu@02040000 { | |
| 206 | reg = <0x02040000 0x3c000>; | |
| 207 | interrupts = <0 3 0x04 0 12 0x04>; | |
| 208 | }; | |
| 209 | ||
| 210 | aipstz@0207c000 { /* AIPSTZ1 */ | |
| 211 | reg = <0x0207c000 0x4000>; | |
| 212 | }; | |
| 213 | ||
| 214 | pwm@02080000 { /* PWM1 */ | |
| 215 | reg = <0x02080000 0x4000>; | |
| 216 | interrupts = <0 83 0x04>; | |
| 217 | }; | |
| 218 | ||
| 219 | pwm@02084000 { /* PWM2 */ | |
| 220 | reg = <0x02084000 0x4000>; | |
| 221 | interrupts = <0 84 0x04>; | |
| 222 | }; | |
| 223 | ||
| 224 | pwm@02088000 { /* PWM3 */ | |
| 225 | reg = <0x02088000 0x4000>; | |
| 226 | interrupts = <0 85 0x04>; | |
| 227 | }; | |
| 228 | ||
| 229 | pwm@0208c000 { /* PWM4 */ | |
| 230 | reg = <0x0208c000 0x4000>; | |
| 231 | interrupts = <0 86 0x04>; | |
| 232 | }; | |
| 233 | ||
| 234 | flexcan@02090000 { /* CAN1 */ | |
| 235 | reg = <0x02090000 0x4000>; | |
| 236 | interrupts = <0 110 0x04>; | |
| 237 | }; | |
| 238 | ||
| 239 | flexcan@02094000 { /* CAN2 */ | |
| 240 | reg = <0x02094000 0x4000>; | |
| 241 | interrupts = <0 111 0x04>; | |
| 242 | }; | |
| 243 | ||
| 244 | gpt@02098000 { | |
| 245 | compatible = "fsl,imx6q-gpt"; | |
| 246 | reg = <0x02098000 0x4000>; | |
| 247 | interrupts = <0 55 0x04>; | |
| 248 | }; | |
| 249 | ||
| 4d191868 | 250 | gpio1: gpio@0209c000 { |
| 7d740f87 SG |
251 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 252 | reg = <0x0209c000 0x4000>; | |
| 253 | interrupts = <0 66 0x04 0 67 0x04>; | |
| 254 | gpio-controller; | |
| 255 | #gpio-cells = <2>; | |
| 256 | interrupt-controller; | |
| 257 | #interrupt-cells = <1>; | |
| 258 | }; | |
| 259 | ||
| 4d191868 | 260 | gpio2: gpio@020a0000 { |
| 7d740f87 SG |
261 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 262 | reg = <0x020a0000 0x4000>; | |
| 263 | interrupts = <0 68 0x04 0 69 0x04>; | |
| 264 | gpio-controller; | |
| 265 | #gpio-cells = <2>; | |
| 266 | interrupt-controller; | |
| 267 | #interrupt-cells = <1>; | |
| 268 | }; | |
| 269 | ||
| 4d191868 | 270 | gpio3: gpio@020a4000 { |
| 7d740f87 SG |
271 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 272 | reg = <0x020a4000 0x4000>; | |
| 273 | interrupts = <0 70 0x04 0 71 0x04>; | |
| 274 | gpio-controller; | |
| 275 | #gpio-cells = <2>; | |
| 276 | interrupt-controller; | |
| 277 | #interrupt-cells = <1>; | |
| 278 | }; | |
| 279 | ||
| 4d191868 | 280 | gpio4: gpio@020a8000 { |
| 7d740f87 SG |
281 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 282 | reg = <0x020a8000 0x4000>; | |
| 283 | interrupts = <0 72 0x04 0 73 0x04>; | |
| 284 | gpio-controller; | |
| 285 | #gpio-cells = <2>; | |
| 286 | interrupt-controller; | |
| 287 | #interrupt-cells = <1>; | |
| 288 | }; | |
| 289 | ||
| 4d191868 | 290 | gpio5: gpio@020ac000 { |
| 7d740f87 SG |
291 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 292 | reg = <0x020ac000 0x4000>; | |
| 293 | interrupts = <0 74 0x04 0 75 0x04>; | |
| 294 | gpio-controller; | |
| 295 | #gpio-cells = <2>; | |
| 296 | interrupt-controller; | |
| 297 | #interrupt-cells = <1>; | |
| 298 | }; | |
| 299 | ||
| 4d191868 | 300 | gpio6: gpio@020b0000 { |
| 7d740f87 SG |
301 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 302 | reg = <0x020b0000 0x4000>; | |
| 303 | interrupts = <0 76 0x04 0 77 0x04>; | |
| 304 | gpio-controller; | |
| 305 | #gpio-cells = <2>; | |
| 306 | interrupt-controller; | |
| 307 | #interrupt-cells = <1>; | |
| 308 | }; | |
| 309 | ||
| 4d191868 | 310 | gpio7: gpio@020b4000 { |
| 7d740f87 SG |
311 | compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; |
| 312 | reg = <0x020b4000 0x4000>; | |
| 313 | interrupts = <0 78 0x04 0 79 0x04>; | |
| 314 | gpio-controller; | |
| 315 | #gpio-cells = <2>; | |
| 316 | interrupt-controller; | |
| 317 | #interrupt-cells = <1>; | |
| 318 | }; | |
| 319 | ||
| 320 | kpp@020b8000 { | |
| 321 | reg = <0x020b8000 0x4000>; | |
| 322 | interrupts = <0 82 0x04>; | |
| 323 | }; | |
| 324 | ||
| 325 | wdog@020bc000 { /* WDOG1 */ | |
| 326 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | |
| 327 | reg = <0x020bc000 0x4000>; | |
| 328 | interrupts = <0 80 0x04>; | |
| 329 | status = "disabled"; | |
| 330 | }; | |
| 331 | ||
| 332 | wdog@020c0000 { /* WDOG2 */ | |
| 333 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | |
| 334 | reg = <0x020c0000 0x4000>; | |
| 335 | interrupts = <0 81 0x04>; | |
| 336 | status = "disabled"; | |
| 337 | }; | |
| 338 | ||
| 339 | ccm@020c4000 { | |
| 340 | compatible = "fsl,imx6q-ccm"; | |
| 341 | reg = <0x020c4000 0x4000>; | |
| 342 | interrupts = <0 87 0x04 0 88 0x04>; | |
| 343 | }; | |
| 344 | ||
| 345 | anatop@020c8000 { | |
| 346 | compatible = "fsl,imx6q-anatop"; | |
| 347 | reg = <0x020c8000 0x1000>; | |
| 348 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | |
| a1e327e6 YCLP |
349 | |
| 350 | regulator-1p1@110 { | |
| 351 | compatible = "fsl,anatop-regulator"; | |
| 352 | regulator-name = "vdd1p1"; | |
| 353 | regulator-min-microvolt = <800000>; | |
| 354 | regulator-max-microvolt = <1375000>; | |
| 355 | regulator-always-on; | |
| 356 | anatop-reg-offset = <0x110>; | |
| 357 | anatop-vol-bit-shift = <8>; | |
| 358 | anatop-vol-bit-width = <5>; | |
| 359 | anatop-min-bit-val = <4>; | |
| 360 | anatop-min-voltage = <800000>; | |
| 361 | anatop-max-voltage = <1375000>; | |
| 362 | }; | |
| 363 | ||
| 364 | regulator-3p0@120 { | |
| 365 | compatible = "fsl,anatop-regulator"; | |
| 366 | regulator-name = "vdd3p0"; | |
| 367 | regulator-min-microvolt = <2800000>; | |
| 368 | regulator-max-microvolt = <3150000>; | |
| 369 | regulator-always-on; | |
| 370 | anatop-reg-offset = <0x120>; | |
| 371 | anatop-vol-bit-shift = <8>; | |
| 372 | anatop-vol-bit-width = <5>; | |
| 373 | anatop-min-bit-val = <0>; | |
| 374 | anatop-min-voltage = <2625000>; | |
| 375 | anatop-max-voltage = <3400000>; | |
| 376 | }; | |
| 377 | ||
| 378 | regulator-2p5@130 { | |
| 379 | compatible = "fsl,anatop-regulator"; | |
| 380 | regulator-name = "vdd2p5"; | |
| 381 | regulator-min-microvolt = <2000000>; | |
| 382 | regulator-max-microvolt = <2750000>; | |
| 383 | regulator-always-on; | |
| 384 | anatop-reg-offset = <0x130>; | |
| 385 | anatop-vol-bit-shift = <8>; | |
| 386 | anatop-vol-bit-width = <5>; | |
| 387 | anatop-min-bit-val = <0>; | |
| 388 | anatop-min-voltage = <2000000>; | |
| 389 | anatop-max-voltage = <2750000>; | |
| 390 | }; | |
| 391 | ||
| 392 | regulator-vddcore@140 { | |
| 393 | compatible = "fsl,anatop-regulator"; | |
| 394 | regulator-name = "cpu"; | |
| 395 | regulator-min-microvolt = <725000>; | |
| 396 | regulator-max-microvolt = <1450000>; | |
| 397 | regulator-always-on; | |
| 398 | anatop-reg-offset = <0x140>; | |
| 399 | anatop-vol-bit-shift = <0>; | |
| 400 | anatop-vol-bit-width = <5>; | |
| 401 | anatop-min-bit-val = <1>; | |
| 402 | anatop-min-voltage = <725000>; | |
| 403 | anatop-max-voltage = <1450000>; | |
| 404 | }; | |
| 405 | ||
| 406 | regulator-vddpu@140 { | |
| 407 | compatible = "fsl,anatop-regulator"; | |
| 408 | regulator-name = "vddpu"; | |
| 409 | regulator-min-microvolt = <725000>; | |
| 410 | regulator-max-microvolt = <1450000>; | |
| 411 | regulator-always-on; | |
| 412 | anatop-reg-offset = <0x140>; | |
| 413 | anatop-vol-bit-shift = <9>; | |
| 414 | anatop-vol-bit-width = <5>; | |
| 415 | anatop-min-bit-val = <1>; | |
| 416 | anatop-min-voltage = <725000>; | |
| 417 | anatop-max-voltage = <1450000>; | |
| 418 | }; | |
| 419 | ||
| 420 | regulator-vddsoc@140 { | |
| 421 | compatible = "fsl,anatop-regulator"; | |
| 422 | regulator-name = "vddsoc"; | |
| 423 | regulator-min-microvolt = <725000>; | |
| 424 | regulator-max-microvolt = <1450000>; | |
| 425 | regulator-always-on; | |
| 426 | anatop-reg-offset = <0x140>; | |
| 427 | anatop-vol-bit-shift = <18>; | |
| 428 | anatop-vol-bit-width = <5>; | |
| 429 | anatop-min-bit-val = <1>; | |
| 430 | anatop-min-voltage = <725000>; | |
| 431 | anatop-max-voltage = <1450000>; | |
| 432 | }; | |
| 7d740f87 SG |
433 | }; |
| 434 | ||
| 435 | usbphy@020c9000 { /* USBPHY1 */ | |
| 436 | reg = <0x020c9000 0x1000>; | |
| 437 | interrupts = <0 44 0x04>; | |
| 438 | }; | |
| 439 | ||
| 440 | usbphy@020ca000 { /* USBPHY2 */ | |
| 441 | reg = <0x020ca000 0x1000>; | |
| 442 | interrupts = <0 45 0x04>; | |
| 443 | }; | |
| 444 | ||
| 445 | snvs@020cc000 { | |
| 446 | reg = <0x020cc000 0x4000>; | |
| 447 | interrupts = <0 19 0x04 0 20 0x04>; | |
| 448 | }; | |
| 449 | ||
| 450 | epit@020d0000 { /* EPIT1 */ | |
| 451 | reg = <0x020d0000 0x4000>; | |
| 452 | interrupts = <0 56 0x04>; | |
| 453 | }; | |
| 454 | ||
| 455 | epit@020d4000 { /* EPIT2 */ | |
| 456 | reg = <0x020d4000 0x4000>; | |
| 457 | interrupts = <0 57 0x04>; | |
| 458 | }; | |
| 459 | ||
| 460 | src@020d8000 { | |
| 461 | compatible = "fsl,imx6q-src"; | |
| 462 | reg = <0x020d8000 0x4000>; | |
| 463 | interrupts = <0 91 0x04 0 96 0x04>; | |
| 464 | }; | |
| 465 | ||
| 466 | gpc@020dc000 { | |
| 467 | compatible = "fsl,imx6q-gpc"; | |
| 468 | reg = <0x020dc000 0x4000>; | |
| 469 | interrupts = <0 89 0x04 0 90 0x04>; | |
| 470 | }; | |
| 471 | ||
| 472 | iomuxc@020e0000 { | |
| 473 | reg = <0x020e0000 0x4000>; | |
| 474 | }; | |
| 475 | ||
| 476 | dcic@020e4000 { /* DCIC1 */ | |
| 477 | reg = <0x020e4000 0x4000>; | |
| 478 | interrupts = <0 124 0x04>; | |
| 479 | }; | |
| 480 | ||
| 481 | dcic@020e8000 { /* DCIC2 */ | |
| 482 | reg = <0x020e8000 0x4000>; | |
| 483 | interrupts = <0 125 0x04>; | |
| 484 | }; | |
| 485 | ||
| 486 | sdma@020ec000 { | |
| 487 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; | |
| 488 | reg = <0x020ec000 0x4000>; | |
| 489 | interrupts = <0 2 0x04>; | |
| 490 | }; | |
| 491 | }; | |
| 492 | ||
| 493 | aips-bus@02100000 { /* AIPS2 */ | |
| 494 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 495 | #address-cells = <1>; | |
| 496 | #size-cells = <1>; | |
| 497 | reg = <0x02100000 0x100000>; | |
| 498 | ranges; | |
| 499 | ||
| 500 | caam@02100000 { | |
| 501 | reg = <0x02100000 0x40000>; | |
| 502 | interrupts = <0 105 0x04 0 106 0x04>; | |
| 503 | }; | |
| 504 | ||
| 505 | aipstz@0217c000 { /* AIPSTZ2 */ | |
| 506 | reg = <0x0217c000 0x4000>; | |
| 507 | }; | |
| 508 | ||
| 509 | enet@02188000 { | |
| 510 | compatible = "fsl,imx6q-fec"; | |
| 511 | reg = <0x02188000 0x4000>; | |
| 512 | interrupts = <0 118 0x04 0 119 0x04>; | |
| 513 | status = "disabled"; | |
| 514 | }; | |
| 515 | ||
| 516 | mlb@0218c000 { | |
| 517 | reg = <0x0218c000 0x4000>; | |
| 518 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; | |
| 519 | }; | |
| 520 | ||
| 521 | usdhc@02190000 { /* uSDHC1 */ | |
| 522 | compatible = "fsl,imx6q-usdhc"; | |
| 523 | reg = <0x02190000 0x4000>; | |
| 524 | interrupts = <0 22 0x04>; | |
| 525 | status = "disabled"; | |
| 526 | }; | |
| 527 | ||
| 528 | usdhc@02194000 { /* uSDHC2 */ | |
| 529 | compatible = "fsl,imx6q-usdhc"; | |
| 530 | reg = <0x02194000 0x4000>; | |
| 531 | interrupts = <0 23 0x04>; | |
| 532 | status = "disabled"; | |
| 533 | }; | |
| 534 | ||
| 535 | usdhc@02198000 { /* uSDHC3 */ | |
| 536 | compatible = "fsl,imx6q-usdhc"; | |
| 537 | reg = <0x02198000 0x4000>; | |
| 538 | interrupts = <0 24 0x04>; | |
| 539 | status = "disabled"; | |
| 540 | }; | |
| 541 | ||
| 542 | usdhc@0219c000 { /* uSDHC4 */ | |
| 543 | compatible = "fsl,imx6q-usdhc"; | |
| 544 | reg = <0x0219c000 0x4000>; | |
| 545 | interrupts = <0 25 0x04>; | |
| 546 | status = "disabled"; | |
| 547 | }; | |
| 548 | ||
| 549 | i2c@021a0000 { /* I2C1 */ | |
| 550 | #address-cells = <1>; | |
| 551 | #size-cells = <0>; | |
| 552 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | |
| 553 | reg = <0x021a0000 0x4000>; | |
| 554 | interrupts = <0 36 0x04>; | |
| 555 | status = "disabled"; | |
| 556 | }; | |
| 557 | ||
| 558 | i2c@021a4000 { /* I2C2 */ | |
| 559 | #address-cells = <1>; | |
| 560 | #size-cells = <0>; | |
| 561 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | |
| 562 | reg = <0x021a4000 0x4000>; | |
| 563 | interrupts = <0 37 0x04>; | |
| 564 | status = "disabled"; | |
| 565 | }; | |
| 566 | ||
| 567 | i2c@021a8000 { /* I2C3 */ | |
| 568 | #address-cells = <1>; | |
| 569 | #size-cells = <0>; | |
| 570 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | |
| 571 | reg = <0x021a8000 0x4000>; | |
| 572 | interrupts = <0 38 0x04>; | |
| 573 | status = "disabled"; | |
| 574 | }; | |
| 575 | ||
| 576 | romcp@021ac000 { | |
| 577 | reg = <0x021ac000 0x4000>; | |
| 578 | }; | |
| 579 | ||
| 580 | mmdc@021b0000 { /* MMDC0 */ | |
| 581 | compatible = "fsl,imx6q-mmdc"; | |
| 582 | reg = <0x021b0000 0x4000>; | |
| 583 | }; | |
| 584 | ||
| 585 | mmdc@021b4000 { /* MMDC1 */ | |
| 586 | reg = <0x021b4000 0x4000>; | |
| 587 | }; | |
| 588 | ||
| 589 | weim@021b8000 { | |
| 590 | reg = <0x021b8000 0x4000>; | |
| 591 | interrupts = <0 14 0x04>; | |
| 592 | }; | |
| 593 | ||
| 594 | ocotp@021bc000 { | |
| 595 | reg = <0x021bc000 0x4000>; | |
| 596 | }; | |
| 597 | ||
| 598 | ocotp@021c0000 { | |
| 599 | reg = <0x021c0000 0x4000>; | |
| 600 | interrupts = <0 21 0x04>; | |
| 601 | }; | |
| 602 | ||
| 603 | tzasc@021d0000 { /* TZASC1 */ | |
| 604 | reg = <0x021d0000 0x4000>; | |
| 605 | interrupts = <0 108 0x04>; | |
| 606 | }; | |
| 607 | ||
| 608 | tzasc@021d4000 { /* TZASC2 */ | |
| 609 | reg = <0x021d4000 0x4000>; | |
| 610 | interrupts = <0 109 0x04>; | |
| 611 | }; | |
| 612 | ||
| 613 | audmux@021d8000 { | |
| 614 | reg = <0x021d8000 0x4000>; | |
| 615 | }; | |
| 616 | ||
| 617 | mipi@021dc000 { /* MIPI-CSI */ | |
| 618 | reg = <0x021dc000 0x4000>; | |
| 619 | }; | |
| 620 | ||
| 621 | mipi@021e0000 { /* MIPI-DSI */ | |
| 622 | reg = <0x021e0000 0x4000>; | |
| 623 | }; | |
| 624 | ||
| 625 | vdoa@021e4000 { | |
| 626 | reg = <0x021e4000 0x4000>; | |
| 627 | interrupts = <0 18 0x04>; | |
| 628 | }; | |
| 629 | ||
| 8f9ffecf | 630 | uart2: uart@021e8000 { |
| 7d740f87 SG |
631 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 632 | reg = <0x021e8000 0x4000>; | |
| 633 | interrupts = <0 27 0x04>; | |
| 634 | status = "disabled"; | |
| 635 | }; | |
| 636 | ||
| 8f9ffecf | 637 | uart3: uart@021ec000 { |
| 7d740f87 SG |
638 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 639 | reg = <0x021ec000 0x4000>; | |
| 640 | interrupts = <0 28 0x04>; | |
| 641 | status = "disabled"; | |
| 642 | }; | |
| 643 | ||
| 8f9ffecf | 644 | uart4: uart@021f0000 { |
| 7d740f87 SG |
645 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 646 | reg = <0x021f0000 0x4000>; | |
| 647 | interrupts = <0 29 0x04>; | |
| 648 | status = "disabled"; | |
| 649 | }; | |
| 650 | ||
| 8f9ffecf | 651 | uart5: uart@021f4000 { |
| 7d740f87 SG |
652 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 653 | reg = <0x021f4000 0x4000>; | |
| 654 | interrupts = <0 30 0x04>; | |
| 655 | status = "disabled"; | |
| 656 | }; | |
| 657 | }; | |
| 658 | }; | |
| 659 | }; |