projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: Add device tree entry for onewire master on i.MX53
[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
8f9ffecf
RZ		 17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
7d740f87
SG		 29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
d90df978
SG		 39 operating-points = <
40 /* kHz uV */
96574a6d
SG		 41 1200000 1275000
42 996000 1250000
43 792000 1150000
d90df978 44 396000 950000
d90df978
SG		 45 >;
46 clock-latency = <61036>; /* two CLK32 periods */
96574a6d
SG		 47 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
48 <&clks 17>, <&clks 170>;
49 clock-names = "arm", "pll2_pfd2_396m", "step",
50 "pll1_sw", "pll1_sys";
51 arm-supply = <&reg_arm>;
52 pu-supply = <&reg_pu>;
53 soc-supply = <&reg_soc>;
7d740f87
SG		 54 };
55
56 cpu@1 {
57 compatible = "arm,cortex-a9";
58 reg = <1>;
59 next-level-cache = <&L2>;
60 };
61
62 cpu@2 {
63 compatible = "arm,cortex-a9";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 };
67
68 cpu@3 {
69 compatible = "arm,cortex-a9";
70 reg = <3>;
71 next-level-cache = <&L2>;
72 };
73 };
74
75 intc: interrupt-controller@00a01000 {
76 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 interrupt-controller;
81 reg = <0x00a01000 0x1000>,
82 <0x00a00100 0x100>;
83 };
84
85 clocks {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 ckil {
90 compatible = "fsl,imx-ckil", "fixed-clock";
91 clock-frequency = <32768>;
92 };
93
94 ckih1 {
95 compatible = "fsl,imx-ckih1", "fixed-clock";
96 clock-frequency = <0>;
97 };
98
99 osc {
100 compatible = "fsl,imx-osc", "fixed-clock";
101 clock-frequency = <24000000>;
102 };
103 };
104
105 soc {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "simple-bus";
109 interrupt-parent = <&intc>;
110 ranges;
111
e5d0f9f5
HS		 112 dma-apbh@00110000 {
113 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
114 reg = <0x00110000 0x2000>;
0e87e043 115 clocks = <&clks 106>;
e5d0f9f5
HS		 116 };
117
be4ccfce 118 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 119 compatible = "fsl,imx6q-gpmi-nand";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
123 reg-names = "gpmi-nand", "bch";
124 interrupts = <0 13 0x04>, <0 15 0x04>;
125 interrupt-names = "gpmi-dma", "bch";
126 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
127 <&clks 150>, <&clks 149>;
128 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
129 "gpmi_bch_apb", "per1_bch";
130 fsl,gpmi-dma-channel = <0>;
131 status = "disabled";
cf922fa8
HS		 132 };
133
7d740f87 134 timer@00a00600 {
58458e03
MZ		 135 compatible = "arm,cortex-a9-twd-timer";
136 reg = <0x00a00600 0x20>;
137 interrupts = <1 13 0xf01>;
7d740f87
SG		 138 };
139
140 L2: l2-cache@00a02000 {
141 compatible = "arm,pl310-cache";
142 reg = <0x00a02000 0x1000>;
143 interrupts = <0 92 0x04>;
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 aips-bus@02000000 { /* AIPS1 */
149 compatible = "fsl,aips-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x02000000 0x100000>;
153 ranges;
154
155 spba-bus@02000000 {
156 compatible = "fsl,spba-bus", "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 reg = <0x02000000 0x40000>;
160 ranges;
161
7b7d6727 162 spdif: spdif@02004000 {
7d740f87
SG		 163 reg = <0x02004000 0x4000>;
164 interrupts = <0 52 0x04>;
165 };
166
7b7d6727 167 ecspi1: ecspi@02008000 {
7d740f87
SG		 168 #address-cells = <1>;
169 #size-cells = <0>;
170 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
171 reg = <0x02008000 0x4000>;
172 interrupts = <0 31 0x04>;
0e87e043
SG		 173 clocks = <&clks 112>, <&clks 112>;
174 clock-names = "ipg", "per";
7d740f87
SG		 175 status = "disabled";
176 };
177
7b7d6727 178 ecspi2: ecspi@0200c000 {
7d740f87
SG		 179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
182 reg = <0x0200c000 0x4000>;
183 interrupts = <0 32 0x04>;
0e87e043
SG		 184 clocks = <&clks 113>, <&clks 113>;
185 clock-names = "ipg", "per";
7d740f87
SG		 186 status = "disabled";
187 };
188
7b7d6727 189 ecspi3: ecspi@02010000 {
7d740f87
SG		 190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
193 reg = <0x02010000 0x4000>;
194 interrupts = <0 33 0x04>;
0e87e043
SG		 195 clocks = <&clks 114>, <&clks 114>;
196 clock-names = "ipg", "per";
7d740f87
SG		 197 status = "disabled";
198 };
199
7b7d6727 200 ecspi4: ecspi@02014000 {
7d740f87
SG		 201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
204 reg = <0x02014000 0x4000>;
205 interrupts = <0 34 0x04>;
0e87e043
SG		 206 clocks = <&clks 115>, <&clks 115>;
207 clock-names = "ipg", "per";
7d740f87
SG		 208 status = "disabled";
209 };
210
7b7d6727 211 ecspi5: ecspi@02018000 {
7d740f87
SG		 212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
215 reg = <0x02018000 0x4000>;
216 interrupts = <0 35 0x04>;
0e87e043
SG		 217 clocks = <&clks 116>, <&clks 116>;
218 clock-names = "ipg", "per";
7d740f87
SG		 219 status = "disabled";
220 };
221
0c456cfa 222 uart1: serial@02020000 {
7d740f87
SG		 223 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
224 reg = <0x02020000 0x4000>;
225 interrupts = <0 26 0x04>;
0e87e043
SG		 226 clocks = <&clks 160>, <&clks 161>;
227 clock-names = "ipg", "per";
7d740f87
SG		 228 status = "disabled";
229 };
230
7b7d6727 231 esai: esai@02024000 {
7d740f87
SG		 232 reg = <0x02024000 0x4000>;
233 interrupts = <0 51 0x04>;
234 };
235
b1a5da8e
RZ		 236 ssi1: ssi@02028000 {
237 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 238 reg = <0x02028000 0x4000>;
239 interrupts = <0 46 0x04>;
0e87e043 240 clocks = <&clks 178>;
b1a5da8e
RZ		 241 fsl,fifo-depth = <15>;
242 fsl,ssi-dma-events = <38 37>;
243 status = "disabled";
7d740f87
SG		 244 };
245
b1a5da8e
RZ		 246 ssi2: ssi@0202c000 {
247 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 248 reg = <0x0202c000 0x4000>;
249 interrupts = <0 47 0x04>;
0e87e043 250 clocks = <&clks 179>;
b1a5da8e
RZ		 251 fsl,fifo-depth = <15>;
252 fsl,ssi-dma-events = <42 41>;
253 status = "disabled";
7d740f87
SG		 254 };
255
b1a5da8e
RZ		 256 ssi3: ssi@02030000 {
257 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 258 reg = <0x02030000 0x4000>;
259 interrupts = <0 48 0x04>;
0e87e043 260 clocks = <&clks 180>;
b1a5da8e
RZ		 261 fsl,fifo-depth = <15>;
262 fsl,ssi-dma-events = <46 45>;
263 status = "disabled";
7d740f87
SG		 264 };
265
7b7d6727 266 asrc: asrc@02034000 {
7d740f87
SG		 267 reg = <0x02034000 0x4000>;
268 interrupts = <0 50 0x04>;
269 };
270
271 spba@0203c000 {
272 reg = <0x0203c000 0x4000>;
273 };
274 };
275
7b7d6727 276 vpu: vpu@02040000 {
7d740f87
SG		 277 reg = <0x02040000 0x3c000>;
278 interrupts = <0 3 0x04 0 12 0x04>;
279 };
280
281 aipstz@0207c000 { /* AIPSTZ1 */
282 reg = <0x0207c000 0x4000>;
283 };
284
7b7d6727 285 pwm1: pwm@02080000 {
33b38587
SH		 286 #pwm-cells = <2>;
287 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 288 reg = <0x02080000 0x4000>;
289 interrupts = <0 83 0x04>;
33b38587
SH		 290 clocks = <&clks 62>, <&clks 145>;
291 clock-names = "ipg", "per";
7d740f87
SG		 292 };
293
7b7d6727 294 pwm2: pwm@02084000 {
33b38587
SH		 295 #pwm-cells = <2>;
296 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 297 reg = <0x02084000 0x4000>;
298 interrupts = <0 84 0x04>;
33b38587
SH		 299 clocks = <&clks 62>, <&clks 146>;
300 clock-names = "ipg", "per";
7d740f87
SG		 301 };
302
7b7d6727 303 pwm3: pwm@02088000 {
33b38587
SH		 304 #pwm-cells = <2>;
305 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 306 reg = <0x02088000 0x4000>;
307 interrupts = <0 85 0x04>;
33b38587
SH		 308 clocks = <&clks 62>, <&clks 147>;
309 clock-names = "ipg", "per";
7d740f87
SG		 310 };
311
7b7d6727 312 pwm4: pwm@0208c000 {
33b38587
SH		 313 #pwm-cells = <2>;
314 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 315 reg = <0x0208c000 0x4000>;
316 interrupts = <0 86 0x04>;
33b38587
SH		 317 clocks = <&clks 62>, <&clks 148>;
318 clock-names = "ipg", "per";
7d740f87
SG		 319 };
320
7b7d6727 321 can1: flexcan@02090000 {
7d740f87
SG		 322 reg = <0x02090000 0x4000>;
323 interrupts = <0 110 0x04>;
324 };
325
7b7d6727 326 can2: flexcan@02094000 {
7d740f87
SG		 327 reg = <0x02094000 0x4000>;
328 interrupts = <0 111 0x04>;
329 };
330
7b7d6727 331 gpt: gpt@02098000 {
7d740f87
SG		 332 compatible = "fsl,imx6q-gpt";
333 reg = <0x02098000 0x4000>;
334 interrupts = <0 55 0x04>;
335 };
336
4d191868 337 gpio1: gpio@0209c000 {
aeb27748 338 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 339 reg = <0x0209c000 0x4000>;
340 interrupts = <0 66 0x04 0 67 0x04>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
88cde8b7 344 #interrupt-cells = <2>;
7d740f87
SG		 345 };
346
4d191868 347 gpio2: gpio@020a0000 {
aeb27748 348 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 349 reg = <0x020a0000 0x4000>;
350 interrupts = <0 68 0x04 0 69 0x04>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
88cde8b7 354 #interrupt-cells = <2>;
7d740f87
SG		 355 };
356
4d191868 357 gpio3: gpio@020a4000 {
aeb27748 358 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 359 reg = <0x020a4000 0x4000>;
360 interrupts = <0 70 0x04 0 71 0x04>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
88cde8b7 364 #interrupt-cells = <2>;
7d740f87
SG		 365 };
366
4d191868 367 gpio4: gpio@020a8000 {
aeb27748 368 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 369 reg = <0x020a8000 0x4000>;
370 interrupts = <0 72 0x04 0 73 0x04>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
88cde8b7 374 #interrupt-cells = <2>;
7d740f87
SG		 375 };
376
4d191868 377 gpio5: gpio@020ac000 {
aeb27748 378 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 379 reg = <0x020ac000 0x4000>;
380 interrupts = <0 74 0x04 0 75 0x04>;
381 gpio-controller;
382 #gpio-cells = <2>;
383 interrupt-controller;
88cde8b7 384 #interrupt-cells = <2>;
7d740f87
SG		 385 };
386
4d191868 387 gpio6: gpio@020b0000 {
aeb27748 388 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 389 reg = <0x020b0000 0x4000>;
390 interrupts = <0 76 0x04 0 77 0x04>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
88cde8b7 394 #interrupt-cells = <2>;
7d740f87
SG		 395 };
396
4d191868 397 gpio7: gpio@020b4000 {
aeb27748 398 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 399 reg = <0x020b4000 0x4000>;
400 interrupts = <0 78 0x04 0 79 0x04>;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
88cde8b7 404 #interrupt-cells = <2>;
7d740f87
SG		 405 };
406
7b7d6727 407 kpp: kpp@020b8000 {
7d740f87
SG		 408 reg = <0x020b8000 0x4000>;
409 interrupts = <0 82 0x04>;
410 };
411
7b7d6727 412 wdog1: wdog@020bc000 {
7d740f87
SG		 413 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
414 reg = <0x020bc000 0x4000>;
415 interrupts = <0 80 0x04>;
0e87e043 416 clocks = <&clks 0>;
7d740f87
SG		 417 };
418
7b7d6727 419 wdog2: wdog@020c0000 {
7d740f87
SG		 420 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
421 reg = <0x020c0000 0x4000>;
422 interrupts = <0 81 0x04>;
0e87e043 423 clocks = <&clks 0>;
7d740f87
SG		 424 status = "disabled";
425 };
426
0e87e043 427 clks: ccm@020c4000 {
7d740f87
SG		 428 compatible = "fsl,imx6q-ccm";
429 reg = <0x020c4000 0x4000>;
430 interrupts = <0 87 0x04 0 88 0x04>;
0e87e043 431 #clock-cells = <1>;
7d740f87
SG		 432 };
433
baa64151
DA		 434 anatop: anatop@020c8000 {
435 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87
SG		 436 reg = <0x020c8000 0x1000>;
437 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
a1e327e6
YCLP		 438
439 regulator-1p1@110 {
440 compatible = "fsl,anatop-regulator";
441 regulator-name = "vdd1p1";
442 regulator-min-microvolt = <800000>;
443 regulator-max-microvolt = <1375000>;
444 regulator-always-on;
445 anatop-reg-offset = <0x110>;
446 anatop-vol-bit-shift = <8>;
447 anatop-vol-bit-width = <5>;
448 anatop-min-bit-val = <4>;
449 anatop-min-voltage = <800000>;
450 anatop-max-voltage = <1375000>;
451 };
452
453 regulator-3p0@120 {
454 compatible = "fsl,anatop-regulator";
455 regulator-name = "vdd3p0";
456 regulator-min-microvolt = <2800000>;
457 regulator-max-microvolt = <3150000>;
458 regulator-always-on;
459 anatop-reg-offset = <0x120>;
460 anatop-vol-bit-shift = <8>;
461 anatop-vol-bit-width = <5>;
462 anatop-min-bit-val = <0>;
463 anatop-min-voltage = <2625000>;
464 anatop-max-voltage = <3400000>;
465 };
466
467 regulator-2p5@130 {
468 compatible = "fsl,anatop-regulator";
469 regulator-name = "vdd2p5";
470 regulator-min-microvolt = <2000000>;
471 regulator-max-microvolt = <2750000>;
472 regulator-always-on;
473 anatop-reg-offset = <0x130>;
474 anatop-vol-bit-shift = <8>;
475 anatop-vol-bit-width = <5>;
476 anatop-min-bit-val = <0>;
477 anatop-min-voltage = <2000000>;
478 anatop-max-voltage = <2750000>;
479 };
480
96574a6d 481 reg_arm: regulator-vddcore@140 {
a1e327e6
YCLP		 482 compatible = "fsl,anatop-regulator";
483 regulator-name = "cpu";
484 regulator-min-microvolt = <725000>;
485 regulator-max-microvolt = <1450000>;
486 regulator-always-on;
487 anatop-reg-offset = <0x140>;
488 anatop-vol-bit-shift = <0>;
489 anatop-vol-bit-width = <5>;
490 anatop-min-bit-val = <1>;
491 anatop-min-voltage = <725000>;
492 anatop-max-voltage = <1450000>;
493 };
494
96574a6d 495 reg_pu: regulator-vddpu@140 {
a1e327e6
YCLP		 496 compatible = "fsl,anatop-regulator";
497 regulator-name = "vddpu";
498 regulator-min-microvolt = <725000>;
499 regulator-max-microvolt = <1450000>;
500 regulator-always-on;
501 anatop-reg-offset = <0x140>;
502 anatop-vol-bit-shift = <9>;
503 anatop-vol-bit-width = <5>;
504 anatop-min-bit-val = <1>;
505 anatop-min-voltage = <725000>;
506 anatop-max-voltage = <1450000>;
507 };
508
96574a6d 509 reg_soc: regulator-vddsoc@140 {
a1e327e6
YCLP		 510 compatible = "fsl,anatop-regulator";
511 regulator-name = "vddsoc";
512 regulator-min-microvolt = <725000>;
513 regulator-max-microvolt = <1450000>;
514 regulator-always-on;
515 anatop-reg-offset = <0x140>;
516 anatop-vol-bit-shift = <18>;
517 anatop-vol-bit-width = <5>;
518 anatop-min-bit-val = <1>;
519 anatop-min-voltage = <725000>;
520 anatop-max-voltage = <1450000>;
521 };
7d740f87
SG		 522 };
523
74bd88f7
RZ		 524 usbphy1: usbphy@020c9000 {
525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 526 reg = <0x020c9000 0x1000>;
527 interrupts = <0 44 0x04>;
0e87e043 528 clocks = <&clks 182>;
7d740f87
SG		 529 };
530
74bd88f7
RZ		 531 usbphy2: usbphy@020ca000 {
532 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 533 reg = <0x020ca000 0x1000>;
534 interrupts = <0 45 0x04>;
0e87e043 535 clocks = <&clks 183>;
7d740f87
SG		 536 };
537
538 snvs@020cc000 {
c9250388
SG		 539 compatible = "fsl,sec-v4.0-mon", "simple-bus";
540 #address-cells = <1>;
541 #size-cells = <1>;
542 ranges = <0 0x020cc000 0x4000>;
543
544 snvs-rtc-lp@34 {
545 compatible = "fsl,sec-v4.0-mon-rtc-lp";
546 reg = <0x34 0x58>;
547 interrupts = <0 19 0x04 0 20 0x04>;
548 };
7d740f87
SG		 549 };
550
7b7d6727 551 epit1: epit@020d0000 { /* EPIT1 */
7d740f87
SG		 552 reg = <0x020d0000 0x4000>;
553 interrupts = <0 56 0x04>;
554 };
555
7b7d6727 556 epit2: epit@020d4000 { /* EPIT2 */
7d740f87
SG		 557 reg = <0x020d4000 0x4000>;
558 interrupts = <0 57 0x04>;
559 };
560
7b7d6727 561 src: src@020d8000 {
7d740f87
SG		 562 compatible = "fsl,imx6q-src";
563 reg = <0x020d8000 0x4000>;
564 interrupts = <0 91 0x04 0 96 0x04>;
565 };
566
7b7d6727 567 gpc: gpc@020dc000 {
7d740f87
SG		 568 compatible = "fsl,imx6q-gpc";
569 reg = <0x020dc000 0x4000>;
570 interrupts = <0 89 0x04 0 90 0x04>;
571 };
572
df37e0c0
DA		 573 gpr: iomuxc-gpr@020e0000 {
574 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
575 reg = <0x020e0000 0x38>;
576 };
577
7b7d6727 578 iomuxc: iomuxc@020e0000 {
551fd208 579 compatible = "fsl,imx6q-iomuxc";
7d740f87 580 reg = <0x020e0000 0x4000>;
551fd208
DA		 581
582 /* shared pinctrl settings */
5ca65c18
RZ		 583 audmux {
584 pinctrl_audmux_1: audmux-1 {
44a509fc
SG		 585 fsl,pins = <
586 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
587 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
588 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
589 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
590 >;
5ca65c18
RZ		 591 };
592 };
593
52ccd492
SG		 594 ecspi1 {
595 pinctrl_ecspi1_1: ecspi1grp-1 {
596 fsl,pins = <
597 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
598 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
599 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
600 >;
601 };
602 };
603
99d5f0cc
SG		 604 enet {
605 pinctrl_enet_1: enetgrp-1 {
606 fsl,pins = <
607 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
608 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
609 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
610 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
611 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
612 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
613 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
614 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
615 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
616 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
617 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
618 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
619 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
620 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
621 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
7629838c 622 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
99d5f0cc
SG		 623 >;
624 };
9e3c0066
SG		 625
626 pinctrl_enet_2: enetgrp-2 {
627 fsl,pins = <
628 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
629 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
630 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
631 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
632 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
633 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
634 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
635 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
636 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
637 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
638 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
639 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
640 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
641 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
642 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
643 >;
644 };
99d5f0cc
SG		 645 };
646
cf922fa8
HS		 647 gpmi-nand {
648 pinctrl_gpmi_nand_1: gpmi-nand-1 {
44a509fc
SG		 649 fsl,pins = <
650 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
651 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
652 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
653 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
654 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
655 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
656 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
657 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
658 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
659 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
660 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
661 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
662 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
663 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
664 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
665 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
666 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
667 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
668 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
669 >;
cf922fa8
HS		 670 };
671 };
672
d99a79fc
RZ		 673 i2c1 {
674 pinctrl_i2c1_1: i2c1grp-1 {
44a509fc
SG		 675 fsl,pins = <
676 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
677 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
678 >;
d99a79fc
RZ		 679 };
680 };
681
497ae174
SG		 682 uart1 {
683 pinctrl_uart1_1: uart1grp-1 {
684 fsl,pins = <
685 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
686 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
687 >;
688 };
689 };
690
e30ba89f
SG		 691 uart2 {
692 pinctrl_uart2_1: uart2grp-1 {
44a509fc
SG		 693 fsl,pins = <
694 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
695 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
696 >;
c3001b2a
RZ		 697 };
698 };
699
9e3c0066
SG		 700 uart4 {
701 pinctrl_uart4_1: uart4grp-1 {
702 fsl,pins = <
703 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
704 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
705 >;
706 };
707 };
708
97a53092
RZ		 709 usbotg {
710 pinctrl_usbotg_1: usbotggrp-1 {
711 fsl,pins = <
712 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
713 >;
714 };
715 };
716
497ae174
SG		 717 usdhc2 {
718 pinctrl_usdhc2_1: usdhc2grp-1 {
719 fsl,pins = <
720 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
721 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
722 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
723 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
724 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
725 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
726 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
727 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
728 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
729 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
730 >;
731 };
732 };
733
551fd208
DA		 734 usdhc3 {
735 pinctrl_usdhc3_1: usdhc3grp-1 {
44a509fc
SG		 736 fsl,pins = <
737 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
738 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
739 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
740 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
741 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
742 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
743 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
744 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
745 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
746 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
747 >;
551fd208 748 };
99d5f0cc
SG		 749
750 pinctrl_usdhc3_2: usdhc3grp-2 {
751 fsl,pins = <
752 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
753 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
754 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
755 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
756 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
757 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
758 >;
759 };
551fd208
DA		 760 };
761
762 usdhc4 {
763 pinctrl_usdhc4_1: usdhc4grp-1 {
44a509fc
SG		 764 fsl,pins = <
765 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
766 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
767 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
768 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
769 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
770 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
771 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
772 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
773 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
774 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
775 >;
551fd208 776 };
99d5f0cc
SG		 777
778 pinctrl_usdhc4_2: usdhc4grp-2 {
779 fsl,pins = <
780 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
781 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
782 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
783 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
784 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
785 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
786 >;
787 };
551fd208 788 };
7d740f87
SG		 789 };
790
7b7d6727 791 dcic1: dcic@020e4000 {
7d740f87
SG		 792 reg = <0x020e4000 0x4000>;
793 interrupts = <0 124 0x04>;
794 };
795
7b7d6727 796 dcic2: dcic@020e8000 {
7d740f87
SG		 797 reg = <0x020e8000 0x4000>;
798 interrupts = <0 125 0x04>;
799 };
800
7b7d6727 801 sdma: sdma@020ec000 {
7d740f87
SG		 802 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
803 reg = <0x020ec000 0x4000>;
804 interrupts = <0 2 0x04>;
0e87e043
SG		 805 clocks = <&clks 155>, <&clks 155>;
806 clock-names = "ipg", "ahb";
d6b9c591 807 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 808 };
809 };
810
811 aips-bus@02100000 { /* AIPS2 */
812 compatible = "fsl,aips-bus", "simple-bus";
813 #address-cells = <1>;
814 #size-cells = <1>;
815 reg = <0x02100000 0x100000>;
816 ranges;
817
818 caam@02100000 {
819 reg = <0x02100000 0x40000>;
820 interrupts = <0 105 0x04 0 106 0x04>;
821 };
822
823 aipstz@0217c000 { /* AIPSTZ2 */
824 reg = <0x0217c000 0x4000>;
825 };
826
7b7d6727 827 usbotg: usb@02184000 {
74bd88f7
RZ		 828 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
829 reg = <0x02184000 0x200>;
830 interrupts = <0 43 0x04>;
0e87e043 831 clocks = <&clks 162>;
74bd88f7 832 fsl,usbphy = <&usbphy1>;
28342c61 833 fsl,usbmisc = <&usbmisc 0>;
74bd88f7
RZ		 834 status = "disabled";
835 };
836
7b7d6727 837 usbh1: usb@02184200 {
74bd88f7
RZ		 838 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
839 reg = <0x02184200 0x200>;
840 interrupts = <0 40 0x04>;
0e87e043 841 clocks = <&clks 162>;
74bd88f7 842 fsl,usbphy = <&usbphy2>;
28342c61 843 fsl,usbmisc = <&usbmisc 1>;
74bd88f7
RZ		 844 status = "disabled";
845 };
846
7b7d6727 847 usbh2: usb@02184400 {
74bd88f7
RZ		 848 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
849 reg = <0x02184400 0x200>;
850 interrupts = <0 41 0x04>;
0e87e043 851 clocks = <&clks 162>;
28342c61 852 fsl,usbmisc = <&usbmisc 2>;
74bd88f7
RZ		 853 status = "disabled";
854 };
855
7b7d6727 856 usbh3: usb@02184600 {
74bd88f7
RZ		 857 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
858 reg = <0x02184600 0x200>;
859 interrupts = <0 42 0x04>;
0e87e043 860 clocks = <&clks 162>;
28342c61 861 fsl,usbmisc = <&usbmisc 3>;
74bd88f7
RZ		 862 status = "disabled";
863 };
864
7b7d6727 865 usbmisc: usbmisc: usbmisc@02184800 {
28342c61
RZ		 866 #index-cells = <1>;
867 compatible = "fsl,imx6q-usbmisc";
868 reg = <0x02184800 0x200>;
869 clocks = <&clks 162>;
870 };
871
7b7d6727 872 fec: ethernet@02188000 {
7d740f87
SG		 873 compatible = "fsl,imx6q-fec";
874 reg = <0x02188000 0x4000>;
875 interrupts = <0 118 0x04 0 119 0x04>;
8dd5c66b 876 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
7629838c 877 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 878 status = "disabled";
879 };
880
881 mlb@0218c000 {
882 reg = <0x0218c000 0x4000>;
883 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
884 };
885
7b7d6727 886 usdhc1: usdhc@02190000 {
7d740f87
SG		 887 compatible = "fsl,imx6q-usdhc";
888 reg = <0x02190000 0x4000>;
889 interrupts = <0 22 0x04>;
0e87e043
SG		 890 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
891 clock-names = "ipg", "ahb", "per";
c104b6a2 892 bus-width = <4>;
7d740f87
SG		 893 status = "disabled";
894 };
895
7b7d6727 896 usdhc2: usdhc@02194000 {
7d740f87
SG		 897 compatible = "fsl,imx6q-usdhc";
898 reg = <0x02194000 0x4000>;
899 interrupts = <0 23 0x04>;
0e87e043
SG		 900 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
901 clock-names = "ipg", "ahb", "per";
c104b6a2 902 bus-width = <4>;
7d740f87
SG		 903 status = "disabled";
904 };
905
7b7d6727 906 usdhc3: usdhc@02198000 {
7d740f87
SG		 907 compatible = "fsl,imx6q-usdhc";
908 reg = <0x02198000 0x4000>;
909 interrupts = <0 24 0x04>;
0e87e043
SG		 910 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
911 clock-names = "ipg", "ahb", "per";
c104b6a2 912 bus-width = <4>;
7d740f87
SG		 913 status = "disabled";
914 };
915
7b7d6727 916 usdhc4: usdhc@0219c000 {
7d740f87
SG		 917 compatible = "fsl,imx6q-usdhc";
918 reg = <0x0219c000 0x4000>;
919 interrupts = <0 25 0x04>;
0e87e043
SG		 920 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
921 clock-names = "ipg", "ahb", "per";
c104b6a2 922 bus-width = <4>;
7d740f87
SG		 923 status = "disabled";
924 };
925
7b7d6727 926 i2c1: i2c@021a0000 {
7d740f87
SG		 927 #address-cells = <1>;
928 #size-cells = <0>;
5bdfba29 929 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 930 reg = <0x021a0000 0x4000>;
931 interrupts = <0 36 0x04>;
0e87e043 932 clocks = <&clks 125>;
7d740f87
SG		 933 status = "disabled";
934 };
935
7b7d6727 936 i2c2: i2c@021a4000 {
7d740f87
SG		 937 #address-cells = <1>;
938 #size-cells = <0>;
5bdfba29 939 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 940 reg = <0x021a4000 0x4000>;
941 interrupts = <0 37 0x04>;
0e87e043 942 clocks = <&clks 126>;
7d740f87
SG		 943 status = "disabled";
944 };
945
7b7d6727 946 i2c3: i2c@021a8000 {
7d740f87
SG		 947 #address-cells = <1>;
948 #size-cells = <0>;
5bdfba29 949 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 950 reg = <0x021a8000 0x4000>;
951 interrupts = <0 38 0x04>;
0e87e043 952 clocks = <&clks 127>;
7d740f87
SG		 953 status = "disabled";
954 };
955
956 romcp@021ac000 {
957 reg = <0x021ac000 0x4000>;
958 };
959
7b7d6727 960 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 961 compatible = "fsl,imx6q-mmdc";
962 reg = <0x021b0000 0x4000>;
963 };
964
7b7d6727 965 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 966 reg = <0x021b4000 0x4000>;
967 };
968
969 weim@021b8000 {
970 reg = <0x021b8000 0x4000>;
971 interrupts = <0 14 0x04>;
972 };
973
974 ocotp@021bc000 {
96574a6d 975 compatible = "fsl,imx6q-ocotp";
7d740f87
SG		 976 reg = <0x021bc000 0x4000>;
977 };
978
979 ocotp@021c0000 {
980 reg = <0x021c0000 0x4000>;
981 interrupts = <0 21 0x04>;
982 };
983
984 tzasc@021d0000 { /* TZASC1 */
985 reg = <0x021d0000 0x4000>;
986 interrupts = <0 108 0x04>;
987 };
988
989 tzasc@021d4000 { /* TZASC2 */
990 reg = <0x021d4000 0x4000>;
991 interrupts = <0 109 0x04>;
992 };
993
7b7d6727 994 audmux: audmux@021d8000 {
f965cd55 995 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 996 reg = <0x021d8000 0x4000>;
f965cd55 997 status = "disabled";
7d740f87
SG		 998 };
999
1000 mipi@021dc000 { /* MIPI-CSI */
1001 reg = <0x021dc000 0x4000>;
1002 };
1003
1004 mipi@021e0000 { /* MIPI-DSI */
1005 reg = <0x021e0000 0x4000>;
1006 };
1007
1008 vdoa@021e4000 {
1009 reg = <0x021e4000 0x4000>;
1010 interrupts = <0 18 0x04>;
1011 };
1012
0c456cfa 1013 uart2: serial@021e8000 {
7d740f87
SG		 1014 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1015 reg = <0x021e8000 0x4000>;
1016 interrupts = <0 27 0x04>;
0e87e043
SG		 1017 clocks = <&clks 160>, <&clks 161>;
1018 clock-names = "ipg", "per";
7d740f87
SG		 1019 status = "disabled";
1020 };
1021
0c456cfa 1022 uart3: serial@021ec000 {
7d740f87
SG		 1023 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1024 reg = <0x021ec000 0x4000>;
1025 interrupts = <0 28 0x04>;
0e87e043
SG		 1026 clocks = <&clks 160>, <&clks 161>;
1027 clock-names = "ipg", "per";
7d740f87
SG		 1028 status = "disabled";
1029 };
1030
0c456cfa 1031 uart4: serial@021f0000 {
7d740f87
SG		 1032 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1033 reg = <0x021f0000 0x4000>;
1034 interrupts = <0 29 0x04>;
0e87e043
SG		 1035 clocks = <&clks 160>, <&clks 161>;
1036 clock-names = "ipg", "per";
7d740f87
SG		 1037 status = "disabled";
1038 };
1039
0c456cfa 1040 uart5: serial@021f4000 {
7d740f87
SG		 1041 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1042 reg = <0x021f4000 0x4000>;
1043 interrupts = <0 30 0x04>;
0e87e043
SG		 1044 clocks = <&clks 160>, <&clks 161>;
1045 clock-names = "ipg", "per";
7d740f87
SG		 1046 status = "disabled";
1047 };
1048 };
91660d74
SH		 1049
1050 ipu1: ipu@02400000 {
1051 #crtc-cells = <1>;
1052 compatible = "fsl,imx6q-ipu";
1053 reg = <0x02400000 0x400000>;
1054 interrupts = <0 6 0x4 0 5 0x4>;
1055 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1056 clock-names = "bus", "di0", "di1";
1057 };
1058
1059 ipu2: ipu@02800000 {
1060 #crtc-cells = <1>;
1061 compatible = "fsl,imx6q-ipu";
1062 reg = <0x02800000 0x400000>;
1063 interrupts = <0 8 0x4 0 7 0x4>;
1064 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1065 clock-names = "bus", "di0", "di1";
1066 };
7d740f87
SG		 1067 };
1068};
Linux kernel - Deliverables
This page took 0.129256 seconds and 5 git commands to generate.