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ARM: dts: imx: ventana: remove unsupported dt nodes
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl-gw51xx.dtsi
CommitLineData
e3946fe8
TH		 1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 led0 = &led0;
18 led1 = &led1;
19 nand = &gpmi;
20 usb0 = &usbh1;
21 usb1 = &usbotg;
22 };
23
24 chosen {
25 bootargs = "console=ttymxc1,115200";
26 };
27
28 leds {
29 compatible = "gpio-leds";
30
31 led0: user1 {
32 label = "user1";
33 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
34 default-state = "on";
35 linux,default-trigger = "heartbeat";
36 };
37
38 led1: user2 {
39 label = "user2";
40 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
41 default-state = "off";
42 };
43 };
44
45 memory {
46 reg = <0x10000000 0x20000000>;
47 };
48
49 pps {
50 compatible = "pps-gpio";
51 gpios = <&gpio1 26 0>;
52 status = "okay";
53 };
54
55 regulators {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 reg_3p3v: regulator@0 {
61 compatible = "regulator-fixed";
62 reg = <0>;
63 regulator-name = "3P3V";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 regulator-always-on;
67 };
68
69 reg_5p0v: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 regulator-name = "5P0V";
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 regulator-always-on;
76 };
77
78 reg_usb_otg_vbus: regulator@2 {
79 compatible = "regulator-fixed";
80 reg = <2>;
81 regulator-name = "usb_otg_vbus";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
84 gpio = <&gpio3 22 0>;
85 enable-active-high;
86 };
87 };
88};
89
90&fec {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_enet>;
93 phy-mode = "rgmii";
94 phy-reset-gpios = <&gpio1 30 0>;
95 status = "okay";
96};
97
98&gpmi {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gpmi_nand>;
101 status = "okay";
102};
103
aef15dba
TH		 104&hdmi {
105 ddc-i2c-bus = <&i2c3>;
106 status = "okay";
107};
108
e3946fe8
TH		 109&i2c1 {
110 clock-frequency = <100000>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c1>;
113 status = "okay";
114
115 eeprom1: eeprom@50 {
116 compatible = "atmel,24c02";
117 reg = <0x50>;
118 pagesize = <16>;
119 };
120
121 eeprom2: eeprom@51 {
122 compatible = "atmel,24c02";
123 reg = <0x51>;
124 pagesize = <16>;
125 };
126
127 eeprom3: eeprom@52 {
128 compatible = "atmel,24c02";
129 reg = <0x52>;
130 pagesize = <16>;
131 };
132
133 eeprom4: eeprom@53 {
134 compatible = "atmel,24c02";
135 reg = <0x53>;
136 pagesize = <16>;
137 };
138
139 gpio: pca9555@23 {
140 compatible = "nxp,pca9555";
141 reg = <0x23>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
e3946fe8
TH		 146 rtc: ds1672@68 {
147 compatible = "dallas,ds1672";
148 reg = <0x68>;
149 };
150};
151
152&i2c2 {
153 clock-frequency = <100000>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c2>;
156 status = "okay";
e3946fe8
TH		 157};
158
159&i2c3 {
160 clock-frequency = <100000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_i2c3>;
163 status = "okay";
e3946fe8
TH		 164};
165
166&iomuxc {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_hog>;
169
170 imx6qdl-gw51xx {
171 pinctrl_hog: hoggrp {
172 fsl,pins = <
173 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */
174 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */
175 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
176 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
177 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
178 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */
179 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
180 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
181 >;
182 };
183
184 pinctrl_enet: enetgrp {
185 fsl,pins = <
186 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
187 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
188 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
189 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
190 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
191 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
192 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
193 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
194 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
195 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
196 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
197 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
198 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
199 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
200 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
201 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
202 >;
203 };
204
205 pinctrl_gpmi_nand: gpminandgrp {
206 fsl,pins = <
207 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
208 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
209 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
210 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
211 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
212 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
213 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
214 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
215 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
216 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
217 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
218 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
219 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
220 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
221 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
222 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
223 >;
224 };
225
226 pinctrl_i2c1: i2c1grp {
227 fsl,pins = <
228 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
229 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
230 >;
231 };
232
233 pinctrl_i2c2: i2c2grp {
234 fsl,pins = <
235 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
236 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
237 >;
238 };
239
240 pinctrl_i2c3: i2c3grp {
241 fsl,pins = <
242 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
243 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
244 >;
245 };
246
247 pinctrl_uart1: uart1grp {
248 fsl,pins = <
249 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
250 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
251 >;
252 };
253
254 pinctrl_uart2: uart2grp {
255 fsl,pins = <
256 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
257 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
258 >;
259 };
260
261 pinctrl_uart3: uart3grp {
262 fsl,pins = <
263 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
264 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
265 >;
266 };
267
268 pinctrl_uart5: uart5grp {
269 fsl,pins = <
270 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
271 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
272 >;
273 };
274
275 pinctrl_usbotg: usbotggrp {
276 fsl,pins = <
277 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
278 >;
279 };
280 };
281};
282
283&pcie {
284 reset-gpio = <&gpio1 0 0>;
285 status = "okay";
286};
287
288&uart1 {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart1>;
291 status = "okay";
292};
293
294&uart2 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart2>;
297 status = "okay";
298};
299
300&uart3 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart3>;
303 status = "okay";
304};
305
306&uart5 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart5>;
309 status = "okay";
310};
311
312&usbotg {
313 vbus-supply = <&reg_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usbotg>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usbh1 {
321 status = "okay";
322};
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