[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl-sabreauto.dtsi

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	memory {
		reg = <0x10000000 0x80000000>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		user {
			label = "debug";
			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
		};
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif",
			   "fsl,imx-sabreauto-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-in;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		status = "okay";
	};
};

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio3 19 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	status = "disabled"; /* pin conflict with WEIM NOR */

	flash: m25p80@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p32";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
};

&hdmi {
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic: pfuze100@08 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	max7310_a: gpio@30 {
		compatible = "maxim,max7310";
		reg = <0x30>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	max7310_b: gpio@32 {
		compatible = "maxim,max7310";
		reg = <0x32>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	max7310_c: gpio@34 {
		compatible = "maxim,max7310";
		reg = <0x34>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6qdl-sabreauto {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
			>;
		};

		pinctrl_ecspi1_cs: ecspi1cs {
			fsl,pins = <
				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
			>;
		};

		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x80000000
			>;
		};

		pinctrl_gpmi_nand: gpminandgrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
				MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
			>;
		};

		pinctrl_pwm3: pwm1grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
			>;
		};

		pinctrl_uart4: uart4grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
			>;
		};

		pinctrl_weim_cs0: weimcs0grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
			>;
		};

		pinctrl_weim_nor: weimnorgrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
				MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
				MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
				MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
				MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
				MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
				MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
				MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
				MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
				MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
				MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
				MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
				MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
				MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
				MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
				MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
				MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
				MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
				MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
				MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
				MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
				MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
				MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
				MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
				MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
				MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
				MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
				MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
				MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
				MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
				MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
				MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
				MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
				MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
				MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
				MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
				MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
				MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
				MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
				MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
				MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
				MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
			>;
		};
	};
};

&ldb {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio6 15 0>;
	wp-gpios = <&gpio1 13 0>;
	status = "okay";
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x08000000 0x08000000>;
	status = "disabled"; /* pin conflict with SPI NOR */

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0 0 0x02000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <2>;
		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
				0x0000c000 0x1404a38e 0x00000000>;
	};
};
Commit	Line	Data
082d33d0 SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
35346b22 LY	13	#include <dt-bindings/gpio/gpio.h>
35346b22 LY	14
082d33d0 SG	15	/ {
	16	memory {
	17	reg = <0x10000000 0x80000000>;
	18	};
1169cf1f	19
35346b22 LY	20	leds {
	21	compatible = "gpio-leds";
	22	pinctrl-names = "default";
	23	pinctrl-0 = <&pinctrl_gpio_leds>;
	24
	25	user {
	26	label = "debug";
	27	gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
	28	};
	29	};
	30
1169cf1f NC	31	sound-spdif {
	32	compatible = "fsl,imx-audio-spdif",
	33	"fsl,imx-sabreauto-spdif";
	34	model = "imx-spdif";
	35	spdif-controller = <&spdif>;
	36	spdif-in;
	37	};
c0f16624 FE	38
	39	backlight {
	40	compatible = "pwm-backlight";
	41	pwms = <&pwm3 0 5000000>;
	42	brightness-levels = <0 4 8 16 32 64 128 255>;
	43	default-brightness-level = <7>;
	44	status = "okay";
	45	};
082d33d0 SG	46	};
082d33d0 SG	47
faacc290 HS	48	&ecspi1 {
	49	fsl,spi-num-chipselects = <1>;
	50	cs-gpios = <&gpio3 19 0>;
	51	pinctrl-names = "default";
817c27a1	52	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
faacc290 HS	53	status = "disabled"; /* pin conflict with WEIM NOR */
	54
	55	flash: m25p80@0 {
	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	compatible = "st,m25p32";
	59	spi-max-frequency = <20000000>;
	60	reg = <0>;
	61	};
	62	};
	63
082d33d0 SG	64	&fec {
082d33d0 SG	65	pinctrl-names = "default";
817c27a1	66	pinctrl-0 = <&pinctrl_enet>;
082d33d0	67	phy-mode = "rgmii";
bc20a5d6 TK	68	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
bc20a5d6 TK	69	<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
082d33d0 SG	70	status = "okay";
	71	};
	72
82726931 HS	73	&gpmi {
82726931 HS	74	pinctrl-names = "default";
817c27a1	75	pinctrl-0 = <&pinctrl_gpmi_nand>;
82726931 HS	76	status = "okay";
	77	};
	78
1906c21a FE	79	&hdmi {
	80	status = "okay";
	81	};
	82
44659021 FE	83	&i2c2 {
	84	clock-frequency = <100000>;
	85	pinctrl-names = "default";
	86	pinctrl-0 = <&pinctrl_i2c2>;
	87	status = "okay";
	88
	89	pmic: pfuze100@08 {
	90	compatible = "fsl,pfuze100";
	91	reg = <0x08>;
	92
	93	regulators {
	94	sw1a_reg: sw1ab {
	95	regulator-min-microvolt = <300000>;
	96	regulator-max-microvolt = <1875000>;
	97	regulator-boot-on;
	98	regulator-always-on;
	99	regulator-ramp-delay = <6250>;
	100	};
	101
	102	sw1c_reg: sw1c {
	103	regulator-min-microvolt = <300000>;
	104	regulator-max-microvolt = <1875000>;
	105	regulator-boot-on;
	106	regulator-always-on;
	107	regulator-ramp-delay = <6250>;
	108	};
	109
	110	sw2_reg: sw2 {
	111	regulator-min-microvolt = <800000>;
	112	regulator-max-microvolt = <3300000>;
	113	regulator-boot-on;
	114	regulator-always-on;
	115	};
	116
	117	sw3a_reg: sw3a {
	118	regulator-min-microvolt = <400000>;
	119	regulator-max-microvolt = <1975000>;
	120	regulator-boot-on;
	121	regulator-always-on;
	122	};
	123
	124	sw3b_reg: sw3b {
	125	regulator-min-microvolt = <400000>;
	126	regulator-max-microvolt = <1975000>;
	127	regulator-boot-on;
	128	regulator-always-on;
	129	};
	130
	131	sw4_reg: sw4 {
	132	regulator-min-microvolt = <800000>;
	133	regulator-max-microvolt = <3300000>;
	134	};
	135
	136	swbst_reg: swbst {
	137	regulator-min-microvolt = <5000000>;
	138	regulator-max-microvolt = <5150000>;
	139	};
	140
	141	snvs_reg: vsnvs {
	142	regulator-min-microvolt = <1000000>;
	143	regulator-max-microvolt = <3000000>;
	144	regulator-boot-on;
	145	regulator-always-on;
	146	};
147
148	vref_reg: vrefddr {
149	regulator-boot-on;
150	regulator-always-on;
151	};
152
153	vgen1_reg: vgen1 {
154	regulator-min-microvolt = <800000>;
155	regulator-max-microvolt = <1550000>;
156	};
157
158	vgen2_reg: vgen2 {
159	regulator-min-microvolt = <800000>;
160	regulator-max-microvolt = <1550000>;
161	};
162
163	vgen3_reg: vgen3 {
164	regulator-min-microvolt = <1800000>;
165	regulator-max-microvolt = <3300000>;
166	};
167
168	vgen4_reg: vgen4 {
169	regulator-min-microvolt = <1800000>;
170	regulator-max-microvolt = <3300000>;
171	regulator-always-on;
172	};
173
174	vgen5_reg: vgen5 {
175	regulator-min-microvolt = <1800000>;
176	regulator-max-microvolt = <3300000>;
177	regulator-always-on;
178	};
179
180	vgen6_reg: vgen6 {
181	regulator-min-microvolt = <1800000>;
182	regulator-max-microvolt = <3300000>;
183	regulator-always-on;
184	};
185	};
186	};
187	};
188
4e18a224 PC	189	&i2c3 {
	190	pinctrl-names = "default";
	191	pinctrl-0 = <&pinctrl_i2c3>;
4e18a224 PC	192	status = "okay";
	193
	194	max7310_a: gpio@30 {
	195	compatible = "maxim,max7310";
	196	reg = <0x30>;
	197	gpio-controller;
	198	#gpio-cells = <2>;
	199	};
	200
	201	max7310_b: gpio@32 {
	202	compatible = "maxim,max7310";
	203	reg = <0x32>;
	204	gpio-controller;
	205	#gpio-cells = <2>;
	206	};
	207
	208	max7310_c: gpio@34 {
	209	compatible = "maxim,max7310";
	210	reg = <0x34>;
	211	gpio-controller;
	212	#gpio-cells = <2>;
	213	};
	214	};
	215
c56009b2 SG	216	&iomuxc {
	217	pinctrl-names = "default";
	218	pinctrl-0 = <&pinctrl_hog>;
	219
817c27a1	220	imx6qdl-sabreauto {
c56009b2 SG	221	pinctrl_hog: hoggrp {
	222	fsl,pins = <
	223	MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
	224	MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
93e2ca02	225	MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
c56009b2 SG	226	>;
c56009b2 SG	227	};
c56009b2	228
817c27a1 SG	229	pinctrl_ecspi1: ecspi1grp {
	230	fsl,pins = <
	231	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	232	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	233	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	234	>;
	235	};
	236
	237	pinctrl_ecspi1_cs: ecspi1cs {
c56009b2 SG	238	fsl,pins = <
	239	MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
	240	>;
	241	};
817c27a1 SG	242
	243	pinctrl_enet: enetgrp {
	244	fsl,pins = <
	245	MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
	246	MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
	247	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	248	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	249	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	250	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	251	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	252	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	253	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	254	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	255	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	256	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	257	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	258	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	259	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
bc20a5d6	260	MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
817c27a1 SG	261	>;
	262	};
	263
35346b22 LY	264	pinctrl_gpio_leds: gpioledsgrp {
	265	fsl,pins = <
	266	MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
	267	>;
	268	};
	269
817c27a1 SG	270	pinctrl_gpmi_nand: gpminandgrp {
	271	fsl,pins = <
	272	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	273	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	274	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	275	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	276	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	277	MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
	278	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	279	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	280	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	281	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	282	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	283	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	284	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	285	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	286	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	287	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	288	MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
	289	>;
	290	};
	291
44659021 FE	292	pinctrl_i2c2: i2c2grp {
	293	fsl,pins = <
	294	MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
	295	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	296	>;
	297	};
	298
4e18a224 PC	299	pinctrl_i2c3: i2c3grp {
	300	fsl,pins = <
	301	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	302	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	303	>;
	304	};
	305
c0f16624 FE	306	pinctrl_pwm3: pwm1grp {
	307	fsl,pins = <
	308	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	309	>;
	310	};
	311
1169cf1f NC	312	pinctrl_spdif: spdifgrp {
	313	fsl,pins = <
	314	MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
	315	>;
	316	};
	317
817c27a1 SG	318	pinctrl_uart4: uart4grp {
	319	fsl,pins = <
	320	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	321	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	322	>;
	323	};
	324
	325	pinctrl_usdhc3: usdhc3grp {
	326	fsl,pins = <
	327	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	328	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	329	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	330	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	331	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	332	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	333	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
	334	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
	335	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
	336	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
	337	>;
	338	};
	339
	340	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	341	fsl,pins = <
	342	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	343	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
	344	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	345	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	346	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	347	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	348	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
	349	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
	350	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
	351	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
	352	>;
	353	};
	354
	355	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	356	fsl,pins = <
	357	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	358	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	359	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	360	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	361	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	362	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	363	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
	364	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
	365	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
	366	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
	367	>;
	368	};
	369
	370	pinctrl_weim_cs0: weimcs0grp {
	371	fsl,pins = <
	372	MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
	373	>;
	374	};
	375
	376	pinctrl_weim_nor: weimnorgrp {
	377	fsl,pins = <
	378	MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
	379	MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
	380	MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
	381	MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
382	MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
383	MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
384	MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
385	MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
386	MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
387	MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
388	MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
389	MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
390	MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
391	MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
392	MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
393	MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
394	MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
395	MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
396	MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
397	MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
398	MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
399	MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
400	MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
401	MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
402	MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
403	MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
404	MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
405	MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
406	MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
407	MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
408	MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
409	MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
410	MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
411	MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
412	MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
413	MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
414	MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
415	MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
416	MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
417	MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
418	MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
419	MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
420	MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
421	>;
422	};
c56009b2 SG	423	};
	424	};
	425
c0f16624 FE	426	&ldb {
	427	status = "okay";
	428
	429	lvds-channel@0 {
	430	fsl,data-mapping = "spwg";
	431	fsl,data-width = <18>;
	432	status = "okay";
	433
	434	display-timings {
	435	native-mode = <&timing0>;
	436	timing0: hsd100pxn1 {
	437	clock-frequency = <65000000>;
	438	hactive = <1024>;
	439	vactive = <768>;
	440	hback-porch = <220>;
	441	hfront-porch = <40>;
	442	vback-porch = <21>;
	443	vfront-porch = <7>;
	444	hsync-len = <60>;
	445	vsync-len = <10>;
	446	};
	447	};
	448	};
	449	};
	450
	451	&pwm3 {
	452	pinctrl-names = "default";
	453	pinctrl-0 = <&pinctrl_pwm3>;
	454	status = "okay";
	455	};
	456
1169cf1f NC	457	&spdif {
	458	pinctrl-names = "default";
	459	pinctrl-0 = <&pinctrl_spdif>;
	460	status = "okay";
	461	};
	462
082d33d0 SG	463	&uart4 {
082d33d0 SG	464	pinctrl-names = "default";
817c27a1	465	pinctrl-0 = <&pinctrl_uart4>;
082d33d0 SG	466	status = "okay";
	467	};
	468
	469	&usdhc3 {
93e2ca02	470	pinctrl-names = "default", "state_100mhz", "state_200mhz";
817c27a1 SG	471	pinctrl-0 = <&pinctrl_usdhc3>;
	472	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	473	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
082d33d0 SG	474	cd-gpios = <&gpio6 15 0>;
	475	wp-gpios = <&gpio1 13 0>;
	476	status = "okay";
	477	};
50fe0e90 HS	478
	479	&weim {
	480	pinctrl-names = "default";
817c27a1	481	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
50fe0e90 HS	482	#address-cells = <2>;
	483	#size-cells = <1>;
	484	ranges = <0 0 0x08000000 0x08000000>;
	485	status = "disabled"; /* pin conflict with SPI NOR */
	486
	487	nor@0,0 {
	488	compatible = "cfi-flash";
	489	reg = <0 0 0x02000000>;
	490	#address-cells = <1>;
	491	#size-cells = <1>;
	492	bank-width = <2>;
	493	fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
	494	0x0000c000 0x1404a38e 0x00000000>;
	495	};
	496	};