[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl-sabrelite.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/ {
	memory {
		reg = <0x10000000 0x40000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_2p5v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-always-on;
		};

		reg_3p3v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_usb_otg_vbus: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "usb_otg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 22 0>;
			enable-active-high;
		};
	};

	sound {
		compatible = "fsl,imx6q-sabrelite-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6q-sabrelite-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio3 19 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "okay";

	flash: m25p80@0 {
		compatible = "sst,sst25vf016b";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 23 0>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 201>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6q-sabrelite {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x80000000
			>;
		};

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
				MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
				MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
				MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
				MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1	/* CS */
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
				/* power enable, high active */
				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0	/* CD */
				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0	/* WP */
			>;
		};

		pinctrl_usdhc4: usdhc4grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0	/* CD */
			>;
		};
	};
};

&ldb {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};
};

&pcie {
	status = "okay";
};

&ssi1 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio7 0 0>;
	wp-gpios = <&gpio7 1 0>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	cd-gpios = <&gpio2 6 0>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};
Commit	Line	Data
1efa1265 TK	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/ {
	14	memory {
	15	reg = <0x10000000 0x40000000>;
	16	};
	17
	18	regulators {
	19	compatible = "simple-bus";
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
	23	reg_2p5v: regulator@0 {
	24	compatible = "regulator-fixed";
	25	reg = <0>;
	26	regulator-name = "2P5V";
	27	regulator-min-microvolt = <2500000>;
	28	regulator-max-microvolt = <2500000>;
	29	regulator-always-on;
	30	};
	31
	32	reg_3p3v: regulator@1 {
	33	compatible = "regulator-fixed";
	34	reg = <1>;
	35	regulator-name = "3P3V";
	36	regulator-min-microvolt = <3300000>;
	37	regulator-max-microvolt = <3300000>;
	38	regulator-always-on;
	39	};
	40
	41	reg_usb_otg_vbus: regulator@2 {
	42	compatible = "regulator-fixed";
	43	reg = <2>;
	44	regulator-name = "usb_otg_vbus";
	45	regulator-min-microvolt = <5000000>;
	46	regulator-max-microvolt = <5000000>;
	47	gpio = <&gpio3 22 0>;
	48	enable-active-high;
	49	};
	50	};
	51
	52	sound {
	53	compatible = "fsl,imx6q-sabrelite-sgtl5000",
	54	"fsl,imx-audio-sgtl5000";
	55	model = "imx6q-sabrelite-sgtl5000";
	56	ssi-controller = <&ssi1>;
	57	audio-codec = <&codec>;
	58	audio-routing =
	59	"MIC_IN", "Mic Jack",
	60	"Mic Jack", "Mic Bias",
	61	"Headphone Jack", "HP_OUT";
	62	mux-int-port = <1>;
	63	mux-ext-port = <4>;
	64	};
65	};
66
67	&audmux {
68	pinctrl-names = "default";
69	pinctrl-0 = <&pinctrl_audmux>;
70	status = "okay";
71	};
72
73	&ecspi1 {
74	fsl,spi-num-chipselects = <1>;
75	cs-gpios = <&gpio3 19 0>;
76	pinctrl-names = "default";
77	pinctrl-0 = <&pinctrl_ecspi1>;
78	status = "okay";
79
80	flash: m25p80@0 {
81	compatible = "sst,sst25vf016b";
82	spi-max-frequency = <20000000>;
83	reg = <0>;
84	};
85	};
86
87	&fec {
88	pinctrl-names = "default";
89	pinctrl-0 = <&pinctrl_enet>;
90	phy-mode = "rgmii";
91	phy-reset-gpios = <&gpio3 23 0>;
92	status = "okay";
93	};
94
95	&i2c1 {
96	clock-frequency = <100000>;
97	pinctrl-names = "default";
98	pinctrl-0 = <&pinctrl_i2c1>;
99	status = "okay";
100
101	codec: sgtl5000@0a {
102	compatible = "fsl,sgtl5000";
103	reg = <0x0a>;
104	clocks = <&clks 201>;
105	VDDA-supply = <&reg_2p5v>;
106	VDDIO-supply = <&reg_3p3v>;
107	};
108	};
109
110	&iomuxc {
111	pinctrl-names = "default";
112	pinctrl-0 = <&pinctrl_hog>;
113
114	imx6q-sabrelite {
115	pinctrl_hog: hoggrp {
116	fsl,pins = <
1efa1265	117	MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
1efa1265 TK	118	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
	119	>;
	120	};
	121
	122	pinctrl_audmux: audmuxgrp {
	123	fsl,pins = <
	124	MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
	125	MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
	126	MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
	127	MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
	128	>;
	129	};
	130
	131	pinctrl_ecspi1: ecspi1grp {
	132	fsl,pins = <
	133	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	134	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	135	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
c40f58aa	136	MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
1efa1265 TK	137	>;
	138	};
	139
	140	pinctrl_enet: enetgrp {
	141	fsl,pins = <
	142	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	143	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	144	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	145	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	146	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	147	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	148	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	149	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	150	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	151	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	152	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	153	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	154	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	155	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	156	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
	157	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	158	>;
	159	};
	160
	161	pinctrl_i2c1: i2c1grp {
	162	fsl,pins = <
	163	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	164	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	165	>;
	166	};
	167
da08d27f TK	168	pinctrl_uart1: uart1grp {
	169	fsl,pins = <
	170	MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
	171	MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
	172	>;
	173	};
	174
1efa1265 TK	175	pinctrl_uart2: uart2grp {
	176	fsl,pins = <
	177	MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
	178	MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
	179	>;
	180	};
	181
	182	pinctrl_usbotg: usbotggrp {
	183	fsl,pins = <
	184	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
d06d8785 TK	185	/* power enable, high active */
d06d8785 TK	186	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
1efa1265 TK	187	>;
	188	};
	189
	190	pinctrl_usdhc3: usdhc3grp {
	191	fsl,pins = <
	192	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	193	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	194	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	195	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	196	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	197	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
473f0fc0 TK	198	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
473f0fc0 TK	199	MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
1efa1265 TK	200	>;
	201	};
	202
	203	pinctrl_usdhc4: usdhc4grp {
	204	fsl,pins = <
	205	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
	206	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
	207	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
	208	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
	209	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
	210	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
0e06842f	211	MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
1efa1265 TK	212	>;
	213	};
	214	};
	215	};
	216
	217	&ldb {
	218	status = "okay";
	219
	220	lvds-channel@0 {
	221	fsl,data-mapping = "spwg";
	222	fsl,data-width = <18>;
	223	status = "okay";
	224
	225	display-timings {
	226	native-mode = <&timing0>;
	227	timing0: hsd100pxn1 {
	228	clock-frequency = <65000000>;
	229	hactive = <1024>;
	230	vactive = <768>;
	231	hback-porch = <220>;
	232	hfront-porch = <40>;
	233	vback-porch = <21>;
	234	vfront-porch = <7>;
	235	hsync-len = <60>;
	236	vsync-len = <10>;
	237	};
	238	};
	239	};
	240	};
	241
	242	&pcie {
	243	status = "okay";
	244	};
	245
	246	&ssi1 {
	247	fsl,mode = "i2s-slave";
	248	status = "okay";
	249	};
	250
da08d27f TK	251	&uart1 {
	252	pinctrl-names = "default";
	253	pinctrl-0 = <&pinctrl_uart1>;
	254	status = "okay";
	255	};
	256
1efa1265 TK	257	&uart2 {
	258	pinctrl-names = "default";
	259	pinctrl-0 = <&pinctrl_uart2>;
	260	status = "okay";
	261	};
	262
	263	&usbh1 {
	264	status = "okay";
	265	};
	266
	267	&usbotg {
	268	vbus-supply = <&reg_usb_otg_vbus>;
	269	pinctrl-names = "default";
	270	pinctrl-0 = <&pinctrl_usbotg>;
	271	disable-over-current;
	272	status = "okay";
	273	};
	274
	275	&usdhc3 {
	276	pinctrl-names = "default";
	277	pinctrl-0 = <&pinctrl_usdhc3>;
	278	cd-gpios = <&gpio7 0 0>;
	279	wp-gpios = <&gpio7 1 0>;
	280	vmmc-supply = <&reg_3p3v>;
	281	status = "okay";
	282	};
	283
	284	&usdhc4 {
	285	pinctrl-names = "default";
	286	pinctrl-0 = <&pinctrl_usdhc4>;
	287	cd-gpios = <&gpio2 6 0>;
1efa1265 TK	288	vmmc-supply = <&reg_3p3v>;
	289	status = "okay";
	290	};