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Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
7d740f87
SG		 14
15/ {
16 aliases {
8f9ffecf
RZ		 17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
5230f8fe
SG		 22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
7d740f87
SG		 29 };
30
7d740f87
SG		 31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
f30fb03d 68 dma_apbh: dma-apbh@00110000 {
e5d0f9f5
HS		 69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
f30fb03d
SG		 71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
0e87e043 75 clocks = <&clks 106>;
e5d0f9f5
HS		 76 };
77
be4ccfce 78 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 79 compatible = "fsl,imx6q-gpmi-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
f30fb03d
SG		 90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
0e87e043
SG		 92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled";
cf922fa8
HS		 94 };
95
7d740f87 96 timer@00a00600 {
58458e03
MZ		 97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
2bb4b70b 100 clocks = <&clks 15>;
7d740f87
SG		 101 };
102
103 L2: l2-cache@00a02000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x00a02000 0x1000>;
106 interrupts = <0 92 0x04>;
107 cache-unified;
108 cache-level = <2>;
5a5ca56e
DB		 109 arm,tag-latency = <4 2 3>;
110 arm,data-latency = <4 2 3>;
7d740f87
SG		 111 };
112
218abe6f
DB		 113 pmu {
114 compatible = "arm,cortex-a9-pmu";
115 interrupts = <0 94 0x04>;
116 };
117
7d740f87
SG		 118 aips-bus@02000000 { /* AIPS1 */
119 compatible = "fsl,aips-bus", "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 reg = <0x02000000 0x100000>;
123 ranges;
124
125 spba-bus@02000000 {
126 compatible = "fsl,spba-bus", "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0x02000000 0x40000>;
130 ranges;
131
7b7d6727 132 spdif: spdif@02004000 {
7d740f87
SG		 133 reg = <0x02004000 0x4000>;
134 interrupts = <0 52 0x04>;
135 };
136
7b7d6727 137 ecspi1: ecspi@02008000 {
7d740f87
SG		 138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
141 reg = <0x02008000 0x4000>;
142 interrupts = <0 31 0x04>;
0e87e043
SG		 143 clocks = <&clks 112>, <&clks 112>;
144 clock-names = "ipg", "per";
7d740f87
SG		 145 status = "disabled";
146 };
147
7b7d6727 148 ecspi2: ecspi@0200c000 {
7d740f87
SG		 149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
152 reg = <0x0200c000 0x4000>;
153 interrupts = <0 32 0x04>;
0e87e043
SG		 154 clocks = <&clks 113>, <&clks 113>;
155 clock-names = "ipg", "per";
7d740f87
SG		 156 status = "disabled";
157 };
158
7b7d6727 159 ecspi3: ecspi@02010000 {
7d740f87
SG		 160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
163 reg = <0x02010000 0x4000>;
164 interrupts = <0 33 0x04>;
0e87e043
SG		 165 clocks = <&clks 114>, <&clks 114>;
166 clock-names = "ipg", "per";
7d740f87
SG		 167 status = "disabled";
168 };
169
7b7d6727 170 ecspi4: ecspi@02014000 {
7d740f87
SG		 171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
174 reg = <0x02014000 0x4000>;
175 interrupts = <0 34 0x04>;
0e87e043
SG		 176 clocks = <&clks 115>, <&clks 115>;
177 clock-names = "ipg", "per";
7d740f87
SG		 178 status = "disabled";
179 };
180
0c456cfa 181 uart1: serial@02020000 {
7d740f87
SG		 182 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
183 reg = <0x02020000 0x4000>;
184 interrupts = <0 26 0x04>;
0e87e043
SG		 185 clocks = <&clks 160>, <&clks 161>;
186 clock-names = "ipg", "per";
7d740f87
SG		 187 status = "disabled";
188 };
189
7b7d6727 190 esai: esai@02024000 {
7d740f87
SG		 191 reg = <0x02024000 0x4000>;
192 interrupts = <0 51 0x04>;
193 };
194
b1a5da8e
RZ		 195 ssi1: ssi@02028000 {
196 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 197 reg = <0x02028000 0x4000>;
198 interrupts = <0 46 0x04>;
0e87e043 199 clocks = <&clks 178>;
b1a5da8e
RZ		 200 fsl,fifo-depth = <15>;
201 fsl,ssi-dma-events = <38 37>;
202 status = "disabled";
7d740f87
SG		 203 };
204
b1a5da8e
RZ		 205 ssi2: ssi@0202c000 {
206 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 207 reg = <0x0202c000 0x4000>;
208 interrupts = <0 47 0x04>;
0e87e043 209 clocks = <&clks 179>;
b1a5da8e
RZ		 210 fsl,fifo-depth = <15>;
211 fsl,ssi-dma-events = <42 41>;
212 status = "disabled";
7d740f87
SG		 213 };
214
b1a5da8e
RZ		 215 ssi3: ssi@02030000 {
216 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87
SG		 217 reg = <0x02030000 0x4000>;
218 interrupts = <0 48 0x04>;
0e87e043 219 clocks = <&clks 180>;
b1a5da8e
RZ		 220 fsl,fifo-depth = <15>;
221 fsl,ssi-dma-events = <46 45>;
222 status = "disabled";
7d740f87
SG		 223 };
224
7b7d6727 225 asrc: asrc@02034000 {
7d740f87
SG		 226 reg = <0x02034000 0x4000>;
227 interrupts = <0 50 0x04>;
228 };
229
230 spba@0203c000 {
231 reg = <0x0203c000 0x4000>;
232 };
233 };
234
7b7d6727 235 vpu: vpu@02040000 {
7d740f87
SG		 236 reg = <0x02040000 0x3c000>;
237 interrupts = <0 3 0x04 0 12 0x04>;
238 };
239
240 aipstz@0207c000 { /* AIPSTZ1 */
241 reg = <0x0207c000 0x4000>;
242 };
243
7b7d6727 244 pwm1: pwm@02080000 {
33b38587
SH		 245 #pwm-cells = <2>;
246 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 247 reg = <0x02080000 0x4000>;
248 interrupts = <0 83 0x04>;
33b38587
SH		 249 clocks = <&clks 62>, <&clks 145>;
250 clock-names = "ipg", "per";
7d740f87
SG		 251 };
252
7b7d6727 253 pwm2: pwm@02084000 {
33b38587
SH		 254 #pwm-cells = <2>;
255 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 256 reg = <0x02084000 0x4000>;
257 interrupts = <0 84 0x04>;
33b38587
SH		 258 clocks = <&clks 62>, <&clks 146>;
259 clock-names = "ipg", "per";
7d740f87
SG		 260 };
261
7b7d6727 262 pwm3: pwm@02088000 {
33b38587
SH		 263 #pwm-cells = <2>;
264 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 265 reg = <0x02088000 0x4000>;
266 interrupts = <0 85 0x04>;
33b38587
SH		 267 clocks = <&clks 62>, <&clks 147>;
268 clock-names = "ipg", "per";
7d740f87
SG		 269 };
270
7b7d6727 271 pwm4: pwm@0208c000 {
33b38587
SH		 272 #pwm-cells = <2>;
273 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87
SG		 274 reg = <0x0208c000 0x4000>;
275 interrupts = <0 86 0x04>;
33b38587
SH		 276 clocks = <&clks 62>, <&clks 148>;
277 clock-names = "ipg", "per";
7d740f87
SG		 278 };
279
7b7d6727 280 can1: flexcan@02090000 {
7d740f87
SG		 281 reg = <0x02090000 0x4000>;
282 interrupts = <0 110 0x04>;
283 };
284
7b7d6727 285 can2: flexcan@02094000 {
7d740f87
SG		 286 reg = <0x02094000 0x4000>;
287 interrupts = <0 111 0x04>;
288 };
289
7b7d6727 290 gpt: gpt@02098000 {
7d740f87
SG		 291 compatible = "fsl,imx6q-gpt";
292 reg = <0x02098000 0x4000>;
293 interrupts = <0 55 0x04>;
4efccadd
SH		 294 clocks = <&clks 119>, <&clks 120>;
295 clock-names = "ipg", "per";
7d740f87
SG		 296 };
297
4d191868 298 gpio1: gpio@0209c000 {
aeb27748 299 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 300 reg = <0x0209c000 0x4000>;
301 interrupts = <0 66 0x04 0 67 0x04>;
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
88cde8b7 305 #interrupt-cells = <2>;
7d740f87
SG		 306 };
307
4d191868 308 gpio2: gpio@020a0000 {
aeb27748 309 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 310 reg = <0x020a0000 0x4000>;
311 interrupts = <0 68 0x04 0 69 0x04>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
88cde8b7 315 #interrupt-cells = <2>;
7d740f87
SG		 316 };
317
4d191868 318 gpio3: gpio@020a4000 {
aeb27748 319 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 320 reg = <0x020a4000 0x4000>;
321 interrupts = <0 70 0x04 0 71 0x04>;
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-controller;
88cde8b7 325 #interrupt-cells = <2>;
7d740f87
SG		 326 };
327
4d191868 328 gpio4: gpio@020a8000 {
aeb27748 329 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 330 reg = <0x020a8000 0x4000>;
331 interrupts = <0 72 0x04 0 73 0x04>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
88cde8b7 335 #interrupt-cells = <2>;
7d740f87
SG		 336 };
337
4d191868 338 gpio5: gpio@020ac000 {
aeb27748 339 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 340 reg = <0x020ac000 0x4000>;
341 interrupts = <0 74 0x04 0 75 0x04>;
342 gpio-controller;
343 #gpio-cells = <2>;
344 interrupt-controller;
88cde8b7 345 #interrupt-cells = <2>;
7d740f87
SG		 346 };
347
4d191868 348 gpio6: gpio@020b0000 {
aeb27748 349 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 350 reg = <0x020b0000 0x4000>;
351 interrupts = <0 76 0x04 0 77 0x04>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
88cde8b7 355 #interrupt-cells = <2>;
7d740f87
SG		 356 };
357
4d191868 358 gpio7: gpio@020b4000 {
aeb27748 359 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87
SG		 360 reg = <0x020b4000 0x4000>;
361 interrupts = <0 78 0x04 0 79 0x04>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
88cde8b7 365 #interrupt-cells = <2>;
7d740f87
SG		 366 };
367
7b7d6727 368 kpp: kpp@020b8000 {
7d740f87
SG		 369 reg = <0x020b8000 0x4000>;
370 interrupts = <0 82 0x04>;
371 };
372
7b7d6727 373 wdog1: wdog@020bc000 {
7d740f87
SG		 374 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
375 reg = <0x020bc000 0x4000>;
376 interrupts = <0 80 0x04>;
0e87e043 377 clocks = <&clks 0>;
7d740f87
SG		 378 };
379
7b7d6727 380 wdog2: wdog@020c0000 {
7d740f87
SG		 381 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
382 reg = <0x020c0000 0x4000>;
383 interrupts = <0 81 0x04>;
0e87e043 384 clocks = <&clks 0>;
7d740f87
SG		 385 status = "disabled";
386 };
387
0e87e043 388 clks: ccm@020c4000 {
7d740f87
SG		 389 compatible = "fsl,imx6q-ccm";
390 reg = <0x020c4000 0x4000>;
391 interrupts = <0 87 0x04 0 88 0x04>;
0e87e043 392 #clock-cells = <1>;
7d740f87
SG		 393 };
394
baa64151
DA		 395 anatop: anatop@020c8000 {
396 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87
SG		 397 reg = <0x020c8000 0x1000>;
398 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
a1e327e6
YCLP		 399
400 regulator-1p1@110 {
401 compatible = "fsl,anatop-regulator";
402 regulator-name = "vdd1p1";
403 regulator-min-microvolt = <800000>;
404 regulator-max-microvolt = <1375000>;
405 regulator-always-on;
406 anatop-reg-offset = <0x110>;
407 anatop-vol-bit-shift = <8>;
408 anatop-vol-bit-width = <5>;
409 anatop-min-bit-val = <4>;
410 anatop-min-voltage = <800000>;
411 anatop-max-voltage = <1375000>;
412 };
413
414 regulator-3p0@120 {
415 compatible = "fsl,anatop-regulator";
416 regulator-name = "vdd3p0";
417 regulator-min-microvolt = <2800000>;
418 regulator-max-microvolt = <3150000>;
419 regulator-always-on;
420 anatop-reg-offset = <0x120>;
421 anatop-vol-bit-shift = <8>;
422 anatop-vol-bit-width = <5>;
423 anatop-min-bit-val = <0>;
424 anatop-min-voltage = <2625000>;
425 anatop-max-voltage = <3400000>;
426 };
427
428 regulator-2p5@130 {
429 compatible = "fsl,anatop-regulator";
430 regulator-name = "vdd2p5";
431 regulator-min-microvolt = <2000000>;
432 regulator-max-microvolt = <2750000>;
433 regulator-always-on;
434 anatop-reg-offset = <0x130>;
435 anatop-vol-bit-shift = <8>;
436 anatop-vol-bit-width = <5>;
437 anatop-min-bit-val = <0>;
438 anatop-min-voltage = <2000000>;
439 anatop-max-voltage = <2750000>;
440 };
441
96574a6d 442 reg_arm: regulator-vddcore@140 {
a1e327e6
YCLP		 443 compatible = "fsl,anatop-regulator";
444 regulator-name = "cpu";
445 regulator-min-microvolt = <725000>;
446 regulator-max-microvolt = <1450000>;
447 regulator-always-on;
448 anatop-reg-offset = <0x140>;
449 anatop-vol-bit-shift = <0>;
450 anatop-vol-bit-width = <5>;
46743dd6
AH		 451 anatop-delay-reg-offset = <0x170>;
452 anatop-delay-bit-shift = <24>;
453 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 454 anatop-min-bit-val = <1>;
455 anatop-min-voltage = <725000>;
456 anatop-max-voltage = <1450000>;
457 };
458
96574a6d 459 reg_pu: regulator-vddpu@140 {
a1e327e6
YCLP		 460 compatible = "fsl,anatop-regulator";
461 regulator-name = "vddpu";
462 regulator-min-microvolt = <725000>;
463 regulator-max-microvolt = <1450000>;
464 regulator-always-on;
465 anatop-reg-offset = <0x140>;
466 anatop-vol-bit-shift = <9>;
467 anatop-vol-bit-width = <5>;
46743dd6
AH		 468 anatop-delay-reg-offset = <0x170>;
469 anatop-delay-bit-shift = <26>;
470 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 471 anatop-min-bit-val = <1>;
472 anatop-min-voltage = <725000>;
473 anatop-max-voltage = <1450000>;
474 };
475
96574a6d 476 reg_soc: regulator-vddsoc@140 {
a1e327e6
YCLP		 477 compatible = "fsl,anatop-regulator";
478 regulator-name = "vddsoc";
479 regulator-min-microvolt = <725000>;
480 regulator-max-microvolt = <1450000>;
481 regulator-always-on;
482 anatop-reg-offset = <0x140>;
483 anatop-vol-bit-shift = <18>;
484 anatop-vol-bit-width = <5>;
46743dd6
AH		 485 anatop-delay-reg-offset = <0x170>;
486 anatop-delay-bit-shift = <28>;
487 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 488 anatop-min-bit-val = <1>;
489 anatop-min-voltage = <725000>;
490 anatop-max-voltage = <1450000>;
491 };
7d740f87
SG		 492 };
493
74bd88f7
RZ		 494 usbphy1: usbphy@020c9000 {
495 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 496 reg = <0x020c9000 0x1000>;
497 interrupts = <0 44 0x04>;
0e87e043 498 clocks = <&clks 182>;
7d740f87
SG		 499 };
500
74bd88f7
RZ		 501 usbphy2: usbphy@020ca000 {
502 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87
SG		 503 reg = <0x020ca000 0x1000>;
504 interrupts = <0 45 0x04>;
0e87e043 505 clocks = <&clks 183>;
7d740f87
SG		 506 };
507
508 snvs@020cc000 {
c9250388
SG		 509 compatible = "fsl,sec-v4.0-mon", "simple-bus";
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges = <0 0x020cc000 0x4000>;
513
514 snvs-rtc-lp@34 {
515 compatible = "fsl,sec-v4.0-mon-rtc-lp";
516 reg = <0x34 0x58>;
517 interrupts = <0 19 0x04 0 20 0x04>;
518 };
7d740f87
SG		 519 };
520
7b7d6727 521 epit1: epit@020d0000 { /* EPIT1 */
7d740f87
SG		 522 reg = <0x020d0000 0x4000>;
523 interrupts = <0 56 0x04>;
524 };
525
7b7d6727 526 epit2: epit@020d4000 { /* EPIT2 */
7d740f87
SG		 527 reg = <0x020d4000 0x4000>;
528 interrupts = <0 57 0x04>;
529 };
530
7b7d6727 531 src: src@020d8000 {
bd3d924d 532 compatible = "fsl,imx6q-src", "fsl,imx51-src";
7d740f87
SG		 533 reg = <0x020d8000 0x4000>;
534 interrupts = <0 91 0x04 0 96 0x04>;
09ebf366 535 #reset-cells = <1>;
7d740f87
SG		 536 };
537
7b7d6727 538 gpc: gpc@020dc000 {
7d740f87
SG		 539 compatible = "fsl,imx6q-gpc";
540 reg = <0x020dc000 0x4000>;
541 interrupts = <0 89 0x04 0 90 0x04>;
542 };
543
df37e0c0
DA		 544 gpr: iomuxc-gpr@020e0000 {
545 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
546 reg = <0x020e0000 0x38>;
547 };
548
41c04342
ST		 549 ldb: ldb@020e0008 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
553 gpr = <&gpr>;
554 status = "disabled";
555
556 lvds-channel@0 {
557 reg = <0>;
558 crtcs = <&ipu1 0>;
559 status = "disabled";
560 };
561
562 lvds-channel@1 {
563 reg = <1>;
564 crtcs = <&ipu1 1>;
565 status = "disabled";
566 };
567 };
568
7b7d6727 569 dcic1: dcic@020e4000 {
7d740f87
SG		 570 reg = <0x020e4000 0x4000>;
571 interrupts = <0 124 0x04>;
572 };
573
7b7d6727 574 dcic2: dcic@020e8000 {
7d740f87
SG		 575 reg = <0x020e8000 0x4000>;
576 interrupts = <0 125 0x04>;
577 };
578
7b7d6727 579 sdma: sdma@020ec000 {
7d740f87
SG		 580 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
581 reg = <0x020ec000 0x4000>;
582 interrupts = <0 2 0x04>;
0e87e043
SG		 583 clocks = <&clks 155>, <&clks 155>;
584 clock-names = "ipg", "ahb";
d6b9c591 585 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 586 };
587 };
588
589 aips-bus@02100000 { /* AIPS2 */
590 compatible = "fsl,aips-bus", "simple-bus";
591 #address-cells = <1>;
592 #size-cells = <1>;
593 reg = <0x02100000 0x100000>;
594 ranges;
595
596 caam@02100000 {
597 reg = <0x02100000 0x40000>;
598 interrupts = <0 105 0x04 0 106 0x04>;
599 };
600
601 aipstz@0217c000 { /* AIPSTZ2 */
602 reg = <0x0217c000 0x4000>;
603 };
604
7b7d6727 605 usbotg: usb@02184000 {
74bd88f7
RZ		 606 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
607 reg = <0x02184000 0x200>;
608 interrupts = <0 43 0x04>;
0e87e043 609 clocks = <&clks 162>;
74bd88f7 610 fsl,usbphy = <&usbphy1>;
28342c61 611 fsl,usbmisc = <&usbmisc 0>;
74bd88f7
RZ		 612 status = "disabled";
613 };
614
7b7d6727 615 usbh1: usb@02184200 {
74bd88f7
RZ		 616 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
617 reg = <0x02184200 0x200>;
618 interrupts = <0 40 0x04>;
0e87e043 619 clocks = <&clks 162>;
74bd88f7 620 fsl,usbphy = <&usbphy2>;
28342c61 621 fsl,usbmisc = <&usbmisc 1>;
74bd88f7
RZ		 622 status = "disabled";
623 };
624
7b7d6727 625 usbh2: usb@02184400 {
74bd88f7
RZ		 626 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
627 reg = <0x02184400 0x200>;
628 interrupts = <0 41 0x04>;
0e87e043 629 clocks = <&clks 162>;
28342c61 630 fsl,usbmisc = <&usbmisc 2>;
74bd88f7
RZ		 631 status = "disabled";
632 };
633
7b7d6727 634 usbh3: usb@02184600 {
74bd88f7
RZ		 635 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
636 reg = <0x02184600 0x200>;
637 interrupts = <0 42 0x04>;
0e87e043 638 clocks = <&clks 162>;
28342c61 639 fsl,usbmisc = <&usbmisc 3>;
74bd88f7
RZ		 640 status = "disabled";
641 };
642
60984bdf 643 usbmisc: usbmisc@02184800 {
28342c61
RZ		 644 #index-cells = <1>;
645 compatible = "fsl,imx6q-usbmisc";
646 reg = <0x02184800 0x200>;
647 clocks = <&clks 162>;
648 };
649
7b7d6727 650 fec: ethernet@02188000 {
7d740f87
SG		 651 compatible = "fsl,imx6q-fec";
652 reg = <0x02188000 0x4000>;
653 interrupts = <0 118 0x04 0 119 0x04>;
8dd5c66b 654 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
7629838c 655 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 656 status = "disabled";
657 };
658
659 mlb@0218c000 {
660 reg = <0x0218c000 0x4000>;
661 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
662 };
663
7b7d6727 664 usdhc1: usdhc@02190000 {
7d740f87
SG		 665 compatible = "fsl,imx6q-usdhc";
666 reg = <0x02190000 0x4000>;
667 interrupts = <0 22 0x04>;
0e87e043
SG		 668 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
669 clock-names = "ipg", "ahb", "per";
c104b6a2 670 bus-width = <4>;
7d740f87
SG		 671 status = "disabled";
672 };
673
7b7d6727 674 usdhc2: usdhc@02194000 {
7d740f87
SG		 675 compatible = "fsl,imx6q-usdhc";
676 reg = <0x02194000 0x4000>;
677 interrupts = <0 23 0x04>;
0e87e043
SG		 678 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
679 clock-names = "ipg", "ahb", "per";
c104b6a2 680 bus-width = <4>;
7d740f87
SG		 681 status = "disabled";
682 };
683
7b7d6727 684 usdhc3: usdhc@02198000 {
7d740f87
SG		 685 compatible = "fsl,imx6q-usdhc";
686 reg = <0x02198000 0x4000>;
687 interrupts = <0 24 0x04>;
0e87e043
SG		 688 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
689 clock-names = "ipg", "ahb", "per";
c104b6a2 690 bus-width = <4>;
7d740f87
SG		 691 status = "disabled";
692 };
693
7b7d6727 694 usdhc4: usdhc@0219c000 {
7d740f87
SG		 695 compatible = "fsl,imx6q-usdhc";
696 reg = <0x0219c000 0x4000>;
697 interrupts = <0 25 0x04>;
0e87e043
SG		 698 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
699 clock-names = "ipg", "ahb", "per";
c104b6a2 700 bus-width = <4>;
7d740f87
SG		 701 status = "disabled";
702 };
703
7b7d6727 704 i2c1: i2c@021a0000 {
7d740f87
SG		 705 #address-cells = <1>;
706 #size-cells = <0>;
5bdfba29 707 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 708 reg = <0x021a0000 0x4000>;
709 interrupts = <0 36 0x04>;
0e87e043 710 clocks = <&clks 125>;
7d740f87
SG		 711 status = "disabled";
712 };
713
7b7d6727 714 i2c2: i2c@021a4000 {
7d740f87
SG		 715 #address-cells = <1>;
716 #size-cells = <0>;
5bdfba29 717 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 718 reg = <0x021a4000 0x4000>;
719 interrupts = <0 37 0x04>;
0e87e043 720 clocks = <&clks 126>;
7d740f87
SG		 721 status = "disabled";
722 };
723
7b7d6727 724 i2c3: i2c@021a8000 {
7d740f87
SG		 725 #address-cells = <1>;
726 #size-cells = <0>;
5bdfba29 727 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87
SG		 728 reg = <0x021a8000 0x4000>;
729 interrupts = <0 38 0x04>;
0e87e043 730 clocks = <&clks 127>;
7d740f87
SG		 731 status = "disabled";
732 };
733
734 romcp@021ac000 {
735 reg = <0x021ac000 0x4000>;
736 };
737
7b7d6727 738 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 739 compatible = "fsl,imx6q-mmdc";
740 reg = <0x021b0000 0x4000>;
741 };
742
7b7d6727 743 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 744 reg = <0x021b4000 0x4000>;
745 };
746
05e3f8e7
HS		 747 weim: weim@021b8000 {
748 compatible = "fsl,imx6q-weim";
7d740f87
SG		 749 reg = <0x021b8000 0x4000>;
750 interrupts = <0 14 0x04>;
05e3f8e7 751 clocks = <&clks 196>;
7d740f87
SG		 752 };
753
754 ocotp@021bc000 {
96574a6d 755 compatible = "fsl,imx6q-ocotp";
7d740f87
SG		 756 reg = <0x021bc000 0x4000>;
757 };
758
7d740f87
SG		 759 tzasc@021d0000 { /* TZASC1 */
760 reg = <0x021d0000 0x4000>;
761 interrupts = <0 108 0x04>;
762 };
763
764 tzasc@021d4000 { /* TZASC2 */
765 reg = <0x021d4000 0x4000>;
766 interrupts = <0 109 0x04>;
767 };
768
7b7d6727 769 audmux: audmux@021d8000 {
f965cd55 770 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 771 reg = <0x021d8000 0x4000>;
f965cd55 772 status = "disabled";
7d740f87
SG		 773 };
774
775 mipi@021dc000 { /* MIPI-CSI */
776 reg = <0x021dc000 0x4000>;
777 };
778
779 mipi@021e0000 { /* MIPI-DSI */
780 reg = <0x021e0000 0x4000>;
781 };
782
783 vdoa@021e4000 {
784 reg = <0x021e4000 0x4000>;
785 interrupts = <0 18 0x04>;
786 };
787
0c456cfa 788 uart2: serial@021e8000 {
7d740f87
SG		 789 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
790 reg = <0x021e8000 0x4000>;
791 interrupts = <0 27 0x04>;
0e87e043
SG		 792 clocks = <&clks 160>, <&clks 161>;
793 clock-names = "ipg", "per";
7d740f87
SG		 794 status = "disabled";
795 };
796
0c456cfa 797 uart3: serial@021ec000 {
7d740f87
SG		 798 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
799 reg = <0x021ec000 0x4000>;
800 interrupts = <0 28 0x04>;
0e87e043
SG		 801 clocks = <&clks 160>, <&clks 161>;
802 clock-names = "ipg", "per";
7d740f87
SG		 803 status = "disabled";
804 };
805
0c456cfa 806 uart4: serial@021f0000 {
7d740f87
SG		 807 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
808 reg = <0x021f0000 0x4000>;
809 interrupts = <0 29 0x04>;
0e87e043
SG		 810 clocks = <&clks 160>, <&clks 161>;
811 clock-names = "ipg", "per";
7d740f87
SG		 812 status = "disabled";
813 };
814
0c456cfa 815 uart5: serial@021f4000 {
7d740f87
SG		 816 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
817 reg = <0x021f4000 0x4000>;
818 interrupts = <0 30 0x04>;
0e87e043
SG		 819 clocks = <&clks 160>, <&clks 161>;
820 clock-names = "ipg", "per";
7d740f87
SG		 821 status = "disabled";
822 };
823 };
91660d74
SH		 824
825 ipu1: ipu@02400000 {
826 #crtc-cells = <1>;
827 compatible = "fsl,imx6q-ipu";
828 reg = <0x02400000 0x400000>;
829 interrupts = <0 6 0x4 0 5 0x4>;
830 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
831 clock-names = "bus", "di0", "di1";
09ebf366 832 resets = <&src 2>;
91660d74 833 };
7d740f87
SG		 834 };
835};
Linux kernel - Deliverables
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