projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d740f87 SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 07134a36 LS |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | ||
| 36dffd8f | 15 | #include "skeleton.dtsi" |
| 7d740f87 SG |
16 | |
| 17 | / { | |
| 18 | aliases { | |
| 22970070 | 19 | ethernet0 = &fec; |
| 5f8fbc2c LW |
20 | can0 = &can1; |
| 21 | can1 = &can2; | |
| 5230f8fe SG |
22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | |
| 24 | gpio2 = &gpio3; | |
| 25 | gpio3 = &gpio4; | |
| 26 | gpio4 = &gpio5; | |
| 27 | gpio5 = &gpio6; | |
| 28 | gpio6 = &gpio7; | |
| 80fa0584 SH |
29 | i2c0 = &i2c1; |
| 30 | i2c1 = &i2c2; | |
| 31 | i2c2 = &i2c3; | |
| fb06d65c SH |
32 | mmc0 = &usdhc1; |
| 33 | mmc1 = &usdhc2; | |
| 34 | mmc2 = &usdhc3; | |
| 35 | mmc3 = &usdhc4; | |
| 80fa0584 SH |
36 | serial0 = &uart1; |
| 37 | serial1 = &uart2; | |
| 38 | serial2 = &uart3; | |
| 39 | serial3 = &uart4; | |
| 40 | serial4 = &uart5; | |
| 41 | spi0 = &ecspi1; | |
| 42 | spi1 = &ecspi2; | |
| 43 | spi2 = &ecspi3; | |
| 44 | spi3 = &ecspi4; | |
| 8189c51f PC |
45 | usbphy0 = &usbphy1; |
| 46 | usbphy1 = &usbphy2; | |
| 7d740f87 SG |
47 | }; |
| 48 | ||
| 7d740f87 SG |
49 | intc: interrupt-controller@00a01000 { |
| 50 | compatible = "arm,cortex-a9-gic"; | |
| 51 | #interrupt-cells = <3>; | |
| 7d740f87 SG |
52 | interrupt-controller; |
| 53 | reg = <0x00a01000 0x1000>, | |
| 54 | <0x00a00100 0x100>; | |
| 55 | }; | |
| 56 | ||
| 57 | clocks { | |
| 58 | #address-cells = <1>; | |
| 59 | #size-cells = <0>; | |
| 60 | ||
| 61 | ckil { | |
| 62 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 63 | #clock-cells = <0>; |
| 7d740f87 SG |
64 | clock-frequency = <32768>; |
| 65 | }; | |
| 66 | ||
| 67 | ckih1 { | |
| 68 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 69 | #clock-cells = <0>; |
| 7d740f87 SG |
70 | clock-frequency = <0>; |
| 71 | }; | |
| 72 | ||
| 73 | osc { | |
| 74 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 75 | #clock-cells = <0>; |
| 7d740f87 SG |
76 | clock-frequency = <24000000>; |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| 80 | soc { | |
| 81 | #address-cells = <1>; | |
| 82 | #size-cells = <1>; | |
| 83 | compatible = "simple-bus"; | |
| 84 | interrupt-parent = <&intc>; | |
| 85 | ranges; | |
| 86 | ||
| f30fb03d | 87 | dma_apbh: dma-apbh@00110000 { |
| e5d0f9f5 HS |
88 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 89 | reg = <0x00110000 0x2000>; | |
| 275c08b5 TK |
90 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 91 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 92 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 93 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
| f30fb03d SG |
94 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 95 | #dma-cells = <1>; | |
| 96 | dma-channels = <4>; | |
| 0e87e043 | 97 | clocks = <&clks 106>; |
| e5d0f9f5 HS |
98 | }; |
| 99 | ||
| be4ccfce | 100 | gpmi: gpmi-nand@00112000 { |
| 0e87e043 SG |
101 | compatible = "fsl,imx6q-gpmi-nand"; |
| 102 | #address-cells = <1>; | |
| 103 | #size-cells = <1>; | |
| 104 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
| 105 | reg-names = "gpmi-nand", "bch"; | |
| 275c08b5 | 106 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
| c7aa12a6 | 107 | interrupt-names = "bch"; |
| 0e87e043 SG |
108 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 109 | <&clks 150>, <&clks 149>; | |
| 110 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
| 111 | "gpmi_bch_apb", "per1_bch"; | |
| f30fb03d SG |
112 | dmas = <&dma_apbh 0>; |
| 113 | dma-names = "rx-tx"; | |
| 0e87e043 | 114 | status = "disabled"; |
| cf922fa8 HS |
115 | }; |
| 116 | ||
| 7d740f87 | 117 | timer@00a00600 { |
| 58458e03 MZ |
118 | compatible = "arm,cortex-a9-twd-timer"; |
| 119 | reg = <0x00a00600 0x20>; | |
| 120 | interrupts = <1 13 0xf01>; | |
| 2bb4b70b | 121 | clocks = <&clks 15>; |
| 7d740f87 SG |
122 | }; |
| 123 | ||
| 124 | L2: l2-cache@00a02000 { | |
| 125 | compatible = "arm,pl310-cache"; | |
| 126 | reg = <0x00a02000 0x1000>; | |
| 275c08b5 | 127 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
128 | cache-unified; |
| 129 | cache-level = <2>; | |
| 5a5ca56e DB |
130 | arm,tag-latency = <4 2 3>; |
| 131 | arm,data-latency = <4 2 3>; | |
| 7d740f87 SG |
132 | }; |
| 133 | ||
| 3a57291f SC |
134 | pcie: pcie@0x01000000 { |
| 135 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
| 136 | reg = <0x01ffc000 0x4000>; /* DBI */ | |
| 137 | #address-cells = <3>; | |
| 138 | #size-cells = <2>; | |
| 139 | device_type = "pci"; | |
| 140 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
| 141 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
| 142 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
| 143 | num-lanes = <1>; | |
| 275c08b5 | 144 | interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; |
| 07134a36 LS |
145 | #interrupt-cells = <1>; |
| 146 | interrupt-map-mask = <0 0 0 0x7>; | |
| 147 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 148 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 149 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 150 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
| 3a57291f SC |
151 | clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; |
| 152 | clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; | |
| 153 | status = "disabled"; | |
| 154 | }; | |
| 155 | ||
| 218abe6f DB |
156 | pmu { |
| 157 | compatible = "arm,cortex-a9-pmu"; | |
| 275c08b5 | 158 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| 218abe6f DB |
159 | }; |
| 160 | ||
| 7d740f87 SG |
161 | aips-bus@02000000 { /* AIPS1 */ |
| 162 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 163 | #address-cells = <1>; | |
| 164 | #size-cells = <1>; | |
| 165 | reg = <0x02000000 0x100000>; | |
| 166 | ranges; | |
| 167 | ||
| 168 | spba-bus@02000000 { | |
| 169 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 170 | #address-cells = <1>; | |
| 171 | #size-cells = <1>; | |
| 172 | reg = <0x02000000 0x40000>; | |
| 173 | ranges; | |
| 174 | ||
| 7b7d6727 | 175 | spdif: spdif@02004000 { |
| c9d96df2 | 176 | compatible = "fsl,imx35-spdif"; |
| 7d740f87 | 177 | reg = <0x02004000 0x4000>; |
| 275c08b5 | 178 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| c9d96df2 FE |
179 | dmas = <&sdma 14 18 0>, |
| 180 | <&sdma 15 18 0>; | |
| 181 | dma-names = "rx", "tx"; | |
| 182 | clocks = <&clks 197>, <&clks 3>, | |
| 183 | <&clks 197>, <&clks 107>, | |
| 184 | <&clks 0>, <&clks 118>, | |
| 793b4b10 | 185 | <&clks 0>, <&clks 139>, |
| c9d96df2 FE |
186 | <&clks 0>; |
| 187 | clock-names = "core", "rxtx0", | |
| 188 | "rxtx1", "rxtx2", | |
| 189 | "rxtx3", "rxtx4", | |
| 190 | "rxtx5", "rxtx6", | |
| 191 | "rxtx7"; | |
| 192 | status = "disabled"; | |
| 7d740f87 SG |
193 | }; |
| 194 | ||
| 7b7d6727 | 195 | ecspi1: ecspi@02008000 { |
| 7d740f87 SG |
196 | #address-cells = <1>; |
| 197 | #size-cells = <0>; | |
| 198 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 199 | reg = <0x02008000 0x4000>; | |
| 275c08b5 | 200 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
201 | clocks = <&clks 112>, <&clks 112>; |
| 202 | clock-names = "ipg", "per"; | |
| b3810c3d FL |
203 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; |
| 204 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
205 | status = "disabled"; |
| 206 | }; | |
| 207 | ||
| 7b7d6727 | 208 | ecspi2: ecspi@0200c000 { |
| 7d740f87 SG |
209 | #address-cells = <1>; |
| 210 | #size-cells = <0>; | |
| 211 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 212 | reg = <0x0200c000 0x4000>; | |
| 275c08b5 | 213 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
214 | clocks = <&clks 113>, <&clks 113>; |
| 215 | clock-names = "ipg", "per"; | |
| b3810c3d FL |
216 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; |
| 217 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
218 | status = "disabled"; |
| 219 | }; | |
| 220 | ||
| 7b7d6727 | 221 | ecspi3: ecspi@02010000 { |
| 7d740f87 SG |
222 | #address-cells = <1>; |
| 223 | #size-cells = <0>; | |
| 224 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 225 | reg = <0x02010000 0x4000>; | |
| 275c08b5 | 226 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
227 | clocks = <&clks 114>, <&clks 114>; |
| 228 | clock-names = "ipg", "per"; | |
| b3810c3d FL |
229 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; |
| 230 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
231 | status = "disabled"; |
| 232 | }; | |
| 233 | ||
| 7b7d6727 | 234 | ecspi4: ecspi@02014000 { |
| 7d740f87 SG |
235 | #address-cells = <1>; |
| 236 | #size-cells = <0>; | |
| 237 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 238 | reg = <0x02014000 0x4000>; | |
| 275c08b5 | 239 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
240 | clocks = <&clks 115>, <&clks 115>; |
| 241 | clock-names = "ipg", "per"; | |
| b3810c3d FL |
242 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; |
| 243 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
244 | status = "disabled"; |
| 245 | }; | |
| 246 | ||
| 0c456cfa | 247 | uart1: serial@02020000 { |
| 7d740f87 SG |
248 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 249 | reg = <0x02020000 0x4000>; | |
| 275c08b5 | 250 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
251 | clocks = <&clks 160>, <&clks 161>; |
| 252 | clock-names = "ipg", "per"; | |
| 72a5cebf HS |
253 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| 254 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
255 | status = "disabled"; |
| 256 | }; | |
| 257 | ||
| 7b7d6727 | 258 | esai: esai@02024000 { |
| 7d740f87 | 259 | reg = <0x02024000 0x4000>; |
| 275c08b5 | 260 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
261 | }; |
| 262 | ||
| b1a5da8e | 263 | ssi1: ssi@02028000 { |
| 98ea6ad2 MP |
264 | compatible = "fsl,imx6q-ssi", |
| 265 | "fsl,imx51-ssi", | |
| 266 | "fsl,imx21-ssi"; | |
| 7d740f87 | 267 | reg = <0x02028000 0x4000>; |
| 275c08b5 | 268 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 269 | clocks = <&clks 178>; |
| 5da826ab SG |
270 | dmas = <&sdma 37 1 0>, |
| 271 | <&sdma 38 1 0>; | |
| 272 | dma-names = "rx", "tx"; | |
| b1a5da8e RZ |
273 | fsl,fifo-depth = <15>; |
| 274 | fsl,ssi-dma-events = <38 37>; | |
| 275 | status = "disabled"; | |
| 7d740f87 SG |
276 | }; |
| 277 | ||
| b1a5da8e | 278 | ssi2: ssi@0202c000 { |
| 98ea6ad2 MP |
279 | compatible = "fsl,imx6q-ssi", |
| 280 | "fsl,imx51-ssi", | |
| 281 | "fsl,imx21-ssi"; | |
| 7d740f87 | 282 | reg = <0x0202c000 0x4000>; |
| 275c08b5 | 283 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 284 | clocks = <&clks 179>; |
| 5da826ab SG |
285 | dmas = <&sdma 41 1 0>, |
| 286 | <&sdma 42 1 0>; | |
| 287 | dma-names = "rx", "tx"; | |
| b1a5da8e RZ |
288 | fsl,fifo-depth = <15>; |
| 289 | fsl,ssi-dma-events = <42 41>; | |
| 290 | status = "disabled"; | |
| 7d740f87 SG |
291 | }; |
| 292 | ||
| b1a5da8e | 293 | ssi3: ssi@02030000 { |
| 98ea6ad2 MP |
294 | compatible = "fsl,imx6q-ssi", |
| 295 | "fsl,imx51-ssi", | |
| 296 | "fsl,imx21-ssi"; | |
| 7d740f87 | 297 | reg = <0x02030000 0x4000>; |
| 275c08b5 | 298 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 299 | clocks = <&clks 180>; |
| 5da826ab SG |
300 | dmas = <&sdma 45 1 0>, |
| 301 | <&sdma 46 1 0>; | |
| 302 | dma-names = "rx", "tx"; | |
| b1a5da8e RZ |
303 | fsl,fifo-depth = <15>; |
| 304 | fsl,ssi-dma-events = <46 45>; | |
| 305 | status = "disabled"; | |
| 7d740f87 SG |
306 | }; |
| 307 | ||
| 7b7d6727 | 308 | asrc: asrc@02034000 { |
| 7d740f87 | 309 | reg = <0x02034000 0x4000>; |
| 275c08b5 | 310 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
311 | }; |
| 312 | ||
| 313 | spba@0203c000 { | |
| 314 | reg = <0x0203c000 0x4000>; | |
| 315 | }; | |
| 316 | }; | |
| 317 | ||
| 7b7d6727 | 318 | vpu: vpu@02040000 { |
| 7d740f87 | 319 | reg = <0x02040000 0x3c000>; |
| 275c08b5 TK |
320 | interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 321 | <0 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
322 | }; |
| 323 | ||
| 324 | aipstz@0207c000 { /* AIPSTZ1 */ | |
| 325 | reg = <0x0207c000 0x4000>; | |
| 326 | }; | |
| 327 | ||
| 7b7d6727 | 328 | pwm1: pwm@02080000 { |
| 33b38587 SH |
329 | #pwm-cells = <2>; |
| 330 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 331 | reg = <0x02080000 0x4000>; |
| 275c08b5 | 332 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| 33b38587 SH |
333 | clocks = <&clks 62>, <&clks 145>; |
| 334 | clock-names = "ipg", "per"; | |
| 7d740f87 SG |
335 | }; |
| 336 | ||
| 7b7d6727 | 337 | pwm2: pwm@02084000 { |
| 33b38587 SH |
338 | #pwm-cells = <2>; |
| 339 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 340 | reg = <0x02084000 0x4000>; |
| 275c08b5 | 341 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| 33b38587 SH |
342 | clocks = <&clks 62>, <&clks 146>; |
| 343 | clock-names = "ipg", "per"; | |
| 7d740f87 SG |
344 | }; |
| 345 | ||
| 7b7d6727 | 346 | pwm3: pwm@02088000 { |
| 33b38587 SH |
347 | #pwm-cells = <2>; |
| 348 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 349 | reg = <0x02088000 0x4000>; |
| 275c08b5 | 350 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| 33b38587 SH |
351 | clocks = <&clks 62>, <&clks 147>; |
| 352 | clock-names = "ipg", "per"; | |
| 7d740f87 SG |
353 | }; |
| 354 | ||
| 7b7d6727 | 355 | pwm4: pwm@0208c000 { |
| 33b38587 SH |
356 | #pwm-cells = <2>; |
| 357 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 358 | reg = <0x0208c000 0x4000>; |
| 275c08b5 | 359 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 33b38587 SH |
360 | clocks = <&clks 62>, <&clks 148>; |
| 361 | clock-names = "ipg", "per"; | |
| 7d740f87 SG |
362 | }; |
| 363 | ||
| 7b7d6727 | 364 | can1: flexcan@02090000 { |
| 0f225212 | 365 | compatible = "fsl,imx6q-flexcan"; |
| 7d740f87 | 366 | reg = <0x02090000 0x4000>; |
| 275c08b5 | 367 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
| 0f225212 SH |
368 | clocks = <&clks 108>, <&clks 109>; |
| 369 | clock-names = "ipg", "per"; | |
| a1135337 | 370 | status = "disabled"; |
| 7d740f87 SG |
371 | }; |
| 372 | ||
| 7b7d6727 | 373 | can2: flexcan@02094000 { |
| 0f225212 | 374 | compatible = "fsl,imx6q-flexcan"; |
| 7d740f87 | 375 | reg = <0x02094000 0x4000>; |
| 275c08b5 | 376 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
| 0f225212 SH |
377 | clocks = <&clks 110>, <&clks 111>; |
| 378 | clock-names = "ipg", "per"; | |
| a1135337 | 379 | status = "disabled"; |
| 7d740f87 SG |
380 | }; |
| 381 | ||
| 7b7d6727 | 382 | gpt: gpt@02098000 { |
| 97b108f9 | 383 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
| 7d740f87 | 384 | reg = <0x02098000 0x4000>; |
| 275c08b5 | 385 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| 4efccadd SH |
386 | clocks = <&clks 119>, <&clks 120>; |
| 387 | clock-names = "ipg", "per"; | |
| 7d740f87 SG |
388 | }; |
| 389 | ||
| 4d191868 | 390 | gpio1: gpio@0209c000 { |
| aeb27748 | 391 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 392 | reg = <0x0209c000 0x4000>; |
| 275c08b5 TK |
393 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| 394 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
395 | gpio-controller; |
| 396 | #gpio-cells = <2>; | |
| 397 | interrupt-controller; | |
| 88cde8b7 | 398 | #interrupt-cells = <2>; |
| 7d740f87 SG |
399 | }; |
| 400 | ||
| 4d191868 | 401 | gpio2: gpio@020a0000 { |
| aeb27748 | 402 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 403 | reg = <0x020a0000 0x4000>; |
| 275c08b5 TK |
404 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| 405 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
406 | gpio-controller; |
| 407 | #gpio-cells = <2>; | |
| 408 | interrupt-controller; | |
| 88cde8b7 | 409 | #interrupt-cells = <2>; |
| 7d740f87 SG |
410 | }; |
| 411 | ||
| 4d191868 | 412 | gpio3: gpio@020a4000 { |
| aeb27748 | 413 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 414 | reg = <0x020a4000 0x4000>; |
| 275c08b5 TK |
415 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| 416 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
417 | gpio-controller; |
| 418 | #gpio-cells = <2>; | |
| 419 | interrupt-controller; | |
| 88cde8b7 | 420 | #interrupt-cells = <2>; |
| 7d740f87 SG |
421 | }; |
| 422 | ||
| 4d191868 | 423 | gpio4: gpio@020a8000 { |
| aeb27748 | 424 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 425 | reg = <0x020a8000 0x4000>; |
| 275c08b5 TK |
426 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| 427 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
428 | gpio-controller; |
| 429 | #gpio-cells = <2>; | |
| 430 | interrupt-controller; | |
| 88cde8b7 | 431 | #interrupt-cells = <2>; |
| 7d740f87 SG |
432 | }; |
| 433 | ||
| 4d191868 | 434 | gpio5: gpio@020ac000 { |
| aeb27748 | 435 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 436 | reg = <0x020ac000 0x4000>; |
| 275c08b5 TK |
437 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| 438 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
439 | gpio-controller; |
| 440 | #gpio-cells = <2>; | |
| 441 | interrupt-controller; | |
| 88cde8b7 | 442 | #interrupt-cells = <2>; |
| 7d740f87 SG |
443 | }; |
| 444 | ||
| 4d191868 | 445 | gpio6: gpio@020b0000 { |
| aeb27748 | 446 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 447 | reg = <0x020b0000 0x4000>; |
| 275c08b5 TK |
448 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
| 449 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
450 | gpio-controller; |
| 451 | #gpio-cells = <2>; | |
| 452 | interrupt-controller; | |
| 88cde8b7 | 453 | #interrupt-cells = <2>; |
| 7d740f87 SG |
454 | }; |
| 455 | ||
| 4d191868 | 456 | gpio7: gpio@020b4000 { |
| aeb27748 | 457 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 458 | reg = <0x020b4000 0x4000>; |
| 275c08b5 TK |
459 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
| 460 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
461 | gpio-controller; |
| 462 | #gpio-cells = <2>; | |
| 463 | interrupt-controller; | |
| 88cde8b7 | 464 | #interrupt-cells = <2>; |
| 7d740f87 SG |
465 | }; |
| 466 | ||
| 7b7d6727 | 467 | kpp: kpp@020b8000 { |
| 7d740f87 | 468 | reg = <0x020b8000 0x4000>; |
| 275c08b5 | 469 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
470 | }; |
| 471 | ||
| 7b7d6727 | 472 | wdog1: wdog@020bc000 { |
| 7d740f87 SG |
473 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 474 | reg = <0x020bc000 0x4000>; | |
| 275c08b5 | 475 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 476 | clocks = <&clks 0>; |
| 7d740f87 SG |
477 | }; |
| 478 | ||
| 7b7d6727 | 479 | wdog2: wdog@020c0000 { |
| 7d740f87 SG |
480 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 481 | reg = <0x020c0000 0x4000>; | |
| 275c08b5 | 482 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 483 | clocks = <&clks 0>; |
| 7d740f87 SG |
484 | status = "disabled"; |
| 485 | }; | |
| 486 | ||
| 0e87e043 | 487 | clks: ccm@020c4000 { |
| 7d740f87 SG |
488 | compatible = "fsl,imx6q-ccm"; |
| 489 | reg = <0x020c4000 0x4000>; | |
| 275c08b5 TK |
490 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| 491 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
| 0e87e043 | 492 | #clock-cells = <1>; |
| 7d740f87 SG |
493 | }; |
| 494 | ||
| baa64151 DA |
495 | anatop: anatop@020c8000 { |
| 496 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
| 7d740f87 | 497 | reg = <0x020c8000 0x1000>; |
| 275c08b5 TK |
498 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| 499 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 500 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
| a1e327e6 YCLP |
501 | |
| 502 | regulator-1p1@110 { | |
| 503 | compatible = "fsl,anatop-regulator"; | |
| 504 | regulator-name = "vdd1p1"; | |
| 505 | regulator-min-microvolt = <800000>; | |
| 506 | regulator-max-microvolt = <1375000>; | |
| 507 | regulator-always-on; | |
| 508 | anatop-reg-offset = <0x110>; | |
| 509 | anatop-vol-bit-shift = <8>; | |
| 510 | anatop-vol-bit-width = <5>; | |
| 511 | anatop-min-bit-val = <4>; | |
| 512 | anatop-min-voltage = <800000>; | |
| 513 | anatop-max-voltage = <1375000>; | |
| 514 | }; | |
| 515 | ||
| 516 | regulator-3p0@120 { | |
| 517 | compatible = "fsl,anatop-regulator"; | |
| 518 | regulator-name = "vdd3p0"; | |
| 519 | regulator-min-microvolt = <2800000>; | |
| 520 | regulator-max-microvolt = <3150000>; | |
| 521 | regulator-always-on; | |
| 522 | anatop-reg-offset = <0x120>; | |
| 523 | anatop-vol-bit-shift = <8>; | |
| 524 | anatop-vol-bit-width = <5>; | |
| 525 | anatop-min-bit-val = <0>; | |
| 526 | anatop-min-voltage = <2625000>; | |
| 527 | anatop-max-voltage = <3400000>; | |
| 528 | }; | |
| 529 | ||
| 530 | regulator-2p5@130 { | |
| 531 | compatible = "fsl,anatop-regulator"; | |
| 532 | regulator-name = "vdd2p5"; | |
| 533 | regulator-min-microvolt = <2000000>; | |
| 534 | regulator-max-microvolt = <2750000>; | |
| 535 | regulator-always-on; | |
| 536 | anatop-reg-offset = <0x130>; | |
| 537 | anatop-vol-bit-shift = <8>; | |
| 538 | anatop-vol-bit-width = <5>; | |
| 539 | anatop-min-bit-val = <0>; | |
| 540 | anatop-min-voltage = <2000000>; | |
| 541 | anatop-max-voltage = <2750000>; | |
| 542 | }; | |
| 543 | ||
| 96574a6d | 544 | reg_arm: regulator-vddcore@140 { |
| a1e327e6 | 545 | compatible = "fsl,anatop-regulator"; |
| 118c98a6 | 546 | regulator-name = "vddarm"; |
| a1e327e6 YCLP |
547 | regulator-min-microvolt = <725000>; |
| 548 | regulator-max-microvolt = <1450000>; | |
| 549 | regulator-always-on; | |
| 550 | anatop-reg-offset = <0x140>; | |
| 551 | anatop-vol-bit-shift = <0>; | |
| 552 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
553 | anatop-delay-reg-offset = <0x170>; |
| 554 | anatop-delay-bit-shift = <24>; | |
| 555 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
556 | anatop-min-bit-val = <1>; |
| 557 | anatop-min-voltage = <725000>; | |
| 558 | anatop-max-voltage = <1450000>; | |
| 559 | }; | |
| 560 | ||
| 96574a6d | 561 | reg_pu: regulator-vddpu@140 { |
| a1e327e6 YCLP |
562 | compatible = "fsl,anatop-regulator"; |
| 563 | regulator-name = "vddpu"; | |
| 564 | regulator-min-microvolt = <725000>; | |
| 565 | regulator-max-microvolt = <1450000>; | |
| 566 | regulator-always-on; | |
| 567 | anatop-reg-offset = <0x140>; | |
| 568 | anatop-vol-bit-shift = <9>; | |
| 569 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
570 | anatop-delay-reg-offset = <0x170>; |
| 571 | anatop-delay-bit-shift = <26>; | |
| 572 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
573 | anatop-min-bit-val = <1>; |
| 574 | anatop-min-voltage = <725000>; | |
| 575 | anatop-max-voltage = <1450000>; | |
| 576 | }; | |
| 577 | ||
| 96574a6d | 578 | reg_soc: regulator-vddsoc@140 { |
| a1e327e6 YCLP |
579 | compatible = "fsl,anatop-regulator"; |
| 580 | regulator-name = "vddsoc"; | |
| 581 | regulator-min-microvolt = <725000>; | |
| 582 | regulator-max-microvolt = <1450000>; | |
| 583 | regulator-always-on; | |
| 584 | anatop-reg-offset = <0x140>; | |
| 585 | anatop-vol-bit-shift = <18>; | |
| 586 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
587 | anatop-delay-reg-offset = <0x170>; |
| 588 | anatop-delay-bit-shift = <28>; | |
| 589 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
590 | anatop-min-bit-val = <1>; |
| 591 | anatop-min-voltage = <725000>; | |
| 592 | anatop-max-voltage = <1450000>; | |
| 593 | }; | |
| 7d740f87 SG |
594 | }; |
| 595 | ||
| 3fe6373b SG |
596 | tempmon: tempmon { |
| 597 | compatible = "fsl,imx6q-tempmon"; | |
| 275c08b5 | 598 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
| 3fe6373b SG |
599 | fsl,tempmon = <&anatop>; |
| 600 | fsl,tempmon-data = <&ocotp>; | |
| f430d19c | 601 | clocks = <&clks 172>; |
| 3fe6373b SG |
602 | }; |
| 603 | ||
| 74bd88f7 RZ |
604 | usbphy1: usbphy@020c9000 { |
| 605 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
| 7d740f87 | 606 | reg = <0x020c9000 0x1000>; |
| 275c08b5 | 607 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 608 | clocks = <&clks 182>; |
| 76a38855 | 609 | fsl,anatop = <&anatop>; |
| 7d740f87 SG |
610 | }; |
| 611 | ||
| 74bd88f7 RZ |
612 | usbphy2: usbphy@020ca000 { |
| 613 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
| 7d740f87 | 614 | reg = <0x020ca000 0x1000>; |
| 275c08b5 | 615 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 616 | clocks = <&clks 183>; |
| 76a38855 | 617 | fsl,anatop = <&anatop>; |
| 7d740f87 SG |
618 | }; |
| 619 | ||
| 620 | snvs@020cc000 { | |
| c9250388 SG |
621 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 622 | #address-cells = <1>; | |
| 623 | #size-cells = <1>; | |
| 624 | ranges = <0 0x020cc000 0x4000>; | |
| 625 | ||
| 626 | snvs-rtc-lp@34 { | |
| 627 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
| 628 | reg = <0x34 0x58>; | |
| 275c08b5 TK |
629 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 630 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
| c9250388 | 631 | }; |
| 7d740f87 SG |
632 | }; |
| 633 | ||
| 7b7d6727 | 634 | epit1: epit@020d0000 { /* EPIT1 */ |
| 7d740f87 | 635 | reg = <0x020d0000 0x4000>; |
| 275c08b5 | 636 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
637 | }; |
| 638 | ||
| 7b7d6727 | 639 | epit2: epit@020d4000 { /* EPIT2 */ |
| 7d740f87 | 640 | reg = <0x020d4000 0x4000>; |
| 275c08b5 | 641 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
642 | }; |
| 643 | ||
| 7b7d6727 | 644 | src: src@020d8000 { |
| bd3d924d | 645 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
| 7d740f87 | 646 | reg = <0x020d8000 0x4000>; |
| 275c08b5 TK |
647 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| 648 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 09ebf366 | 649 | #reset-cells = <1>; |
| 7d740f87 SG |
650 | }; |
| 651 | ||
| 7b7d6727 | 652 | gpc: gpc@020dc000 { |
| 7d740f87 SG |
653 | compatible = "fsl,imx6q-gpc"; |
| 654 | reg = <0x020dc000 0x4000>; | |
| 275c08b5 TK |
655 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
| 656 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
657 | }; |
| 658 | ||
| df37e0c0 DA |
659 | gpr: iomuxc-gpr@020e0000 { |
| 660 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
| 661 | reg = <0x020e0000 0x38>; | |
| 662 | }; | |
| 663 | ||
| c56009b2 SG |
664 | iomuxc: iomuxc@020e0000 { |
| 665 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
| 666 | reg = <0x020e0000 0x4000>; | |
| c56009b2 SG |
667 | }; |
| 668 | ||
| 41c04342 ST |
669 | ldb: ldb@020e0008 { |
| 670 | #address-cells = <1>; | |
| 671 | #size-cells = <0>; | |
| 672 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
| 673 | gpr = <&gpr>; | |
| 674 | status = "disabled"; | |
| 675 | ||
| 676 | lvds-channel@0 { | |
| 4520e692 PZ |
677 | #address-cells = <1>; |
| 678 | #size-cells = <0>; | |
| 41c04342 | 679 | reg = <0>; |
| 41c04342 | 680 | status = "disabled"; |
| 4520e692 PZ |
681 | |
| 682 | port@0 { | |
| 683 | reg = <0>; | |
| 684 | ||
| 685 | lvds0_mux_0: endpoint { | |
| 686 | remote-endpoint = <&ipu1_di0_lvds0>; | |
| 687 | }; | |
| 688 | }; | |
| 689 | ||
| 690 | port@1 { | |
| 691 | reg = <1>; | |
| 692 | ||
| 693 | lvds0_mux_1: endpoint { | |
| 694 | remote-endpoint = <&ipu1_di1_lvds0>; | |
| 695 | }; | |
| 696 | }; | |
| 41c04342 ST |
697 | }; |
| 698 | ||
| 699 | lvds-channel@1 { | |
| 4520e692 PZ |
700 | #address-cells = <1>; |
| 701 | #size-cells = <0>; | |
| 41c04342 | 702 | reg = <1>; |
| 41c04342 | 703 | status = "disabled"; |
| 4520e692 PZ |
704 | |
| 705 | port@0 { | |
| 706 | reg = <0>; | |
| 707 | ||
| 708 | lvds1_mux_0: endpoint { | |
| 709 | remote-endpoint = <&ipu1_di0_lvds1>; | |
| 710 | }; | |
| 711 | }; | |
| 712 | ||
| 713 | port@1 { | |
| 714 | reg = <1>; | |
| 715 | ||
| 716 | lvds1_mux_1: endpoint { | |
| 717 | remote-endpoint = <&ipu1_di1_lvds1>; | |
| 718 | }; | |
| 719 | }; | |
| 41c04342 ST |
720 | }; |
| 721 | }; | |
| 722 | ||
| 04cec1a2 | 723 | hdmi: hdmi@0120000 { |
| 4520e692 PZ |
724 | #address-cells = <1>; |
| 725 | #size-cells = <0>; | |
| 04cec1a2 RK |
726 | reg = <0x00120000 0x9000>; |
| 727 | interrupts = <0 115 0x04>; | |
| 728 | gpr = <&gpr>; | |
| 729 | clocks = <&clks 123>, <&clks 124>; | |
| 730 | clock-names = "iahb", "isfr"; | |
| 731 | status = "disabled"; | |
| 4520e692 PZ |
732 | |
| 733 | port@0 { | |
| 734 | reg = <0>; | |
| 735 | ||
| 736 | hdmi_mux_0: endpoint { | |
| 737 | remote-endpoint = <&ipu1_di0_hdmi>; | |
| 738 | }; | |
| 739 | }; | |
| 740 | ||
| 741 | port@1 { | |
| 742 | reg = <1>; | |
| 743 | ||
| 744 | hdmi_mux_1: endpoint { | |
| 745 | remote-endpoint = <&ipu1_di1_hdmi>; | |
| 746 | }; | |
| 747 | }; | |
| 04cec1a2 RK |
748 | }; |
| 749 | ||
| 7b7d6727 | 750 | dcic1: dcic@020e4000 { |
| 7d740f87 | 751 | reg = <0x020e4000 0x4000>; |
| 275c08b5 | 752 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
753 | }; |
| 754 | ||
| 7b7d6727 | 755 | dcic2: dcic@020e8000 { |
| 7d740f87 | 756 | reg = <0x020e8000 0x4000>; |
| 275c08b5 | 757 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
758 | }; |
| 759 | ||
| 7b7d6727 | 760 | sdma: sdma@020ec000 { |
| 7d740f87 SG |
761 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 762 | reg = <0x020ec000 0x4000>; | |
| 275c08b5 | 763 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
764 | clocks = <&clks 155>, <&clks 155>; |
| 765 | clock-names = "ipg", "ahb"; | |
| fb72bb21 | 766 | #dma-cells = <3>; |
| d6b9c591 | 767 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| 7d740f87 SG |
768 | }; |
| 769 | }; | |
| 770 | ||
| 771 | aips-bus@02100000 { /* AIPS2 */ | |
| 772 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 773 | #address-cells = <1>; | |
| 774 | #size-cells = <1>; | |
| 775 | reg = <0x02100000 0x100000>; | |
| 776 | ranges; | |
| 777 | ||
| 778 | caam@02100000 { | |
| 779 | reg = <0x02100000 0x40000>; | |
| 275c08b5 TK |
780 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, |
| 781 | <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
782 | }; |
| 783 | ||
| 784 | aipstz@0217c000 { /* AIPSTZ2 */ | |
| 785 | reg = <0x0217c000 0x4000>; | |
| 786 | }; | |
| 787 | ||
| 7b7d6727 | 788 | usbotg: usb@02184000 { |
| 74bd88f7 RZ |
789 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 790 | reg = <0x02184000 0x200>; | |
| 275c08b5 | 791 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 792 | clocks = <&clks 162>; |
| 74bd88f7 | 793 | fsl,usbphy = <&usbphy1>; |
| 28342c61 | 794 | fsl,usbmisc = <&usbmisc 0>; |
| 74bd88f7 RZ |
795 | status = "disabled"; |
| 796 | }; | |
| 797 | ||
| 7b7d6727 | 798 | usbh1: usb@02184200 { |
| 74bd88f7 RZ |
799 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 800 | reg = <0x02184200 0x200>; | |
| 275c08b5 | 801 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 802 | clocks = <&clks 162>; |
| 74bd88f7 | 803 | fsl,usbphy = <&usbphy2>; |
| 28342c61 | 804 | fsl,usbmisc = <&usbmisc 1>; |
| 74bd88f7 RZ |
805 | status = "disabled"; |
| 806 | }; | |
| 807 | ||
| 7b7d6727 | 808 | usbh2: usb@02184400 { |
| 74bd88f7 RZ |
809 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 810 | reg = <0x02184400 0x200>; | |
| 275c08b5 | 811 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 812 | clocks = <&clks 162>; |
| 28342c61 | 813 | fsl,usbmisc = <&usbmisc 2>; |
| 74bd88f7 RZ |
814 | status = "disabled"; |
| 815 | }; | |
| 816 | ||
| 7b7d6727 | 817 | usbh3: usb@02184600 { |
| 74bd88f7 RZ |
818 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 819 | reg = <0x02184600 0x200>; | |
| 275c08b5 | 820 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 821 | clocks = <&clks 162>; |
| 28342c61 | 822 | fsl,usbmisc = <&usbmisc 3>; |
| 74bd88f7 RZ |
823 | status = "disabled"; |
| 824 | }; | |
| 825 | ||
| 60984bdf | 826 | usbmisc: usbmisc@02184800 { |
| 28342c61 RZ |
827 | #index-cells = <1>; |
| 828 | compatible = "fsl,imx6q-usbmisc"; | |
| 829 | reg = <0x02184800 0x200>; | |
| 830 | clocks = <&clks 162>; | |
| 831 | }; | |
| 832 | ||
| 7b7d6727 | 833 | fec: ethernet@02188000 { |
| 7d740f87 SG |
834 | compatible = "fsl,imx6q-fec"; |
| 835 | reg = <0x02188000 0x4000>; | |
| 454cf8f5 TK |
836 | interrupts-extended = |
| 837 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 838 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
| 8dd5c66b | 839 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
| 7629838c | 840 | clock-names = "ipg", "ahb", "ptp"; |
| 7d740f87 SG |
841 | status = "disabled"; |
| 842 | }; | |
| 843 | ||
| 844 | mlb@0218c000 { | |
| 845 | reg = <0x0218c000 0x4000>; | |
| 275c08b5 TK |
846 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
| 847 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 848 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
849 | }; |
| 850 | ||
| 7b7d6727 | 851 | usdhc1: usdhc@02190000 { |
| 7d740f87 SG |
852 | compatible = "fsl,imx6q-usdhc"; |
| 853 | reg = <0x02190000 0x4000>; | |
| 275c08b5 | 854 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
855 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| 856 | clock-names = "ipg", "ahb", "per"; | |
| c104b6a2 | 857 | bus-width = <4>; |
| 7d740f87 SG |
858 | status = "disabled"; |
| 859 | }; | |
| 860 | ||
| 7b7d6727 | 861 | usdhc2: usdhc@02194000 { |
| 7d740f87 SG |
862 | compatible = "fsl,imx6q-usdhc"; |
| 863 | reg = <0x02194000 0x4000>; | |
| 275c08b5 | 864 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
865 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| 866 | clock-names = "ipg", "ahb", "per"; | |
| c104b6a2 | 867 | bus-width = <4>; |
| 7d740f87 SG |
868 | status = "disabled"; |
| 869 | }; | |
| 870 | ||
| 7b7d6727 | 871 | usdhc3: usdhc@02198000 { |
| 7d740f87 SG |
872 | compatible = "fsl,imx6q-usdhc"; |
| 873 | reg = <0x02198000 0x4000>; | |
| 275c08b5 | 874 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
875 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| 876 | clock-names = "ipg", "ahb", "per"; | |
| c104b6a2 | 877 | bus-width = <4>; |
| 7d740f87 SG |
878 | status = "disabled"; |
| 879 | }; | |
| 880 | ||
| 7b7d6727 | 881 | usdhc4: usdhc@0219c000 { |
| 7d740f87 SG |
882 | compatible = "fsl,imx6q-usdhc"; |
| 883 | reg = <0x0219c000 0x4000>; | |
| 275c08b5 | 884 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
885 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| 886 | clock-names = "ipg", "ahb", "per"; | |
| c104b6a2 | 887 | bus-width = <4>; |
| 7d740f87 SG |
888 | status = "disabled"; |
| 889 | }; | |
| 890 | ||
| 7b7d6727 | 891 | i2c1: i2c@021a0000 { |
| 7d740f87 SG |
892 | #address-cells = <1>; |
| 893 | #size-cells = <0>; | |
| 5bdfba29 | 894 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 895 | reg = <0x021a0000 0x4000>; |
| 275c08b5 | 896 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 897 | clocks = <&clks 125>; |
| 7d740f87 SG |
898 | status = "disabled"; |
| 899 | }; | |
| 900 | ||
| 7b7d6727 | 901 | i2c2: i2c@021a4000 { |
| 7d740f87 SG |
902 | #address-cells = <1>; |
| 903 | #size-cells = <0>; | |
| 5bdfba29 | 904 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 905 | reg = <0x021a4000 0x4000>; |
| 275c08b5 | 906 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 907 | clocks = <&clks 126>; |
| 7d740f87 SG |
908 | status = "disabled"; |
| 909 | }; | |
| 910 | ||
| 7b7d6727 | 911 | i2c3: i2c@021a8000 { |
| 7d740f87 SG |
912 | #address-cells = <1>; |
| 913 | #size-cells = <0>; | |
| 5bdfba29 | 914 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 915 | reg = <0x021a8000 0x4000>; |
| 275c08b5 | 916 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 | 917 | clocks = <&clks 127>; |
| 7d740f87 SG |
918 | status = "disabled"; |
| 919 | }; | |
| 920 | ||
| 921 | romcp@021ac000 { | |
| 922 | reg = <0x021ac000 0x4000>; | |
| 923 | }; | |
| 924 | ||
| 7b7d6727 | 925 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
| 7d740f87 SG |
926 | compatible = "fsl,imx6q-mmdc"; |
| 927 | reg = <0x021b0000 0x4000>; | |
| 928 | }; | |
| 929 | ||
| 7b7d6727 | 930 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
| 7d740f87 SG |
931 | reg = <0x021b4000 0x4000>; |
| 932 | }; | |
| 933 | ||
| 05e3f8e7 HS |
934 | weim: weim@021b8000 { |
| 935 | compatible = "fsl,imx6q-weim"; | |
| 7d740f87 | 936 | reg = <0x021b8000 0x4000>; |
| 275c08b5 | 937 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 05e3f8e7 | 938 | clocks = <&clks 196>; |
| 7d740f87 SG |
939 | }; |
| 940 | ||
| 3fe6373b SG |
941 | ocotp: ocotp@021bc000 { |
| 942 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
| 7d740f87 SG |
943 | reg = <0x021bc000 0x4000>; |
| 944 | }; | |
| 945 | ||
| 7d740f87 SG |
946 | tzasc@021d0000 { /* TZASC1 */ |
| 947 | reg = <0x021d0000 0x4000>; | |
| 275c08b5 | 948 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
949 | }; |
| 950 | ||
| 951 | tzasc@021d4000 { /* TZASC2 */ | |
| 952 | reg = <0x021d4000 0x4000>; | |
| 275c08b5 | 953 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
954 | }; |
| 955 | ||
| 7b7d6727 | 956 | audmux: audmux@021d8000 { |
| f965cd55 | 957 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
| 7d740f87 | 958 | reg = <0x021d8000 0x4000>; |
| f965cd55 | 959 | status = "disabled"; |
| 7d740f87 SG |
960 | }; |
| 961 | ||
| 5e0c7cd4 | 962 | mipi_csi: mipi@021dc000 { |
| 7d740f87 SG |
963 | reg = <0x021dc000 0x4000>; |
| 964 | }; | |
| 965 | ||
| 4520e692 PZ |
966 | mipi_dsi: mipi@021e0000 { |
| 967 | #address-cells = <1>; | |
| 968 | #size-cells = <0>; | |
| 7d740f87 | 969 | reg = <0x021e0000 0x4000>; |
| 4520e692 PZ |
970 | status = "disabled"; |
| 971 | ||
| 972 | port@0 { | |
| 973 | reg = <0>; | |
| 974 | ||
| 975 | mipi_mux_0: endpoint { | |
| 976 | remote-endpoint = <&ipu1_di0_mipi>; | |
| 977 | }; | |
| 978 | }; | |
| 979 | ||
| 980 | port@1 { | |
| 981 | reg = <1>; | |
| 982 | ||
| 983 | mipi_mux_1: endpoint { | |
| 984 | remote-endpoint = <&ipu1_di1_mipi>; | |
| 985 | }; | |
| 986 | }; | |
| 7d740f87 SG |
987 | }; |
| 988 | ||
| 989 | vdoa@021e4000 { | |
| 990 | reg = <0x021e4000 0x4000>; | |
| 275c08b5 | 991 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
992 | }; |
| 993 | ||
| 0c456cfa | 994 | uart2: serial@021e8000 { |
| 7d740f87 SG |
995 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 996 | reg = <0x021e8000 0x4000>; | |
| 275c08b5 | 997 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
998 | clocks = <&clks 160>, <&clks 161>; |
| 999 | clock-names = "ipg", "per"; | |
| 72a5cebf HS |
1000 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| 1001 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1002 | status = "disabled"; |
| 1003 | }; | |
| 1004 | ||
| 0c456cfa | 1005 | uart3: serial@021ec000 { |
| 7d740f87 SG |
1006 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1007 | reg = <0x021ec000 0x4000>; | |
| 275c08b5 | 1008 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
1009 | clocks = <&clks 160>, <&clks 161>; |
| 1010 | clock-names = "ipg", "per"; | |
| 72a5cebf HS |
1011 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| 1012 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1013 | status = "disabled"; |
| 1014 | }; | |
| 1015 | ||
| 0c456cfa | 1016 | uart4: serial@021f0000 { |
| 7d740f87 SG |
1017 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1018 | reg = <0x021f0000 0x4000>; | |
| 275c08b5 | 1019 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
1020 | clocks = <&clks 160>, <&clks 161>; |
| 1021 | clock-names = "ipg", "per"; | |
| 72a5cebf HS |
1022 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| 1023 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1024 | status = "disabled"; |
| 1025 | }; | |
| 1026 | ||
| 0c456cfa | 1027 | uart5: serial@021f4000 { |
| 7d740f87 SG |
1028 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1029 | reg = <0x021f4000 0x4000>; | |
| 275c08b5 | 1030 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| 0e87e043 SG |
1031 | clocks = <&clks 160>, <&clks 161>; |
| 1032 | clock-names = "ipg", "per"; | |
| 72a5cebf HS |
1033 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| 1034 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1035 | status = "disabled"; |
| 1036 | }; | |
| 1037 | }; | |
| 91660d74 SH |
1038 | |
| 1039 | ipu1: ipu@02400000 { | |
| 4520e692 PZ |
1040 | #address-cells = <1>; |
| 1041 | #size-cells = <0>; | |
| 91660d74 SH |
1042 | compatible = "fsl,imx6q-ipu"; |
| 1043 | reg = <0x02400000 0x400000>; | |
| 275c08b5 TK |
1044 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
| 1045 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 91660d74 SH |
1046 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| 1047 | clock-names = "bus", "di0", "di1"; | |
| 09ebf366 | 1048 | resets = <&src 2>; |
| 4520e692 PZ |
1049 | |
| 1050 | ipu1_di0: port@2 { | |
| 1051 | #address-cells = <1>; | |
| 1052 | #size-cells = <0>; | |
| 1053 | reg = <2>; | |
| 1054 | ||
| 1055 | ipu1_di0_disp0: endpoint@0 { | |
| 1056 | }; | |
| 1057 | ||
| 1058 | ipu1_di0_hdmi: endpoint@1 { | |
| 1059 | remote-endpoint = <&hdmi_mux_0>; | |
| 1060 | }; | |
| 1061 | ||
| 1062 | ipu1_di0_mipi: endpoint@2 { | |
| 1063 | remote-endpoint = <&mipi_mux_0>; | |
| 1064 | }; | |
| 1065 | ||
| 1066 | ipu1_di0_lvds0: endpoint@3 { | |
| 1067 | remote-endpoint = <&lvds0_mux_0>; | |
| 1068 | }; | |
| 1069 | ||
| 1070 | ipu1_di0_lvds1: endpoint@4 { | |
| 1071 | remote-endpoint = <&lvds1_mux_0>; | |
| 1072 | }; | |
| 1073 | }; | |
| 1074 | ||
| 1075 | ipu1_di1: port@3 { | |
| 1076 | #address-cells = <1>; | |
| 1077 | #size-cells = <0>; | |
| 1078 | reg = <3>; | |
| 1079 | ||
| 1080 | ipu1_di0_disp1: endpoint@0 { | |
| 1081 | }; | |
| 1082 | ||
| 1083 | ipu1_di1_hdmi: endpoint@1 { | |
| 1084 | remote-endpoint = <&hdmi_mux_1>; | |
| 1085 | }; | |
| 1086 | ||
| 1087 | ipu1_di1_mipi: endpoint@2 { | |
| 1088 | remote-endpoint = <&mipi_mux_1>; | |
| 1089 | }; | |
| 1090 | ||
| 1091 | ipu1_di1_lvds0: endpoint@3 { | |
| 1092 | remote-endpoint = <&lvds0_mux_1>; | |
| 1093 | }; | |
| 1094 | ||
| 1095 | ipu1_di1_lvds1: endpoint@4 { | |
| 1096 | remote-endpoint = <&lvds1_mux_1>; | |
| 1097 | }; | |
| 1098 | }; | |
| 91660d74 | 1099 | }; |
| 7d740f87 SG |
1100 | }; |
| 1101 | }; |