projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d740f87 SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 8888f651 | 13 | #include <dt-bindings/clock/imx6qdl-clock.h> |
| 07134a36 LS |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | ||
| 36dffd8f | 16 | #include "skeleton.dtsi" |
| 7d740f87 SG |
17 | |
| 18 | / { | |
| 19 | aliases { | |
| 22970070 | 20 | ethernet0 = &fec; |
| 5f8fbc2c LW |
21 | can0 = &can1; |
| 22 | can1 = &can2; | |
| 5230f8fe SG |
23 | gpio0 = &gpio1; |
| 24 | gpio1 = &gpio2; | |
| 25 | gpio2 = &gpio3; | |
| 26 | gpio3 = &gpio4; | |
| 27 | gpio4 = &gpio5; | |
| 28 | gpio5 = &gpio6; | |
| 29 | gpio6 = &gpio7; | |
| 80fa0584 SH |
30 | i2c0 = &i2c1; |
| 31 | i2c1 = &i2c2; | |
| 32 | i2c2 = &i2c3; | |
| fb06d65c SH |
33 | mmc0 = &usdhc1; |
| 34 | mmc1 = &usdhc2; | |
| 35 | mmc2 = &usdhc3; | |
| 36 | mmc3 = &usdhc4; | |
| 80fa0584 SH |
37 | serial0 = &uart1; |
| 38 | serial1 = &uart2; | |
| 39 | serial2 = &uart3; | |
| 40 | serial3 = &uart4; | |
| 41 | serial4 = &uart5; | |
| 42 | spi0 = &ecspi1; | |
| 43 | spi1 = &ecspi2; | |
| 44 | spi2 = &ecspi3; | |
| 45 | spi3 = &ecspi4; | |
| 8189c51f PC |
46 | usbphy0 = &usbphy1; |
| 47 | usbphy1 = &usbphy2; | |
| 7d740f87 SG |
48 | }; |
| 49 | ||
| 7d740f87 SG |
50 | intc: interrupt-controller@00a01000 { |
| 51 | compatible = "arm,cortex-a9-gic"; | |
| 52 | #interrupt-cells = <3>; | |
| 7d740f87 SG |
53 | interrupt-controller; |
| 54 | reg = <0x00a01000 0x1000>, | |
| 55 | <0x00a00100 0x100>; | |
| 56 | }; | |
| 57 | ||
| 58 | clocks { | |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <0>; | |
| 61 | ||
| 62 | ckil { | |
| 63 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 64 | #clock-cells = <0>; |
| 7d740f87 SG |
65 | clock-frequency = <32768>; |
| 66 | }; | |
| 67 | ||
| 68 | ckih1 { | |
| 69 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 70 | #clock-cells = <0>; |
| 7d740f87 SG |
71 | clock-frequency = <0>; |
| 72 | }; | |
| 73 | ||
| 74 | osc { | |
| 75 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 76 | #clock-cells = <0>; |
| 7d740f87 SG |
77 | clock-frequency = <24000000>; |
| 78 | }; | |
| 79 | }; | |
| 80 | ||
| 81 | soc { | |
| 82 | #address-cells = <1>; | |
| 83 | #size-cells = <1>; | |
| 84 | compatible = "simple-bus"; | |
| 85 | interrupt-parent = <&intc>; | |
| 86 | ranges; | |
| 87 | ||
| f30fb03d | 88 | dma_apbh: dma-apbh@00110000 { |
| e5d0f9f5 HS |
89 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 90 | reg = <0x00110000 0x2000>; | |
| 275c08b5 TK |
91 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 93 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 94 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
| f30fb03d SG |
95 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 96 | #dma-cells = <1>; | |
| 97 | dma-channels = <4>; | |
| 8888f651 | 98 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
| e5d0f9f5 HS |
99 | }; |
| 100 | ||
| be4ccfce | 101 | gpmi: gpmi-nand@00112000 { |
| 0e87e043 SG |
102 | compatible = "fsl,imx6q-gpmi-nand"; |
| 103 | #address-cells = <1>; | |
| 104 | #size-cells = <1>; | |
| 105 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
| 106 | reg-names = "gpmi-nand", "bch"; | |
| 275c08b5 | 107 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
| c7aa12a6 | 108 | interrupt-names = "bch"; |
| 8888f651 SG |
109 | clocks = <&clks IMX6QDL_CLK_GPMI_IO>, |
| 110 | <&clks IMX6QDL_CLK_GPMI_APB>, | |
| 111 | <&clks IMX6QDL_CLK_GPMI_BCH>, | |
| 112 | <&clks IMX6QDL_CLK_GPMI_BCH_APB>, | |
| 113 | <&clks IMX6QDL_CLK_PER1_BCH>; | |
| 0e87e043 SG |
114 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 115 | "gpmi_bch_apb", "per1_bch"; | |
| f30fb03d SG |
116 | dmas = <&dma_apbh 0>; |
| 117 | dma-names = "rx-tx"; | |
| 0e87e043 | 118 | status = "disabled"; |
| cf922fa8 HS |
119 | }; |
| 120 | ||
| 7d740f87 | 121 | timer@00a00600 { |
| 58458e03 MZ |
122 | compatible = "arm,cortex-a9-twd-timer"; |
| 123 | reg = <0x00a00600 0x20>; | |
| 124 | interrupts = <1 13 0xf01>; | |
| 8888f651 | 125 | clocks = <&clks IMX6QDL_CLK_TWD>; |
| 7d740f87 SG |
126 | }; |
| 127 | ||
| 128 | L2: l2-cache@00a02000 { | |
| 129 | compatible = "arm,pl310-cache"; | |
| 130 | reg = <0x00a02000 0x1000>; | |
| 275c08b5 | 131 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
132 | cache-unified; |
| 133 | cache-level = <2>; | |
| 5a5ca56e DB |
134 | arm,tag-latency = <4 2 3>; |
| 135 | arm,data-latency = <4 2 3>; | |
| 7d740f87 SG |
136 | }; |
| 137 | ||
| 3a57291f SC |
138 | pcie: pcie@0x01000000 { |
| 139 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
| fcd17303 LS |
140 | reg = <0x01ffc000 0x04000>, |
| 141 | <0x01f00000 0x80000>; | |
| 142 | reg-names = "dbi", "config"; | |
| 3a57291f SC |
143 | #address-cells = <3>; |
| 144 | #size-cells = <2>; | |
| 145 | device_type = "pci"; | |
| 146 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
| 147 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
| 148 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
| 149 | num-lanes = <1>; | |
| 92a7eb7c LS |
150 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | interrupt-names = "msi"; | |
| 07134a36 LS |
152 | #interrupt-cells = <1>; |
| 153 | interrupt-map-mask = <0 0 0 0x7>; | |
| 154 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 155 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 156 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 157 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
| 8888f651 SG |
158 | clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, |
| 159 | <&clks IMX6QDL_CLK_LVDS1_GATE>, | |
| 160 | <&clks IMX6QDL_CLK_PCIE_REF_125M>; | |
| 92a7eb7c | 161 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
| 3a57291f SC |
162 | status = "disabled"; |
| 163 | }; | |
| 164 | ||
| 218abe6f DB |
165 | pmu { |
| 166 | compatible = "arm,cortex-a9-pmu"; | |
| 275c08b5 | 167 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| 218abe6f DB |
168 | }; |
| 169 | ||
| 7d740f87 SG |
170 | aips-bus@02000000 { /* AIPS1 */ |
| 171 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 172 | #address-cells = <1>; | |
| 173 | #size-cells = <1>; | |
| 174 | reg = <0x02000000 0x100000>; | |
| 175 | ranges; | |
| 176 | ||
| 177 | spba-bus@02000000 { | |
| 178 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 179 | #address-cells = <1>; | |
| 180 | #size-cells = <1>; | |
| 181 | reg = <0x02000000 0x40000>; | |
| 182 | ranges; | |
| 183 | ||
| 7b7d6727 | 184 | spdif: spdif@02004000 { |
| c9d96df2 | 185 | compatible = "fsl,imx35-spdif"; |
| 7d740f87 | 186 | reg = <0x02004000 0x4000>; |
| 275c08b5 | 187 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| c9d96df2 FE |
188 | dmas = <&sdma 14 18 0>, |
| 189 | <&sdma 15 18 0>; | |
| 190 | dma-names = "rx", "tx"; | |
| 8888f651 SG |
191 | clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, |
| 192 | <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, | |
| 193 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
| 194 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
| 195 | <&clks IMX6QDL_CLK_DUMMY>; | |
| c9d96df2 FE |
196 | clock-names = "core", "rxtx0", |
| 197 | "rxtx1", "rxtx2", | |
| 198 | "rxtx3", "rxtx4", | |
| 199 | "rxtx5", "rxtx6", | |
| 200 | "rxtx7"; | |
| 201 | status = "disabled"; | |
| 7d740f87 SG |
202 | }; |
| 203 | ||
| 7b7d6727 | 204 | ecspi1: ecspi@02008000 { |
| 7d740f87 SG |
205 | #address-cells = <1>; |
| 206 | #size-cells = <0>; | |
| 207 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 208 | reg = <0x02008000 0x4000>; | |
| 275c08b5 | 209 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
210 | clocks = <&clks IMX6QDL_CLK_ECSPI1>, |
| 211 | <&clks IMX6QDL_CLK_ECSPI1>; | |
| 0e87e043 | 212 | clock-names = "ipg", "per"; |
| b3810c3d FL |
213 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; |
| 214 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
215 | status = "disabled"; |
| 216 | }; | |
| 217 | ||
| 7b7d6727 | 218 | ecspi2: ecspi@0200c000 { |
| 7d740f87 SG |
219 | #address-cells = <1>; |
| 220 | #size-cells = <0>; | |
| 221 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 222 | reg = <0x0200c000 0x4000>; | |
| 275c08b5 | 223 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
224 | clocks = <&clks IMX6QDL_CLK_ECSPI2>, |
| 225 | <&clks IMX6QDL_CLK_ECSPI2>; | |
| 0e87e043 | 226 | clock-names = "ipg", "per"; |
| b3810c3d FL |
227 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; |
| 228 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
229 | status = "disabled"; |
| 230 | }; | |
| 231 | ||
| 7b7d6727 | 232 | ecspi3: ecspi@02010000 { |
| 7d740f87 SG |
233 | #address-cells = <1>; |
| 234 | #size-cells = <0>; | |
| 235 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 236 | reg = <0x02010000 0x4000>; | |
| 275c08b5 | 237 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
238 | clocks = <&clks IMX6QDL_CLK_ECSPI3>, |
| 239 | <&clks IMX6QDL_CLK_ECSPI3>; | |
| 0e87e043 | 240 | clock-names = "ipg", "per"; |
| b3810c3d FL |
241 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; |
| 242 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
243 | status = "disabled"; |
| 244 | }; | |
| 245 | ||
| 7b7d6727 | 246 | ecspi4: ecspi@02014000 { |
| 7d740f87 SG |
247 | #address-cells = <1>; |
| 248 | #size-cells = <0>; | |
| 249 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 250 | reg = <0x02014000 0x4000>; | |
| 275c08b5 | 251 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
252 | clocks = <&clks IMX6QDL_CLK_ECSPI4>, |
| 253 | <&clks IMX6QDL_CLK_ECSPI4>; | |
| 0e87e043 | 254 | clock-names = "ipg", "per"; |
| b3810c3d FL |
255 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; |
| 256 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
257 | status = "disabled"; |
| 258 | }; | |
| 259 | ||
| 0c456cfa | 260 | uart1: serial@02020000 { |
| 7d740f87 SG |
261 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 262 | reg = <0x02020000 0x4000>; | |
| 275c08b5 | 263 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
264 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 265 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 266 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
267 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| 268 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
269 | status = "disabled"; |
| 270 | }; | |
| 271 | ||
| 7b7d6727 | 272 | esai: esai@02024000 { |
| 7d740f87 | 273 | reg = <0x02024000 0x4000>; |
| 275c08b5 | 274 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
275 | }; |
| 276 | ||
| b1a5da8e | 277 | ssi1: ssi@02028000 { |
| 6ff7f51e | 278 | #sound-dai-cells = <0>; |
| 98ea6ad2 | 279 | compatible = "fsl,imx6q-ssi", |
| 4c03527e | 280 | "fsl,imx51-ssi"; |
| 7d740f87 | 281 | reg = <0x02028000 0x4000>; |
| 275c08b5 | 282 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| 935632e9 SW |
283 | clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, |
| 284 | <&clks IMX6QDL_CLK_SSI1>; | |
| 285 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
286 | dmas = <&sdma 37 1 0>, |
| 287 | <&sdma 38 1 0>; | |
| 288 | dma-names = "rx", "tx"; | |
| b1a5da8e | 289 | fsl,fifo-depth = <15>; |
| b1a5da8e | 290 | status = "disabled"; |
| 7d740f87 SG |
291 | }; |
| 292 | ||
| b1a5da8e | 293 | ssi2: ssi@0202c000 { |
| 6ff7f51e | 294 | #sound-dai-cells = <0>; |
| 98ea6ad2 | 295 | compatible = "fsl,imx6q-ssi", |
| 4c03527e | 296 | "fsl,imx51-ssi"; |
| 7d740f87 | 297 | reg = <0x0202c000 0x4000>; |
| 275c08b5 | 298 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| 935632e9 SW |
299 | clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, |
| 300 | <&clks IMX6QDL_CLK_SSI2>; | |
| 301 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
302 | dmas = <&sdma 41 1 0>, |
| 303 | <&sdma 42 1 0>; | |
| 304 | dma-names = "rx", "tx"; | |
| b1a5da8e | 305 | fsl,fifo-depth = <15>; |
| b1a5da8e | 306 | status = "disabled"; |
| 7d740f87 SG |
307 | }; |
| 308 | ||
| b1a5da8e | 309 | ssi3: ssi@02030000 { |
| 6ff7f51e | 310 | #sound-dai-cells = <0>; |
| 98ea6ad2 | 311 | compatible = "fsl,imx6q-ssi", |
| 4c03527e | 312 | "fsl,imx51-ssi"; |
| 7d740f87 | 313 | reg = <0x02030000 0x4000>; |
| 275c08b5 | 314 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| 935632e9 SW |
315 | clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, |
| 316 | <&clks IMX6QDL_CLK_SSI3>; | |
| 317 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
318 | dmas = <&sdma 45 1 0>, |
| 319 | <&sdma 46 1 0>; | |
| 320 | dma-names = "rx", "tx"; | |
| b1a5da8e | 321 | fsl,fifo-depth = <15>; |
| b1a5da8e | 322 | status = "disabled"; |
| 7d740f87 SG |
323 | }; |
| 324 | ||
| 7b7d6727 | 325 | asrc: asrc@02034000 { |
| 7d740f87 | 326 | reg = <0x02034000 0x4000>; |
| 275c08b5 | 327 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
328 | }; |
| 329 | ||
| 330 | spba@0203c000 { | |
| 331 | reg = <0x0203c000 0x4000>; | |
| 332 | }; | |
| 333 | }; | |
| 334 | ||
| 7b7d6727 | 335 | vpu: vpu@02040000 { |
| a04a0b6f | 336 | compatible = "cnm,coda960"; |
| 7d740f87 | 337 | reg = <0x02040000 0x3c000>; |
| 275c08b5 TK |
338 | interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 339 | <0 12 IRQ_TYPE_LEVEL_HIGH>; | |
| a04a0b6f PZ |
340 | interrupt-names = "bit", "jpeg"; |
| 341 | clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
| 342 | <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, | |
| 343 | <&clks IMX6QDL_CLK_OCRAM>; | |
| 344 | clock-names = "per", "ahb", "ocram"; | |
| 345 | resets = <&src 1>; | |
| 346 | iram = <&ocram>; | |
| 7d740f87 SG |
347 | }; |
| 348 | ||
| 349 | aipstz@0207c000 { /* AIPSTZ1 */ | |
| 350 | reg = <0x0207c000 0x4000>; | |
| 351 | }; | |
| 352 | ||
| 7b7d6727 | 353 | pwm1: pwm@02080000 { |
| 33b38587 SH |
354 | #pwm-cells = <2>; |
| 355 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 356 | reg = <0x02080000 0x4000>; |
| 275c08b5 | 357 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
358 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 359 | <&clks IMX6QDL_CLK_PWM1>; | |
| 33b38587 | 360 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
361 | }; |
| 362 | ||
| 7b7d6727 | 363 | pwm2: pwm@02084000 { |
| 33b38587 SH |
364 | #pwm-cells = <2>; |
| 365 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 366 | reg = <0x02084000 0x4000>; |
| 275c08b5 | 367 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
368 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 369 | <&clks IMX6QDL_CLK_PWM2>; | |
| 33b38587 | 370 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
371 | }; |
| 372 | ||
| 7b7d6727 | 373 | pwm3: pwm@02088000 { |
| 33b38587 SH |
374 | #pwm-cells = <2>; |
| 375 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 376 | reg = <0x02088000 0x4000>; |
| 275c08b5 | 377 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
378 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 379 | <&clks IMX6QDL_CLK_PWM3>; | |
| 33b38587 | 380 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
381 | }; |
| 382 | ||
| 7b7d6727 | 383 | pwm4: pwm@0208c000 { |
| 33b38587 SH |
384 | #pwm-cells = <2>; |
| 385 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 386 | reg = <0x0208c000 0x4000>; |
| 275c08b5 | 387 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
388 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 389 | <&clks IMX6QDL_CLK_PWM4>; | |
| 33b38587 | 390 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
391 | }; |
| 392 | ||
| 7b7d6727 | 393 | can1: flexcan@02090000 { |
| 0f225212 | 394 | compatible = "fsl,imx6q-flexcan"; |
| 7d740f87 | 395 | reg = <0x02090000 0x4000>; |
| 275c08b5 | 396 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
397 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
| 398 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; | |
| 0f225212 | 399 | clock-names = "ipg", "per"; |
| a1135337 | 400 | status = "disabled"; |
| 7d740f87 SG |
401 | }; |
| 402 | ||
| 7b7d6727 | 403 | can2: flexcan@02094000 { |
| 0f225212 | 404 | compatible = "fsl,imx6q-flexcan"; |
| 7d740f87 | 405 | reg = <0x02094000 0x4000>; |
| 275c08b5 | 406 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
407 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
| 408 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; | |
| 0f225212 | 409 | clock-names = "ipg", "per"; |
| a1135337 | 410 | status = "disabled"; |
| 7d740f87 SG |
411 | }; |
| 412 | ||
| 7b7d6727 | 413 | gpt: gpt@02098000 { |
| 97b108f9 | 414 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
| 7d740f87 | 415 | reg = <0x02098000 0x4000>; |
| 275c08b5 | 416 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 417 | clocks = <&clks IMX6QDL_CLK_GPT_IPG>, |
| 2b2244a3 AH |
418 | <&clks IMX6QDL_CLK_GPT_IPG_PER>, |
| 419 | <&clks IMX6QDL_CLK_GPT_3M>; | |
| 420 | clock-names = "ipg", "per", "osc_per"; | |
| 7d740f87 SG |
421 | }; |
| 422 | ||
| 4d191868 | 423 | gpio1: gpio@0209c000 { |
| aeb27748 | 424 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 425 | reg = <0x0209c000 0x4000>; |
| 275c08b5 TK |
426 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| 427 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
428 | gpio-controller; |
| 429 | #gpio-cells = <2>; | |
| 430 | interrupt-controller; | |
| 88cde8b7 | 431 | #interrupt-cells = <2>; |
| 7d740f87 SG |
432 | }; |
| 433 | ||
| 4d191868 | 434 | gpio2: gpio@020a0000 { |
| aeb27748 | 435 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 436 | reg = <0x020a0000 0x4000>; |
| 275c08b5 TK |
437 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| 438 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
439 | gpio-controller; |
| 440 | #gpio-cells = <2>; | |
| 441 | interrupt-controller; | |
| 88cde8b7 | 442 | #interrupt-cells = <2>; |
| 7d740f87 SG |
443 | }; |
| 444 | ||
| 4d191868 | 445 | gpio3: gpio@020a4000 { |
| aeb27748 | 446 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 447 | reg = <0x020a4000 0x4000>; |
| 275c08b5 TK |
448 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| 449 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
450 | gpio-controller; |
| 451 | #gpio-cells = <2>; | |
| 452 | interrupt-controller; | |
| 88cde8b7 | 453 | #interrupt-cells = <2>; |
| 7d740f87 SG |
454 | }; |
| 455 | ||
| 4d191868 | 456 | gpio4: gpio@020a8000 { |
| aeb27748 | 457 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 458 | reg = <0x020a8000 0x4000>; |
| 275c08b5 TK |
459 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| 460 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
461 | gpio-controller; |
| 462 | #gpio-cells = <2>; | |
| 463 | interrupt-controller; | |
| 88cde8b7 | 464 | #interrupt-cells = <2>; |
| 7d740f87 SG |
465 | }; |
| 466 | ||
| 4d191868 | 467 | gpio5: gpio@020ac000 { |
| aeb27748 | 468 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 469 | reg = <0x020ac000 0x4000>; |
| 275c08b5 TK |
470 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| 471 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
472 | gpio-controller; |
| 473 | #gpio-cells = <2>; | |
| 474 | interrupt-controller; | |
| 88cde8b7 | 475 | #interrupt-cells = <2>; |
| 7d740f87 SG |
476 | }; |
| 477 | ||
| 4d191868 | 478 | gpio6: gpio@020b0000 { |
| aeb27748 | 479 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 480 | reg = <0x020b0000 0x4000>; |
| 275c08b5 TK |
481 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
| 482 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
483 | gpio-controller; |
| 484 | #gpio-cells = <2>; | |
| 485 | interrupt-controller; | |
| 88cde8b7 | 486 | #interrupt-cells = <2>; |
| 7d740f87 SG |
487 | }; |
| 488 | ||
| 4d191868 | 489 | gpio7: gpio@020b4000 { |
| aeb27748 | 490 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 491 | reg = <0x020b4000 0x4000>; |
| 275c08b5 TK |
492 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
| 493 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
494 | gpio-controller; |
| 495 | #gpio-cells = <2>; | |
| 496 | interrupt-controller; | |
| 88cde8b7 | 497 | #interrupt-cells = <2>; |
| 7d740f87 SG |
498 | }; |
| 499 | ||
| 7b7d6727 | 500 | kpp: kpp@020b8000 { |
| 36d3a8f0 | 501 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
| 7d740f87 | 502 | reg = <0x020b8000 0x4000>; |
| 275c08b5 | 503 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 504 | clocks = <&clks IMX6QDL_CLK_IPG>; |
| 1b6f2368 | 505 | status = "disabled"; |
| 7d740f87 SG |
506 | }; |
| 507 | ||
| 7b7d6727 | 508 | wdog1: wdog@020bc000 { |
| 7d740f87 SG |
509 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 510 | reg = <0x020bc000 0x4000>; | |
| 275c08b5 | 511 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 512 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
| 7d740f87 SG |
513 | }; |
| 514 | ||
| 7b7d6727 | 515 | wdog2: wdog@020c0000 { |
| 7d740f87 SG |
516 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 517 | reg = <0x020c0000 0x4000>; | |
| 275c08b5 | 518 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 519 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
| 7d740f87 SG |
520 | status = "disabled"; |
| 521 | }; | |
| 522 | ||
| 0e87e043 | 523 | clks: ccm@020c4000 { |
| 7d740f87 SG |
524 | compatible = "fsl,imx6q-ccm"; |
| 525 | reg = <0x020c4000 0x4000>; | |
| 275c08b5 TK |
526 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| 527 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
| 0e87e043 | 528 | #clock-cells = <1>; |
| 7d740f87 SG |
529 | }; |
| 530 | ||
| baa64151 DA |
531 | anatop: anatop@020c8000 { |
| 532 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
| 7d740f87 | 533 | reg = <0x020c8000 0x1000>; |
| 275c08b5 TK |
534 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| 535 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 536 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
| a1e327e6 YCLP |
537 | |
| 538 | regulator-1p1@110 { | |
| 539 | compatible = "fsl,anatop-regulator"; | |
| 540 | regulator-name = "vdd1p1"; | |
| 541 | regulator-min-microvolt = <800000>; | |
| 542 | regulator-max-microvolt = <1375000>; | |
| 543 | regulator-always-on; | |
| 544 | anatop-reg-offset = <0x110>; | |
| 545 | anatop-vol-bit-shift = <8>; | |
| 546 | anatop-vol-bit-width = <5>; | |
| 547 | anatop-min-bit-val = <4>; | |
| 548 | anatop-min-voltage = <800000>; | |
| 549 | anatop-max-voltage = <1375000>; | |
| 550 | }; | |
| 551 | ||
| 552 | regulator-3p0@120 { | |
| 553 | compatible = "fsl,anatop-regulator"; | |
| 554 | regulator-name = "vdd3p0"; | |
| 555 | regulator-min-microvolt = <2800000>; | |
| 556 | regulator-max-microvolt = <3150000>; | |
| 557 | regulator-always-on; | |
| 558 | anatop-reg-offset = <0x120>; | |
| 559 | anatop-vol-bit-shift = <8>; | |
| 560 | anatop-vol-bit-width = <5>; | |
| 561 | anatop-min-bit-val = <0>; | |
| 562 | anatop-min-voltage = <2625000>; | |
| 563 | anatop-max-voltage = <3400000>; | |
| 564 | }; | |
| 565 | ||
| 566 | regulator-2p5@130 { | |
| 567 | compatible = "fsl,anatop-regulator"; | |
| 568 | regulator-name = "vdd2p5"; | |
| 569 | regulator-min-microvolt = <2000000>; | |
| 570 | regulator-max-microvolt = <2750000>; | |
| 571 | regulator-always-on; | |
| 572 | anatop-reg-offset = <0x130>; | |
| 573 | anatop-vol-bit-shift = <8>; | |
| 574 | anatop-vol-bit-width = <5>; | |
| 575 | anatop-min-bit-val = <0>; | |
| 576 | anatop-min-voltage = <2000000>; | |
| 577 | anatop-max-voltage = <2750000>; | |
| 578 | }; | |
| 579 | ||
| 96574a6d | 580 | reg_arm: regulator-vddcore@140 { |
| a1e327e6 | 581 | compatible = "fsl,anatop-regulator"; |
| 118c98a6 | 582 | regulator-name = "vddarm"; |
| a1e327e6 YCLP |
583 | regulator-min-microvolt = <725000>; |
| 584 | regulator-max-microvolt = <1450000>; | |
| 585 | regulator-always-on; | |
| 586 | anatop-reg-offset = <0x140>; | |
| 587 | anatop-vol-bit-shift = <0>; | |
| 588 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
589 | anatop-delay-reg-offset = <0x170>; |
| 590 | anatop-delay-bit-shift = <24>; | |
| 591 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
592 | anatop-min-bit-val = <1>; |
| 593 | anatop-min-voltage = <725000>; | |
| 594 | anatop-max-voltage = <1450000>; | |
| 595 | }; | |
| 596 | ||
| 96574a6d | 597 | reg_pu: regulator-vddpu@140 { |
| a1e327e6 YCLP |
598 | compatible = "fsl,anatop-regulator"; |
| 599 | regulator-name = "vddpu"; | |
| 600 | regulator-min-microvolt = <725000>; | |
| 601 | regulator-max-microvolt = <1450000>; | |
| 602 | regulator-always-on; | |
| 603 | anatop-reg-offset = <0x140>; | |
| 604 | anatop-vol-bit-shift = <9>; | |
| 605 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
606 | anatop-delay-reg-offset = <0x170>; |
| 607 | anatop-delay-bit-shift = <26>; | |
| 608 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
609 | anatop-min-bit-val = <1>; |
| 610 | anatop-min-voltage = <725000>; | |
| 611 | anatop-max-voltage = <1450000>; | |
| 612 | }; | |
| 613 | ||
| 96574a6d | 614 | reg_soc: regulator-vddsoc@140 { |
| a1e327e6 YCLP |
615 | compatible = "fsl,anatop-regulator"; |
| 616 | regulator-name = "vddsoc"; | |
| 617 | regulator-min-microvolt = <725000>; | |
| 618 | regulator-max-microvolt = <1450000>; | |
| 619 | regulator-always-on; | |
| 620 | anatop-reg-offset = <0x140>; | |
| 621 | anatop-vol-bit-shift = <18>; | |
| 622 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
623 | anatop-delay-reg-offset = <0x170>; |
| 624 | anatop-delay-bit-shift = <28>; | |
| 625 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
626 | anatop-min-bit-val = <1>; |
| 627 | anatop-min-voltage = <725000>; | |
| 628 | anatop-max-voltage = <1450000>; | |
| 629 | }; | |
| 7d740f87 SG |
630 | }; |
| 631 | ||
| 3fe6373b SG |
632 | tempmon: tempmon { |
| 633 | compatible = "fsl,imx6q-tempmon"; | |
| 275c08b5 | 634 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
| 3fe6373b SG |
635 | fsl,tempmon = <&anatop>; |
| 636 | fsl,tempmon-data = <&ocotp>; | |
| 8888f651 | 637 | clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
| 3fe6373b SG |
638 | }; |
| 639 | ||
| 74bd88f7 RZ |
640 | usbphy1: usbphy@020c9000 { |
| 641 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
| 7d740f87 | 642 | reg = <0x020c9000 0x1000>; |
| 275c08b5 | 643 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 644 | clocks = <&clks IMX6QDL_CLK_USBPHY1>; |
| 76a38855 | 645 | fsl,anatop = <&anatop>; |
| 7d740f87 SG |
646 | }; |
| 647 | ||
| 74bd88f7 RZ |
648 | usbphy2: usbphy@020ca000 { |
| 649 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
| 7d740f87 | 650 | reg = <0x020ca000 0x1000>; |
| 275c08b5 | 651 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 652 | clocks = <&clks IMX6QDL_CLK_USBPHY2>; |
| 76a38855 | 653 | fsl,anatop = <&anatop>; |
| 7d740f87 SG |
654 | }; |
| 655 | ||
| 656 | snvs@020cc000 { | |
| c9250388 SG |
657 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 658 | #address-cells = <1>; | |
| 659 | #size-cells = <1>; | |
| 660 | ranges = <0 0x020cc000 0x4000>; | |
| 661 | ||
| 662 | snvs-rtc-lp@34 { | |
| 663 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
| 664 | reg = <0x34 0x58>; | |
| 275c08b5 TK |
665 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 666 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
| c9250388 | 667 | }; |
| 7d740f87 SG |
668 | }; |
| 669 | ||
| 7b7d6727 | 670 | epit1: epit@020d0000 { /* EPIT1 */ |
| 7d740f87 | 671 | reg = <0x020d0000 0x4000>; |
| 275c08b5 | 672 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
673 | }; |
| 674 | ||
| 7b7d6727 | 675 | epit2: epit@020d4000 { /* EPIT2 */ |
| 7d740f87 | 676 | reg = <0x020d4000 0x4000>; |
| 275c08b5 | 677 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
678 | }; |
| 679 | ||
| 7b7d6727 | 680 | src: src@020d8000 { |
| bd3d924d | 681 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
| 7d740f87 | 682 | reg = <0x020d8000 0x4000>; |
| 275c08b5 TK |
683 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| 684 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 09ebf366 | 685 | #reset-cells = <1>; |
| 7d740f87 SG |
686 | }; |
| 687 | ||
| 7b7d6727 | 688 | gpc: gpc@020dc000 { |
| 7d740f87 SG |
689 | compatible = "fsl,imx6q-gpc"; |
| 690 | reg = <0x020dc000 0x4000>; | |
| 275c08b5 TK |
691 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
| 692 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
693 | }; |
| 694 | ||
| df37e0c0 DA |
695 | gpr: iomuxc-gpr@020e0000 { |
| 696 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
| 697 | reg = <0x020e0000 0x38>; | |
| 698 | }; | |
| 699 | ||
| c56009b2 SG |
700 | iomuxc: iomuxc@020e0000 { |
| 701 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
| 702 | reg = <0x020e0000 0x4000>; | |
| c56009b2 SG |
703 | }; |
| 704 | ||
| 41c04342 ST |
705 | ldb: ldb@020e0008 { |
| 706 | #address-cells = <1>; | |
| 707 | #size-cells = <0>; | |
| 708 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
| 709 | gpr = <&gpr>; | |
| 710 | status = "disabled"; | |
| 711 | ||
| 712 | lvds-channel@0 { | |
| 4520e692 PZ |
713 | #address-cells = <1>; |
| 714 | #size-cells = <0>; | |
| 41c04342 | 715 | reg = <0>; |
| 41c04342 | 716 | status = "disabled"; |
| 4520e692 PZ |
717 | |
| 718 | port@0 { | |
| 719 | reg = <0>; | |
| 720 | ||
| 721 | lvds0_mux_0: endpoint { | |
| 722 | remote-endpoint = <&ipu1_di0_lvds0>; | |
| 723 | }; | |
| 724 | }; | |
| 725 | ||
| 726 | port@1 { | |
| 727 | reg = <1>; | |
| 728 | ||
| 729 | lvds0_mux_1: endpoint { | |
| 730 | remote-endpoint = <&ipu1_di1_lvds0>; | |
| 731 | }; | |
| 732 | }; | |
| 41c04342 ST |
733 | }; |
| 734 | ||
| 735 | lvds-channel@1 { | |
| 4520e692 PZ |
736 | #address-cells = <1>; |
| 737 | #size-cells = <0>; | |
| 41c04342 | 738 | reg = <1>; |
| 41c04342 | 739 | status = "disabled"; |
| 4520e692 PZ |
740 | |
| 741 | port@0 { | |
| 742 | reg = <0>; | |
| 743 | ||
| 744 | lvds1_mux_0: endpoint { | |
| 745 | remote-endpoint = <&ipu1_di0_lvds1>; | |
| 746 | }; | |
| 747 | }; | |
| 748 | ||
| 749 | port@1 { | |
| 750 | reg = <1>; | |
| 751 | ||
| 752 | lvds1_mux_1: endpoint { | |
| 753 | remote-endpoint = <&ipu1_di1_lvds1>; | |
| 754 | }; | |
| 755 | }; | |
| 41c04342 ST |
756 | }; |
| 757 | }; | |
| 758 | ||
| 04cec1a2 | 759 | hdmi: hdmi@0120000 { |
| 4520e692 PZ |
760 | #address-cells = <1>; |
| 761 | #size-cells = <0>; | |
| 04cec1a2 RK |
762 | reg = <0x00120000 0x9000>; |
| 763 | interrupts = <0 115 0x04>; | |
| 764 | gpr = <&gpr>; | |
| 8888f651 SG |
765 | clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, |
| 766 | <&clks IMX6QDL_CLK_HDMI_ISFR>; | |
| 04cec1a2 RK |
767 | clock-names = "iahb", "isfr"; |
| 768 | status = "disabled"; | |
| 4520e692 PZ |
769 | |
| 770 | port@0 { | |
| 771 | reg = <0>; | |
| 772 | ||
| 773 | hdmi_mux_0: endpoint { | |
| 774 | remote-endpoint = <&ipu1_di0_hdmi>; | |
| 775 | }; | |
| 776 | }; | |
| 777 | ||
| 778 | port@1 { | |
| 779 | reg = <1>; | |
| 780 | ||
| 781 | hdmi_mux_1: endpoint { | |
| 782 | remote-endpoint = <&ipu1_di1_hdmi>; | |
| 783 | }; | |
| 784 | }; | |
| 04cec1a2 RK |
785 | }; |
| 786 | ||
| 7b7d6727 | 787 | dcic1: dcic@020e4000 { |
| 7d740f87 | 788 | reg = <0x020e4000 0x4000>; |
| 275c08b5 | 789 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
790 | }; |
| 791 | ||
| 7b7d6727 | 792 | dcic2: dcic@020e8000 { |
| 7d740f87 | 793 | reg = <0x020e8000 0x4000>; |
| 275c08b5 | 794 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
795 | }; |
| 796 | ||
| 7b7d6727 | 797 | sdma: sdma@020ec000 { |
| 7d740f87 SG |
798 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 799 | reg = <0x020ec000 0x4000>; | |
| 275c08b5 | 800 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
801 | clocks = <&clks IMX6QDL_CLK_SDMA>, |
| 802 | <&clks IMX6QDL_CLK_SDMA>; | |
| 0e87e043 | 803 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 804 | #dma-cells = <3>; |
| d6b9c591 | 805 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| 7d740f87 SG |
806 | }; |
| 807 | }; | |
| 808 | ||
| 809 | aips-bus@02100000 { /* AIPS2 */ | |
| 810 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 811 | #address-cells = <1>; | |
| 812 | #size-cells = <1>; | |
| 813 | reg = <0x02100000 0x100000>; | |
| 814 | ranges; | |
| 815 | ||
| 816 | caam@02100000 { | |
| 817 | reg = <0x02100000 0x40000>; | |
| 275c08b5 TK |
818 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, |
| 819 | <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
820 | }; |
| 821 | ||
| 822 | aipstz@0217c000 { /* AIPSTZ2 */ | |
| 823 | reg = <0x0217c000 0x4000>; | |
| 824 | }; | |
| 825 | ||
| 7b7d6727 | 826 | usbotg: usb@02184000 { |
| 74bd88f7 RZ |
827 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 828 | reg = <0x02184000 0x200>; | |
| 275c08b5 | 829 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 830 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 74bd88f7 | 831 | fsl,usbphy = <&usbphy1>; |
| 28342c61 | 832 | fsl,usbmisc = <&usbmisc 0>; |
| 74bd88f7 RZ |
833 | status = "disabled"; |
| 834 | }; | |
| 835 | ||
| 7b7d6727 | 836 | usbh1: usb@02184200 { |
| 74bd88f7 RZ |
837 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 838 | reg = <0x02184200 0x200>; | |
| 275c08b5 | 839 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 840 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 74bd88f7 | 841 | fsl,usbphy = <&usbphy2>; |
| 28342c61 | 842 | fsl,usbmisc = <&usbmisc 1>; |
| 74bd88f7 RZ |
843 | status = "disabled"; |
| 844 | }; | |
| 845 | ||
| 7b7d6727 | 846 | usbh2: usb@02184400 { |
| 74bd88f7 RZ |
847 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 848 | reg = <0x02184400 0x200>; | |
| 275c08b5 | 849 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 850 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 28342c61 | 851 | fsl,usbmisc = <&usbmisc 2>; |
| 74bd88f7 RZ |
852 | status = "disabled"; |
| 853 | }; | |
| 854 | ||
| 7b7d6727 | 855 | usbh3: usb@02184600 { |
| 74bd88f7 RZ |
856 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 857 | reg = <0x02184600 0x200>; | |
| 275c08b5 | 858 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 859 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 28342c61 | 860 | fsl,usbmisc = <&usbmisc 3>; |
| 74bd88f7 RZ |
861 | status = "disabled"; |
| 862 | }; | |
| 863 | ||
| 60984bdf | 864 | usbmisc: usbmisc@02184800 { |
| 28342c61 RZ |
865 | #index-cells = <1>; |
| 866 | compatible = "fsl,imx6q-usbmisc"; | |
| 867 | reg = <0x02184800 0x200>; | |
| 8888f651 | 868 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 28342c61 RZ |
869 | }; |
| 870 | ||
| 7b7d6727 | 871 | fec: ethernet@02188000 { |
| 7d740f87 SG |
872 | compatible = "fsl,imx6q-fec"; |
| 873 | reg = <0x02188000 0x4000>; | |
| 454cf8f5 TK |
874 | interrupts-extended = |
| 875 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 876 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
| 8888f651 SG |
877 | clocks = <&clks IMX6QDL_CLK_ENET>, |
| 878 | <&clks IMX6QDL_CLK_ENET>, | |
| 879 | <&clks IMX6QDL_CLK_ENET_REF>; | |
| 7629838c | 880 | clock-names = "ipg", "ahb", "ptp"; |
| 7d740f87 SG |
881 | status = "disabled"; |
| 882 | }; | |
| 883 | ||
| 884 | mlb@0218c000 { | |
| 885 | reg = <0x0218c000 0x4000>; | |
| 275c08b5 TK |
886 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
| 887 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 888 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
889 | }; |
| 890 | ||
| 7b7d6727 | 891 | usdhc1: usdhc@02190000 { |
| 7d740f87 SG |
892 | compatible = "fsl,imx6q-usdhc"; |
| 893 | reg = <0x02190000 0x4000>; | |
| 275c08b5 | 894 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
895 | clocks = <&clks IMX6QDL_CLK_USDHC1>, |
| 896 | <&clks IMX6QDL_CLK_USDHC1>, | |
| 897 | <&clks IMX6QDL_CLK_USDHC1>; | |
| 0e87e043 | 898 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 899 | bus-width = <4>; |
| 7d740f87 SG |
900 | status = "disabled"; |
| 901 | }; | |
| 902 | ||
| 7b7d6727 | 903 | usdhc2: usdhc@02194000 { |
| 7d740f87 SG |
904 | compatible = "fsl,imx6q-usdhc"; |
| 905 | reg = <0x02194000 0x4000>; | |
| 275c08b5 | 906 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
907 | clocks = <&clks IMX6QDL_CLK_USDHC2>, |
| 908 | <&clks IMX6QDL_CLK_USDHC2>, | |
| 909 | <&clks IMX6QDL_CLK_USDHC2>; | |
| 0e87e043 | 910 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 911 | bus-width = <4>; |
| 7d740f87 SG |
912 | status = "disabled"; |
| 913 | }; | |
| 914 | ||
| 7b7d6727 | 915 | usdhc3: usdhc@02198000 { |
| 7d740f87 SG |
916 | compatible = "fsl,imx6q-usdhc"; |
| 917 | reg = <0x02198000 0x4000>; | |
| 275c08b5 | 918 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
919 | clocks = <&clks IMX6QDL_CLK_USDHC3>, |
| 920 | <&clks IMX6QDL_CLK_USDHC3>, | |
| 921 | <&clks IMX6QDL_CLK_USDHC3>; | |
| 0e87e043 | 922 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 923 | bus-width = <4>; |
| 7d740f87 SG |
924 | status = "disabled"; |
| 925 | }; | |
| 926 | ||
| 7b7d6727 | 927 | usdhc4: usdhc@0219c000 { |
| 7d740f87 SG |
928 | compatible = "fsl,imx6q-usdhc"; |
| 929 | reg = <0x0219c000 0x4000>; | |
| 275c08b5 | 930 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
931 | clocks = <&clks IMX6QDL_CLK_USDHC4>, |
| 932 | <&clks IMX6QDL_CLK_USDHC4>, | |
| 933 | <&clks IMX6QDL_CLK_USDHC4>; | |
| 0e87e043 | 934 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 935 | bus-width = <4>; |
| 7d740f87 SG |
936 | status = "disabled"; |
| 937 | }; | |
| 938 | ||
| 7b7d6727 | 939 | i2c1: i2c@021a0000 { |
| 7d740f87 SG |
940 | #address-cells = <1>; |
| 941 | #size-cells = <0>; | |
| 5bdfba29 | 942 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 943 | reg = <0x021a0000 0x4000>; |
| 275c08b5 | 944 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 945 | clocks = <&clks IMX6QDL_CLK_I2C1>; |
| 7d740f87 SG |
946 | status = "disabled"; |
| 947 | }; | |
| 948 | ||
| 7b7d6727 | 949 | i2c2: i2c@021a4000 { |
| 7d740f87 SG |
950 | #address-cells = <1>; |
| 951 | #size-cells = <0>; | |
| 5bdfba29 | 952 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 953 | reg = <0x021a4000 0x4000>; |
| 275c08b5 | 954 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 955 | clocks = <&clks IMX6QDL_CLK_I2C2>; |
| 7d740f87 SG |
956 | status = "disabled"; |
| 957 | }; | |
| 958 | ||
| 7b7d6727 | 959 | i2c3: i2c@021a8000 { |
| 7d740f87 SG |
960 | #address-cells = <1>; |
| 961 | #size-cells = <0>; | |
| 5bdfba29 | 962 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 963 | reg = <0x021a8000 0x4000>; |
| 275c08b5 | 964 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 965 | clocks = <&clks IMX6QDL_CLK_I2C3>; |
| 7d740f87 SG |
966 | status = "disabled"; |
| 967 | }; | |
| 968 | ||
| 969 | romcp@021ac000 { | |
| 970 | reg = <0x021ac000 0x4000>; | |
| 971 | }; | |
| 972 | ||
| 7b7d6727 | 973 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
| 7d740f87 SG |
974 | compatible = "fsl,imx6q-mmdc"; |
| 975 | reg = <0x021b0000 0x4000>; | |
| 976 | }; | |
| 977 | ||
| 7b7d6727 | 978 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
| 7d740f87 SG |
979 | reg = <0x021b4000 0x4000>; |
| 980 | }; | |
| 981 | ||
| 05e3f8e7 HS |
982 | weim: weim@021b8000 { |
| 983 | compatible = "fsl,imx6q-weim"; | |
| 7d740f87 | 984 | reg = <0x021b8000 0x4000>; |
| 275c08b5 | 985 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 986 | clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; |
| 7d740f87 SG |
987 | }; |
| 988 | ||
| 3fe6373b SG |
989 | ocotp: ocotp@021bc000 { |
| 990 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
| 7d740f87 SG |
991 | reg = <0x021bc000 0x4000>; |
| 992 | }; | |
| 993 | ||
| 7d740f87 SG |
994 | tzasc@021d0000 { /* TZASC1 */ |
| 995 | reg = <0x021d0000 0x4000>; | |
| 275c08b5 | 996 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
997 | }; |
| 998 | ||
| 999 | tzasc@021d4000 { /* TZASC2 */ | |
| 1000 | reg = <0x021d4000 0x4000>; | |
| 275c08b5 | 1001 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
1002 | }; |
| 1003 | ||
| 7b7d6727 | 1004 | audmux: audmux@021d8000 { |
| f965cd55 | 1005 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
| 7d740f87 | 1006 | reg = <0x021d8000 0x4000>; |
| f965cd55 | 1007 | status = "disabled"; |
| 7d740f87 SG |
1008 | }; |
| 1009 | ||
| 5e0c7cd4 | 1010 | mipi_csi: mipi@021dc000 { |
| 7d740f87 SG |
1011 | reg = <0x021dc000 0x4000>; |
| 1012 | }; | |
| 1013 | ||
| 4520e692 PZ |
1014 | mipi_dsi: mipi@021e0000 { |
| 1015 | #address-cells = <1>; | |
| 1016 | #size-cells = <0>; | |
| 7d740f87 | 1017 | reg = <0x021e0000 0x4000>; |
| 4520e692 PZ |
1018 | status = "disabled"; |
| 1019 | ||
| 1020 | port@0 { | |
| 1021 | reg = <0>; | |
| 1022 | ||
| 1023 | mipi_mux_0: endpoint { | |
| 1024 | remote-endpoint = <&ipu1_di0_mipi>; | |
| 1025 | }; | |
| 1026 | }; | |
| 1027 | ||
| 1028 | port@1 { | |
| 1029 | reg = <1>; | |
| 1030 | ||
| 1031 | mipi_mux_1: endpoint { | |
| 1032 | remote-endpoint = <&ipu1_di1_mipi>; | |
| 1033 | }; | |
| 1034 | }; | |
| 7d740f87 SG |
1035 | }; |
| 1036 | ||
| 1037 | vdoa@021e4000 { | |
| 1038 | reg = <0x021e4000 0x4000>; | |
| 275c08b5 | 1039 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
1040 | }; |
| 1041 | ||
| 0c456cfa | 1042 | uart2: serial@021e8000 { |
| 7d740f87 SG |
1043 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1044 | reg = <0x021e8000 0x4000>; | |
| 275c08b5 | 1045 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1046 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1047 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1048 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1049 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| 1050 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1051 | status = "disabled"; |
| 1052 | }; | |
| 1053 | ||
| 0c456cfa | 1054 | uart3: serial@021ec000 { |
| 7d740f87 SG |
1055 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1056 | reg = <0x021ec000 0x4000>; | |
| 275c08b5 | 1057 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1058 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1059 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1060 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1061 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| 1062 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1063 | status = "disabled"; |
| 1064 | }; | |
| 1065 | ||
| 0c456cfa | 1066 | uart4: serial@021f0000 { |
| 7d740f87 SG |
1067 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1068 | reg = <0x021f0000 0x4000>; | |
| 275c08b5 | 1069 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1070 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1071 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1072 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1073 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| 1074 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1075 | status = "disabled"; |
| 1076 | }; | |
| 1077 | ||
| 0c456cfa | 1078 | uart5: serial@021f4000 { |
| 7d740f87 SG |
1079 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1080 | reg = <0x021f4000 0x4000>; | |
| 275c08b5 | 1081 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1082 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1083 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1084 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1085 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| 1086 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1087 | status = "disabled"; |
| 1088 | }; | |
| 1089 | }; | |
| 91660d74 SH |
1090 | |
| 1091 | ipu1: ipu@02400000 { | |
| 4520e692 PZ |
1092 | #address-cells = <1>; |
| 1093 | #size-cells = <0>; | |
| 91660d74 SH |
1094 | compatible = "fsl,imx6q-ipu"; |
| 1095 | reg = <0x02400000 0x400000>; | |
| 275c08b5 TK |
1096 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
| 1097 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 8888f651 SG |
1098 | clocks = <&clks IMX6QDL_CLK_IPU1>, |
| 1099 | <&clks IMX6QDL_CLK_IPU1_DI0>, | |
| 1100 | <&clks IMX6QDL_CLK_IPU1_DI1>; | |
| 91660d74 | 1101 | clock-names = "bus", "di0", "di1"; |
| 09ebf366 | 1102 | resets = <&src 2>; |
| 4520e692 | 1103 | |
| c0470c38 PZ |
1104 | ipu1_csi0: port@0 { |
| 1105 | reg = <0>; | |
| 1106 | }; | |
| 1107 | ||
| 1108 | ipu1_csi1: port@1 { | |
| 1109 | reg = <1>; | |
| 1110 | }; | |
| 1111 | ||
| 4520e692 PZ |
1112 | ipu1_di0: port@2 { |
| 1113 | #address-cells = <1>; | |
| 1114 | #size-cells = <0>; | |
| 1115 | reg = <2>; | |
| 1116 | ||
| 1117 | ipu1_di0_disp0: endpoint@0 { | |
| 1118 | }; | |
| 1119 | ||
| 1120 | ipu1_di0_hdmi: endpoint@1 { | |
| 1121 | remote-endpoint = <&hdmi_mux_0>; | |
| 1122 | }; | |
| 1123 | ||
| 1124 | ipu1_di0_mipi: endpoint@2 { | |
| 1125 | remote-endpoint = <&mipi_mux_0>; | |
| 1126 | }; | |
| 1127 | ||
| 1128 | ipu1_di0_lvds0: endpoint@3 { | |
| 1129 | remote-endpoint = <&lvds0_mux_0>; | |
| 1130 | }; | |
| 1131 | ||
| 1132 | ipu1_di0_lvds1: endpoint@4 { | |
| 1133 | remote-endpoint = <&lvds1_mux_0>; | |
| 1134 | }; | |
| 1135 | }; | |
| 1136 | ||
| 1137 | ipu1_di1: port@3 { | |
| 1138 | #address-cells = <1>; | |
| 1139 | #size-cells = <0>; | |
| 1140 | reg = <3>; | |
| 1141 | ||
| 1142 | ipu1_di0_disp1: endpoint@0 { | |
| 1143 | }; | |
| 1144 | ||
| 1145 | ipu1_di1_hdmi: endpoint@1 { | |
| 1146 | remote-endpoint = <&hdmi_mux_1>; | |
| 1147 | }; | |
| 1148 | ||
| 1149 | ipu1_di1_mipi: endpoint@2 { | |
| 1150 | remote-endpoint = <&mipi_mux_1>; | |
| 1151 | }; | |
| 1152 | ||
| 1153 | ipu1_di1_lvds0: endpoint@3 { | |
| 1154 | remote-endpoint = <&lvds0_mux_1>; | |
| 1155 | }; | |
| 1156 | ||
| 1157 | ipu1_di1_lvds1: endpoint@4 { | |
| 1158 | remote-endpoint = <&lvds1_mux_1>; | |
| 1159 | }; | |
| 1160 | }; | |
| 91660d74 | 1161 | }; |
| 7d740f87 SG |
1162 | }; |
| 1163 | }; |