Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /include/ "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
8f9ffecf RZ |
17 | serial0 = &uart1; |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
20 | serial3 = &uart4; | |
21 | serial4 = &uart5; | |
5230f8fe SG |
22 | gpio0 = &gpio1; |
23 | gpio1 = &gpio2; | |
24 | gpio2 = &gpio3; | |
25 | gpio3 = &gpio4; | |
26 | gpio4 = &gpio5; | |
27 | gpio5 = &gpio6; | |
28 | gpio6 = &gpio7; | |
7d740f87 SG |
29 | }; |
30 | ||
7d740f87 SG |
31 | intc: interrupt-controller@00a01000 { |
32 | compatible = "arm,cortex-a9-gic"; | |
33 | #interrupt-cells = <3>; | |
34 | #address-cells = <1>; | |
35 | #size-cells = <1>; | |
36 | interrupt-controller; | |
37 | reg = <0x00a01000 0x1000>, | |
38 | <0x00a00100 0x100>; | |
39 | }; | |
40 | ||
41 | clocks { | |
42 | #address-cells = <1>; | |
43 | #size-cells = <0>; | |
44 | ||
45 | ckil { | |
46 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
47 | clock-frequency = <32768>; | |
48 | }; | |
49 | ||
50 | ckih1 { | |
51 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
52 | clock-frequency = <0>; | |
53 | }; | |
54 | ||
55 | osc { | |
56 | compatible = "fsl,imx-osc", "fixed-clock"; | |
57 | clock-frequency = <24000000>; | |
58 | }; | |
59 | }; | |
60 | ||
61 | soc { | |
62 | #address-cells = <1>; | |
63 | #size-cells = <1>; | |
64 | compatible = "simple-bus"; | |
65 | interrupt-parent = <&intc>; | |
66 | ranges; | |
67 | ||
e5d0f9f5 HS |
68 | dma-apbh@00110000 { |
69 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | |
70 | reg = <0x00110000 0x2000>; | |
0e87e043 | 71 | clocks = <&clks 106>; |
e5d0f9f5 HS |
72 | }; |
73 | ||
be4ccfce | 74 | gpmi: gpmi-nand@00112000 { |
0e87e043 SG |
75 | compatible = "fsl,imx6q-gpmi-nand"; |
76 | #address-cells = <1>; | |
77 | #size-cells = <1>; | |
78 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
79 | reg-names = "gpmi-nand", "bch"; | |
80 | interrupts = <0 13 0x04>, <0 15 0x04>; | |
81 | interrupt-names = "gpmi-dma", "bch"; | |
82 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, | |
83 | <&clks 150>, <&clks 149>; | |
84 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
85 | "gpmi_bch_apb", "per1_bch"; | |
86 | fsl,gpmi-dma-channel = <0>; | |
87 | status = "disabled"; | |
cf922fa8 HS |
88 | }; |
89 | ||
7d740f87 | 90 | timer@00a00600 { |
58458e03 MZ |
91 | compatible = "arm,cortex-a9-twd-timer"; |
92 | reg = <0x00a00600 0x20>; | |
93 | interrupts = <1 13 0xf01>; | |
7d740f87 SG |
94 | }; |
95 | ||
96 | L2: l2-cache@00a02000 { | |
97 | compatible = "arm,pl310-cache"; | |
98 | reg = <0x00a02000 0x1000>; | |
99 | interrupts = <0 92 0x04>; | |
100 | cache-unified; | |
101 | cache-level = <2>; | |
102 | }; | |
103 | ||
104 | aips-bus@02000000 { /* AIPS1 */ | |
105 | compatible = "fsl,aips-bus", "simple-bus"; | |
106 | #address-cells = <1>; | |
107 | #size-cells = <1>; | |
108 | reg = <0x02000000 0x100000>; | |
109 | ranges; | |
110 | ||
111 | spba-bus@02000000 { | |
112 | compatible = "fsl,spba-bus", "simple-bus"; | |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | reg = <0x02000000 0x40000>; | |
116 | ranges; | |
117 | ||
7b7d6727 | 118 | spdif: spdif@02004000 { |
7d740f87 SG |
119 | reg = <0x02004000 0x4000>; |
120 | interrupts = <0 52 0x04>; | |
121 | }; | |
122 | ||
7b7d6727 | 123 | ecspi1: ecspi@02008000 { |
7d740f87 SG |
124 | #address-cells = <1>; |
125 | #size-cells = <0>; | |
126 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
127 | reg = <0x02008000 0x4000>; | |
128 | interrupts = <0 31 0x04>; | |
0e87e043 SG |
129 | clocks = <&clks 112>, <&clks 112>; |
130 | clock-names = "ipg", "per"; | |
7d740f87 SG |
131 | status = "disabled"; |
132 | }; | |
133 | ||
7b7d6727 | 134 | ecspi2: ecspi@0200c000 { |
7d740f87 SG |
135 | #address-cells = <1>; |
136 | #size-cells = <0>; | |
137 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
138 | reg = <0x0200c000 0x4000>; | |
139 | interrupts = <0 32 0x04>; | |
0e87e043 SG |
140 | clocks = <&clks 113>, <&clks 113>; |
141 | clock-names = "ipg", "per"; | |
7d740f87 SG |
142 | status = "disabled"; |
143 | }; | |
144 | ||
7b7d6727 | 145 | ecspi3: ecspi@02010000 { |
7d740f87 SG |
146 | #address-cells = <1>; |
147 | #size-cells = <0>; | |
148 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
149 | reg = <0x02010000 0x4000>; | |
150 | interrupts = <0 33 0x04>; | |
0e87e043 SG |
151 | clocks = <&clks 114>, <&clks 114>; |
152 | clock-names = "ipg", "per"; | |
7d740f87 SG |
153 | status = "disabled"; |
154 | }; | |
155 | ||
7b7d6727 | 156 | ecspi4: ecspi@02014000 { |
7d740f87 SG |
157 | #address-cells = <1>; |
158 | #size-cells = <0>; | |
159 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
160 | reg = <0x02014000 0x4000>; | |
161 | interrupts = <0 34 0x04>; | |
0e87e043 SG |
162 | clocks = <&clks 115>, <&clks 115>; |
163 | clock-names = "ipg", "per"; | |
7d740f87 SG |
164 | status = "disabled"; |
165 | }; | |
166 | ||
0c456cfa | 167 | uart1: serial@02020000 { |
7d740f87 SG |
168 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
169 | reg = <0x02020000 0x4000>; | |
170 | interrupts = <0 26 0x04>; | |
0e87e043 SG |
171 | clocks = <&clks 160>, <&clks 161>; |
172 | clock-names = "ipg", "per"; | |
7d740f87 SG |
173 | status = "disabled"; |
174 | }; | |
175 | ||
7b7d6727 | 176 | esai: esai@02024000 { |
7d740f87 SG |
177 | reg = <0x02024000 0x4000>; |
178 | interrupts = <0 51 0x04>; | |
179 | }; | |
180 | ||
b1a5da8e RZ |
181 | ssi1: ssi@02028000 { |
182 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
183 | reg = <0x02028000 0x4000>; |
184 | interrupts = <0 46 0x04>; | |
0e87e043 | 185 | clocks = <&clks 178>; |
b1a5da8e RZ |
186 | fsl,fifo-depth = <15>; |
187 | fsl,ssi-dma-events = <38 37>; | |
188 | status = "disabled"; | |
7d740f87 SG |
189 | }; |
190 | ||
b1a5da8e RZ |
191 | ssi2: ssi@0202c000 { |
192 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
193 | reg = <0x0202c000 0x4000>; |
194 | interrupts = <0 47 0x04>; | |
0e87e043 | 195 | clocks = <&clks 179>; |
b1a5da8e RZ |
196 | fsl,fifo-depth = <15>; |
197 | fsl,ssi-dma-events = <42 41>; | |
198 | status = "disabled"; | |
7d740f87 SG |
199 | }; |
200 | ||
b1a5da8e RZ |
201 | ssi3: ssi@02030000 { |
202 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | |
7d740f87 SG |
203 | reg = <0x02030000 0x4000>; |
204 | interrupts = <0 48 0x04>; | |
0e87e043 | 205 | clocks = <&clks 180>; |
b1a5da8e RZ |
206 | fsl,fifo-depth = <15>; |
207 | fsl,ssi-dma-events = <46 45>; | |
208 | status = "disabled"; | |
7d740f87 SG |
209 | }; |
210 | ||
7b7d6727 | 211 | asrc: asrc@02034000 { |
7d740f87 SG |
212 | reg = <0x02034000 0x4000>; |
213 | interrupts = <0 50 0x04>; | |
214 | }; | |
215 | ||
216 | spba@0203c000 { | |
217 | reg = <0x0203c000 0x4000>; | |
218 | }; | |
219 | }; | |
220 | ||
7b7d6727 | 221 | vpu: vpu@02040000 { |
7d740f87 SG |
222 | reg = <0x02040000 0x3c000>; |
223 | interrupts = <0 3 0x04 0 12 0x04>; | |
224 | }; | |
225 | ||
226 | aipstz@0207c000 { /* AIPSTZ1 */ | |
227 | reg = <0x0207c000 0x4000>; | |
228 | }; | |
229 | ||
7b7d6727 | 230 | pwm1: pwm@02080000 { |
33b38587 SH |
231 | #pwm-cells = <2>; |
232 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
233 | reg = <0x02080000 0x4000>; |
234 | interrupts = <0 83 0x04>; | |
33b38587 SH |
235 | clocks = <&clks 62>, <&clks 145>; |
236 | clock-names = "ipg", "per"; | |
7d740f87 SG |
237 | }; |
238 | ||
7b7d6727 | 239 | pwm2: pwm@02084000 { |
33b38587 SH |
240 | #pwm-cells = <2>; |
241 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
242 | reg = <0x02084000 0x4000>; |
243 | interrupts = <0 84 0x04>; | |
33b38587 SH |
244 | clocks = <&clks 62>, <&clks 146>; |
245 | clock-names = "ipg", "per"; | |
7d740f87 SG |
246 | }; |
247 | ||
7b7d6727 | 248 | pwm3: pwm@02088000 { |
33b38587 SH |
249 | #pwm-cells = <2>; |
250 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
251 | reg = <0x02088000 0x4000>; |
252 | interrupts = <0 85 0x04>; | |
33b38587 SH |
253 | clocks = <&clks 62>, <&clks 147>; |
254 | clock-names = "ipg", "per"; | |
7d740f87 SG |
255 | }; |
256 | ||
7b7d6727 | 257 | pwm4: pwm@0208c000 { |
33b38587 SH |
258 | #pwm-cells = <2>; |
259 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 SG |
260 | reg = <0x0208c000 0x4000>; |
261 | interrupts = <0 86 0x04>; | |
33b38587 SH |
262 | clocks = <&clks 62>, <&clks 148>; |
263 | clock-names = "ipg", "per"; | |
7d740f87 SG |
264 | }; |
265 | ||
7b7d6727 | 266 | can1: flexcan@02090000 { |
7d740f87 SG |
267 | reg = <0x02090000 0x4000>; |
268 | interrupts = <0 110 0x04>; | |
269 | }; | |
270 | ||
7b7d6727 | 271 | can2: flexcan@02094000 { |
7d740f87 SG |
272 | reg = <0x02094000 0x4000>; |
273 | interrupts = <0 111 0x04>; | |
274 | }; | |
275 | ||
7b7d6727 | 276 | gpt: gpt@02098000 { |
7d740f87 SG |
277 | compatible = "fsl,imx6q-gpt"; |
278 | reg = <0x02098000 0x4000>; | |
279 | interrupts = <0 55 0x04>; | |
280 | }; | |
281 | ||
4d191868 | 282 | gpio1: gpio@0209c000 { |
aeb27748 | 283 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
284 | reg = <0x0209c000 0x4000>; |
285 | interrupts = <0 66 0x04 0 67 0x04>; | |
286 | gpio-controller; | |
287 | #gpio-cells = <2>; | |
288 | interrupt-controller; | |
88cde8b7 | 289 | #interrupt-cells = <2>; |
7d740f87 SG |
290 | }; |
291 | ||
4d191868 | 292 | gpio2: gpio@020a0000 { |
aeb27748 | 293 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
294 | reg = <0x020a0000 0x4000>; |
295 | interrupts = <0 68 0x04 0 69 0x04>; | |
296 | gpio-controller; | |
297 | #gpio-cells = <2>; | |
298 | interrupt-controller; | |
88cde8b7 | 299 | #interrupt-cells = <2>; |
7d740f87 SG |
300 | }; |
301 | ||
4d191868 | 302 | gpio3: gpio@020a4000 { |
aeb27748 | 303 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
304 | reg = <0x020a4000 0x4000>; |
305 | interrupts = <0 70 0x04 0 71 0x04>; | |
306 | gpio-controller; | |
307 | #gpio-cells = <2>; | |
308 | interrupt-controller; | |
88cde8b7 | 309 | #interrupt-cells = <2>; |
7d740f87 SG |
310 | }; |
311 | ||
4d191868 | 312 | gpio4: gpio@020a8000 { |
aeb27748 | 313 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
314 | reg = <0x020a8000 0x4000>; |
315 | interrupts = <0 72 0x04 0 73 0x04>; | |
316 | gpio-controller; | |
317 | #gpio-cells = <2>; | |
318 | interrupt-controller; | |
88cde8b7 | 319 | #interrupt-cells = <2>; |
7d740f87 SG |
320 | }; |
321 | ||
4d191868 | 322 | gpio5: gpio@020ac000 { |
aeb27748 | 323 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
324 | reg = <0x020ac000 0x4000>; |
325 | interrupts = <0 74 0x04 0 75 0x04>; | |
326 | gpio-controller; | |
327 | #gpio-cells = <2>; | |
328 | interrupt-controller; | |
88cde8b7 | 329 | #interrupt-cells = <2>; |
7d740f87 SG |
330 | }; |
331 | ||
4d191868 | 332 | gpio6: gpio@020b0000 { |
aeb27748 | 333 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
334 | reg = <0x020b0000 0x4000>; |
335 | interrupts = <0 76 0x04 0 77 0x04>; | |
336 | gpio-controller; | |
337 | #gpio-cells = <2>; | |
338 | interrupt-controller; | |
88cde8b7 | 339 | #interrupt-cells = <2>; |
7d740f87 SG |
340 | }; |
341 | ||
4d191868 | 342 | gpio7: gpio@020b4000 { |
aeb27748 | 343 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 SG |
344 | reg = <0x020b4000 0x4000>; |
345 | interrupts = <0 78 0x04 0 79 0x04>; | |
346 | gpio-controller; | |
347 | #gpio-cells = <2>; | |
348 | interrupt-controller; | |
88cde8b7 | 349 | #interrupt-cells = <2>; |
7d740f87 SG |
350 | }; |
351 | ||
7b7d6727 | 352 | kpp: kpp@020b8000 { |
7d740f87 SG |
353 | reg = <0x020b8000 0x4000>; |
354 | interrupts = <0 82 0x04>; | |
355 | }; | |
356 | ||
7b7d6727 | 357 | wdog1: wdog@020bc000 { |
7d740f87 SG |
358 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
359 | reg = <0x020bc000 0x4000>; | |
360 | interrupts = <0 80 0x04>; | |
0e87e043 | 361 | clocks = <&clks 0>; |
7d740f87 SG |
362 | }; |
363 | ||
7b7d6727 | 364 | wdog2: wdog@020c0000 { |
7d740f87 SG |
365 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
366 | reg = <0x020c0000 0x4000>; | |
367 | interrupts = <0 81 0x04>; | |
0e87e043 | 368 | clocks = <&clks 0>; |
7d740f87 SG |
369 | status = "disabled"; |
370 | }; | |
371 | ||
0e87e043 | 372 | clks: ccm@020c4000 { |
7d740f87 SG |
373 | compatible = "fsl,imx6q-ccm"; |
374 | reg = <0x020c4000 0x4000>; | |
375 | interrupts = <0 87 0x04 0 88 0x04>; | |
0e87e043 | 376 | #clock-cells = <1>; |
7d740f87 SG |
377 | }; |
378 | ||
baa64151 DA |
379 | anatop: anatop@020c8000 { |
380 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
7d740f87 SG |
381 | reg = <0x020c8000 0x1000>; |
382 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | |
a1e327e6 YCLP |
383 | |
384 | regulator-1p1@110 { | |
385 | compatible = "fsl,anatop-regulator"; | |
386 | regulator-name = "vdd1p1"; | |
387 | regulator-min-microvolt = <800000>; | |
388 | regulator-max-microvolt = <1375000>; | |
389 | regulator-always-on; | |
390 | anatop-reg-offset = <0x110>; | |
391 | anatop-vol-bit-shift = <8>; | |
392 | anatop-vol-bit-width = <5>; | |
393 | anatop-min-bit-val = <4>; | |
394 | anatop-min-voltage = <800000>; | |
395 | anatop-max-voltage = <1375000>; | |
396 | }; | |
397 | ||
398 | regulator-3p0@120 { | |
399 | compatible = "fsl,anatop-regulator"; | |
400 | regulator-name = "vdd3p0"; | |
401 | regulator-min-microvolt = <2800000>; | |
402 | regulator-max-microvolt = <3150000>; | |
403 | regulator-always-on; | |
404 | anatop-reg-offset = <0x120>; | |
405 | anatop-vol-bit-shift = <8>; | |
406 | anatop-vol-bit-width = <5>; | |
407 | anatop-min-bit-val = <0>; | |
408 | anatop-min-voltage = <2625000>; | |
409 | anatop-max-voltage = <3400000>; | |
410 | }; | |
411 | ||
412 | regulator-2p5@130 { | |
413 | compatible = "fsl,anatop-regulator"; | |
414 | regulator-name = "vdd2p5"; | |
415 | regulator-min-microvolt = <2000000>; | |
416 | regulator-max-microvolt = <2750000>; | |
417 | regulator-always-on; | |
418 | anatop-reg-offset = <0x130>; | |
419 | anatop-vol-bit-shift = <8>; | |
420 | anatop-vol-bit-width = <5>; | |
421 | anatop-min-bit-val = <0>; | |
422 | anatop-min-voltage = <2000000>; | |
423 | anatop-max-voltage = <2750000>; | |
424 | }; | |
425 | ||
96574a6d | 426 | reg_arm: regulator-vddcore@140 { |
a1e327e6 YCLP |
427 | compatible = "fsl,anatop-regulator"; |
428 | regulator-name = "cpu"; | |
429 | regulator-min-microvolt = <725000>; | |
430 | regulator-max-microvolt = <1450000>; | |
431 | regulator-always-on; | |
432 | anatop-reg-offset = <0x140>; | |
433 | anatop-vol-bit-shift = <0>; | |
434 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
435 | anatop-delay-reg-offset = <0x170>; |
436 | anatop-delay-bit-shift = <24>; | |
437 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
438 | anatop-min-bit-val = <1>; |
439 | anatop-min-voltage = <725000>; | |
440 | anatop-max-voltage = <1450000>; | |
441 | }; | |
442 | ||
96574a6d | 443 | reg_pu: regulator-vddpu@140 { |
a1e327e6 YCLP |
444 | compatible = "fsl,anatop-regulator"; |
445 | regulator-name = "vddpu"; | |
446 | regulator-min-microvolt = <725000>; | |
447 | regulator-max-microvolt = <1450000>; | |
448 | regulator-always-on; | |
449 | anatop-reg-offset = <0x140>; | |
450 | anatop-vol-bit-shift = <9>; | |
451 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
452 | anatop-delay-reg-offset = <0x170>; |
453 | anatop-delay-bit-shift = <26>; | |
454 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
455 | anatop-min-bit-val = <1>; |
456 | anatop-min-voltage = <725000>; | |
457 | anatop-max-voltage = <1450000>; | |
458 | }; | |
459 | ||
96574a6d | 460 | reg_soc: regulator-vddsoc@140 { |
a1e327e6 YCLP |
461 | compatible = "fsl,anatop-regulator"; |
462 | regulator-name = "vddsoc"; | |
463 | regulator-min-microvolt = <725000>; | |
464 | regulator-max-microvolt = <1450000>; | |
465 | regulator-always-on; | |
466 | anatop-reg-offset = <0x140>; | |
467 | anatop-vol-bit-shift = <18>; | |
468 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
469 | anatop-delay-reg-offset = <0x170>; |
470 | anatop-delay-bit-shift = <28>; | |
471 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
472 | anatop-min-bit-val = <1>; |
473 | anatop-min-voltage = <725000>; | |
474 | anatop-max-voltage = <1450000>; | |
475 | }; | |
7d740f87 SG |
476 | }; |
477 | ||
74bd88f7 RZ |
478 | usbphy1: usbphy@020c9000 { |
479 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 SG |
480 | reg = <0x020c9000 0x1000>; |
481 | interrupts = <0 44 0x04>; | |
0e87e043 | 482 | clocks = <&clks 182>; |
7d740f87 SG |
483 | }; |
484 | ||
74bd88f7 RZ |
485 | usbphy2: usbphy@020ca000 { |
486 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 SG |
487 | reg = <0x020ca000 0x1000>; |
488 | interrupts = <0 45 0x04>; | |
0e87e043 | 489 | clocks = <&clks 183>; |
7d740f87 SG |
490 | }; |
491 | ||
492 | snvs@020cc000 { | |
c9250388 SG |
493 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
494 | #address-cells = <1>; | |
495 | #size-cells = <1>; | |
496 | ranges = <0 0x020cc000 0x4000>; | |
497 | ||
498 | snvs-rtc-lp@34 { | |
499 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
500 | reg = <0x34 0x58>; | |
501 | interrupts = <0 19 0x04 0 20 0x04>; | |
502 | }; | |
7d740f87 SG |
503 | }; |
504 | ||
7b7d6727 | 505 | epit1: epit@020d0000 { /* EPIT1 */ |
7d740f87 SG |
506 | reg = <0x020d0000 0x4000>; |
507 | interrupts = <0 56 0x04>; | |
508 | }; | |
509 | ||
7b7d6727 | 510 | epit2: epit@020d4000 { /* EPIT2 */ |
7d740f87 SG |
511 | reg = <0x020d4000 0x4000>; |
512 | interrupts = <0 57 0x04>; | |
513 | }; | |
514 | ||
7b7d6727 | 515 | src: src@020d8000 { |
7d740f87 SG |
516 | compatible = "fsl,imx6q-src"; |
517 | reg = <0x020d8000 0x4000>; | |
518 | interrupts = <0 91 0x04 0 96 0x04>; | |
519 | }; | |
520 | ||
7b7d6727 | 521 | gpc: gpc@020dc000 { |
7d740f87 SG |
522 | compatible = "fsl,imx6q-gpc"; |
523 | reg = <0x020dc000 0x4000>; | |
524 | interrupts = <0 89 0x04 0 90 0x04>; | |
525 | }; | |
526 | ||
df37e0c0 DA |
527 | gpr: iomuxc-gpr@020e0000 { |
528 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
529 | reg = <0x020e0000 0x38>; | |
530 | }; | |
531 | ||
7b7d6727 | 532 | dcic1: dcic@020e4000 { |
7d740f87 SG |
533 | reg = <0x020e4000 0x4000>; |
534 | interrupts = <0 124 0x04>; | |
535 | }; | |
536 | ||
7b7d6727 | 537 | dcic2: dcic@020e8000 { |
7d740f87 SG |
538 | reg = <0x020e8000 0x4000>; |
539 | interrupts = <0 125 0x04>; | |
540 | }; | |
541 | ||
7b7d6727 | 542 | sdma: sdma@020ec000 { |
7d740f87 SG |
543 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
544 | reg = <0x020ec000 0x4000>; | |
545 | interrupts = <0 2 0x04>; | |
0e87e043 SG |
546 | clocks = <&clks 155>, <&clks 155>; |
547 | clock-names = "ipg", "ahb"; | |
d6b9c591 | 548 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
549 | }; |
550 | }; | |
551 | ||
552 | aips-bus@02100000 { /* AIPS2 */ | |
553 | compatible = "fsl,aips-bus", "simple-bus"; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <1>; | |
556 | reg = <0x02100000 0x100000>; | |
557 | ranges; | |
558 | ||
559 | caam@02100000 { | |
560 | reg = <0x02100000 0x40000>; | |
561 | interrupts = <0 105 0x04 0 106 0x04>; | |
562 | }; | |
563 | ||
564 | aipstz@0217c000 { /* AIPSTZ2 */ | |
565 | reg = <0x0217c000 0x4000>; | |
566 | }; | |
567 | ||
7b7d6727 | 568 | usbotg: usb@02184000 { |
74bd88f7 RZ |
569 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
570 | reg = <0x02184000 0x200>; | |
571 | interrupts = <0 43 0x04>; | |
0e87e043 | 572 | clocks = <&clks 162>; |
74bd88f7 | 573 | fsl,usbphy = <&usbphy1>; |
28342c61 | 574 | fsl,usbmisc = <&usbmisc 0>; |
74bd88f7 RZ |
575 | status = "disabled"; |
576 | }; | |
577 | ||
7b7d6727 | 578 | usbh1: usb@02184200 { |
74bd88f7 RZ |
579 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
580 | reg = <0x02184200 0x200>; | |
581 | interrupts = <0 40 0x04>; | |
0e87e043 | 582 | clocks = <&clks 162>; |
74bd88f7 | 583 | fsl,usbphy = <&usbphy2>; |
28342c61 | 584 | fsl,usbmisc = <&usbmisc 1>; |
74bd88f7 RZ |
585 | status = "disabled"; |
586 | }; | |
587 | ||
7b7d6727 | 588 | usbh2: usb@02184400 { |
74bd88f7 RZ |
589 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
590 | reg = <0x02184400 0x200>; | |
591 | interrupts = <0 41 0x04>; | |
0e87e043 | 592 | clocks = <&clks 162>; |
28342c61 | 593 | fsl,usbmisc = <&usbmisc 2>; |
74bd88f7 RZ |
594 | status = "disabled"; |
595 | }; | |
596 | ||
7b7d6727 | 597 | usbh3: usb@02184600 { |
74bd88f7 RZ |
598 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
599 | reg = <0x02184600 0x200>; | |
600 | interrupts = <0 42 0x04>; | |
0e87e043 | 601 | clocks = <&clks 162>; |
28342c61 | 602 | fsl,usbmisc = <&usbmisc 3>; |
74bd88f7 RZ |
603 | status = "disabled"; |
604 | }; | |
605 | ||
7b7d6727 | 606 | usbmisc: usbmisc: usbmisc@02184800 { |
28342c61 RZ |
607 | #index-cells = <1>; |
608 | compatible = "fsl,imx6q-usbmisc"; | |
609 | reg = <0x02184800 0x200>; | |
610 | clocks = <&clks 162>; | |
611 | }; | |
612 | ||
7b7d6727 | 613 | fec: ethernet@02188000 { |
7d740f87 SG |
614 | compatible = "fsl,imx6q-fec"; |
615 | reg = <0x02188000 0x4000>; | |
616 | interrupts = <0 118 0x04 0 119 0x04>; | |
8dd5c66b | 617 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
7629838c | 618 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
619 | status = "disabled"; |
620 | }; | |
621 | ||
622 | mlb@0218c000 { | |
623 | reg = <0x0218c000 0x4000>; | |
624 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; | |
625 | }; | |
626 | ||
7b7d6727 | 627 | usdhc1: usdhc@02190000 { |
7d740f87 SG |
628 | compatible = "fsl,imx6q-usdhc"; |
629 | reg = <0x02190000 0x4000>; | |
630 | interrupts = <0 22 0x04>; | |
0e87e043 SG |
631 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
632 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 633 | bus-width = <4>; |
7d740f87 SG |
634 | status = "disabled"; |
635 | }; | |
636 | ||
7b7d6727 | 637 | usdhc2: usdhc@02194000 { |
7d740f87 SG |
638 | compatible = "fsl,imx6q-usdhc"; |
639 | reg = <0x02194000 0x4000>; | |
640 | interrupts = <0 23 0x04>; | |
0e87e043 SG |
641 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
642 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 643 | bus-width = <4>; |
7d740f87 SG |
644 | status = "disabled"; |
645 | }; | |
646 | ||
7b7d6727 | 647 | usdhc3: usdhc@02198000 { |
7d740f87 SG |
648 | compatible = "fsl,imx6q-usdhc"; |
649 | reg = <0x02198000 0x4000>; | |
650 | interrupts = <0 24 0x04>; | |
0e87e043 SG |
651 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
652 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 653 | bus-width = <4>; |
7d740f87 SG |
654 | status = "disabled"; |
655 | }; | |
656 | ||
7b7d6727 | 657 | usdhc4: usdhc@0219c000 { |
7d740f87 SG |
658 | compatible = "fsl,imx6q-usdhc"; |
659 | reg = <0x0219c000 0x4000>; | |
660 | interrupts = <0 25 0x04>; | |
0e87e043 SG |
661 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
662 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 663 | bus-width = <4>; |
7d740f87 SG |
664 | status = "disabled"; |
665 | }; | |
666 | ||
7b7d6727 | 667 | i2c1: i2c@021a0000 { |
7d740f87 SG |
668 | #address-cells = <1>; |
669 | #size-cells = <0>; | |
5bdfba29 | 670 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
671 | reg = <0x021a0000 0x4000>; |
672 | interrupts = <0 36 0x04>; | |
0e87e043 | 673 | clocks = <&clks 125>; |
7d740f87 SG |
674 | status = "disabled"; |
675 | }; | |
676 | ||
7b7d6727 | 677 | i2c2: i2c@021a4000 { |
7d740f87 SG |
678 | #address-cells = <1>; |
679 | #size-cells = <0>; | |
5bdfba29 | 680 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
681 | reg = <0x021a4000 0x4000>; |
682 | interrupts = <0 37 0x04>; | |
0e87e043 | 683 | clocks = <&clks 126>; |
7d740f87 SG |
684 | status = "disabled"; |
685 | }; | |
686 | ||
7b7d6727 | 687 | i2c3: i2c@021a8000 { |
7d740f87 SG |
688 | #address-cells = <1>; |
689 | #size-cells = <0>; | |
5bdfba29 | 690 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 SG |
691 | reg = <0x021a8000 0x4000>; |
692 | interrupts = <0 38 0x04>; | |
0e87e043 | 693 | clocks = <&clks 127>; |
7d740f87 SG |
694 | status = "disabled"; |
695 | }; | |
696 | ||
697 | romcp@021ac000 { | |
698 | reg = <0x021ac000 0x4000>; | |
699 | }; | |
700 | ||
7b7d6727 | 701 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
7d740f87 SG |
702 | compatible = "fsl,imx6q-mmdc"; |
703 | reg = <0x021b0000 0x4000>; | |
704 | }; | |
705 | ||
7b7d6727 | 706 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
7d740f87 SG |
707 | reg = <0x021b4000 0x4000>; |
708 | }; | |
709 | ||
710 | weim@021b8000 { | |
711 | reg = <0x021b8000 0x4000>; | |
712 | interrupts = <0 14 0x04>; | |
713 | }; | |
714 | ||
715 | ocotp@021bc000 { | |
96574a6d | 716 | compatible = "fsl,imx6q-ocotp"; |
7d740f87 SG |
717 | reg = <0x021bc000 0x4000>; |
718 | }; | |
719 | ||
720 | ocotp@021c0000 { | |
721 | reg = <0x021c0000 0x4000>; | |
722 | interrupts = <0 21 0x04>; | |
723 | }; | |
724 | ||
725 | tzasc@021d0000 { /* TZASC1 */ | |
726 | reg = <0x021d0000 0x4000>; | |
727 | interrupts = <0 108 0x04>; | |
728 | }; | |
729 | ||
730 | tzasc@021d4000 { /* TZASC2 */ | |
731 | reg = <0x021d4000 0x4000>; | |
732 | interrupts = <0 109 0x04>; | |
733 | }; | |
734 | ||
7b7d6727 | 735 | audmux: audmux@021d8000 { |
f965cd55 | 736 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 737 | reg = <0x021d8000 0x4000>; |
f965cd55 | 738 | status = "disabled"; |
7d740f87 SG |
739 | }; |
740 | ||
741 | mipi@021dc000 { /* MIPI-CSI */ | |
742 | reg = <0x021dc000 0x4000>; | |
743 | }; | |
744 | ||
745 | mipi@021e0000 { /* MIPI-DSI */ | |
746 | reg = <0x021e0000 0x4000>; | |
747 | }; | |
748 | ||
749 | vdoa@021e4000 { | |
750 | reg = <0x021e4000 0x4000>; | |
751 | interrupts = <0 18 0x04>; | |
752 | }; | |
753 | ||
0c456cfa | 754 | uart2: serial@021e8000 { |
7d740f87 SG |
755 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
756 | reg = <0x021e8000 0x4000>; | |
757 | interrupts = <0 27 0x04>; | |
0e87e043 SG |
758 | clocks = <&clks 160>, <&clks 161>; |
759 | clock-names = "ipg", "per"; | |
7d740f87 SG |
760 | status = "disabled"; |
761 | }; | |
762 | ||
0c456cfa | 763 | uart3: serial@021ec000 { |
7d740f87 SG |
764 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
765 | reg = <0x021ec000 0x4000>; | |
766 | interrupts = <0 28 0x04>; | |
0e87e043 SG |
767 | clocks = <&clks 160>, <&clks 161>; |
768 | clock-names = "ipg", "per"; | |
7d740f87 SG |
769 | status = "disabled"; |
770 | }; | |
771 | ||
0c456cfa | 772 | uart4: serial@021f0000 { |
7d740f87 SG |
773 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
774 | reg = <0x021f0000 0x4000>; | |
775 | interrupts = <0 29 0x04>; | |
0e87e043 SG |
776 | clocks = <&clks 160>, <&clks 161>; |
777 | clock-names = "ipg", "per"; | |
7d740f87 SG |
778 | status = "disabled"; |
779 | }; | |
780 | ||
0c456cfa | 781 | uart5: serial@021f4000 { |
7d740f87 SG |
782 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
783 | reg = <0x021f4000 0x4000>; | |
784 | interrupts = <0 30 0x04>; | |
0e87e043 SG |
785 | clocks = <&clks 160>, <&clks 161>; |
786 | clock-names = "ipg", "per"; | |
7d740f87 SG |
787 | status = "disabled"; |
788 | }; | |
789 | }; | |
91660d74 SH |
790 | |
791 | ipu1: ipu@02400000 { | |
792 | #crtc-cells = <1>; | |
793 | compatible = "fsl,imx6q-ipu"; | |
794 | reg = <0x02400000 0x400000>; | |
795 | interrupts = <0 6 0x4 0 5 0x4>; | |
796 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; | |
797 | clock-names = "bus", "di0", "di1"; | |
798 | }; | |
7d740f87 SG |
799 | }; |
800 | }; |