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ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
7d740f87
SG		 14
15/ {
16 aliases {
5f8fbc2c
LW		 17 can0 = &can1;
18 can1 = &can2;
5230f8fe
SG		 19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 gpio5 = &gpio6;
25 gpio6 = &gpio7;
80fa0584
SH		 26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 spi0 = &ecspi1;
35 spi1 = &ecspi2;
36 spi2 = &ecspi3;
37 spi3 = &ecspi4;
7d740f87
SG		 38 };
39
7d740f87
SG		 40 intc: interrupt-controller@00a01000 {
41 compatible = "arm,cortex-a9-gic";
42 #interrupt-cells = <3>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 interrupt-controller;
46 reg = <0x00a01000 0x1000>,
47 <0x00a00100 0x100>;
48 };
49
50 clocks {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ckil {
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 clock-frequency = <32768>;
57 };
58
59 ckih1 {
60 compatible = "fsl,imx-ckih1", "fixed-clock";
61 clock-frequency = <0>;
62 };
63
64 osc {
65 compatible = "fsl,imx-osc", "fixed-clock";
66 clock-frequency = <24000000>;
67 };
68 };
69
70 soc {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "simple-bus";
74 interrupt-parent = <&intc>;
75 ranges;
76
f30fb03d 77 dma_apbh: dma-apbh@00110000 {
e5d0f9f5
HS		 78 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
79 reg = <0x00110000 0x2000>;
275c08b5
TK		 80 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
81 <0 13 IRQ_TYPE_LEVEL_HIGH>,
82 <0 13 IRQ_TYPE_LEVEL_HIGH>,
83 <0 13 IRQ_TYPE_LEVEL_HIGH>;
f30fb03d
SG		 84 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
85 #dma-cells = <1>;
86 dma-channels = <4>;
0e87e043 87 clocks = <&clks 106>;
e5d0f9f5
HS		 88 };
89
be4ccfce 90 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 91 compatible = "fsl,imx6q-gpmi-nand";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
95 reg-names = "gpmi-nand", "bch";
275c08b5 96 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
c7aa12a6 97 interrupt-names = "bch";
0e87e043
SG		 98 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
99 <&clks 150>, <&clks 149>;
100 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
101 "gpmi_bch_apb", "per1_bch";
f30fb03d
SG		 102 dmas = <&dma_apbh 0>;
103 dma-names = "rx-tx";
0e87e043 104 status = "disabled";
cf922fa8
HS		 105 };
106
7d740f87 107 timer@00a00600 {
58458e03
MZ		 108 compatible = "arm,cortex-a9-twd-timer";
109 reg = <0x00a00600 0x20>;
110 interrupts = <1 13 0xf01>;
2bb4b70b 111 clocks = <&clks 15>;
7d740f87
SG		 112 };
113
114 L2: l2-cache@00a02000 {
115 compatible = "arm,pl310-cache";
116 reg = <0x00a02000 0x1000>;
275c08b5 117 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 118 cache-unified;
119 cache-level = <2>;
5a5ca56e
DB		 120 arm,tag-latency = <4 2 3>;
121 arm,data-latency = <4 2 3>;
7d740f87
SG		 122 };
123
3a57291f
SC		 124 pcie: pcie@0x01000000 {
125 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
126 reg = <0x01ffc000 0x4000>; /* DBI */
127 #address-cells = <3>;
128 #size-cells = <2>;
129 device_type = "pci";
130 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
131 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
132 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
133 num-lanes = <1>;
275c08b5 134 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
3a57291f
SC		 135 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
136 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
137 status = "disabled";
138 };
139
218abe6f
DB		 140 pmu {
141 compatible = "arm,cortex-a9-pmu";
275c08b5 142 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
218abe6f
DB		 143 };
144
7d740f87
SG		 145 aips-bus@02000000 { /* AIPS1 */
146 compatible = "fsl,aips-bus", "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0x02000000 0x100000>;
150 ranges;
151
152 spba-bus@02000000 {
153 compatible = "fsl,spba-bus", "simple-bus";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 reg = <0x02000000 0x40000>;
157 ranges;
158
7b7d6727 159 spdif: spdif@02004000 {
c9d96df2 160 compatible = "fsl,imx35-spdif";
7d740f87 161 reg = <0x02004000 0x4000>;
275c08b5 162 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
c9d96df2
FE		 163 dmas = <&sdma 14 18 0>,
164 <&sdma 15 18 0>;
165 dma-names = "rx", "tx";
166 clocks = <&clks 197>, <&clks 3>,
167 <&clks 197>, <&clks 107>,
168 <&clks 0>, <&clks 118>,
793b4b10 169 <&clks 0>, <&clks 139>,
c9d96df2
FE		 170 <&clks 0>;
171 clock-names = "core", "rxtx0",
172 "rxtx1", "rxtx2",
173 "rxtx3", "rxtx4",
174 "rxtx5", "rxtx6",
175 "rxtx7";
176 status = "disabled";
7d740f87
SG		 177 };
178
7b7d6727 179 ecspi1: ecspi@02008000 {
7d740f87
SG		 180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
183 reg = <0x02008000 0x4000>;
275c08b5 184 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 185 clocks = <&clks 112>, <&clks 112>;
186 clock-names = "ipg", "per";
7d740f87
SG		 187 status = "disabled";
188 };
189
7b7d6727 190 ecspi2: ecspi@0200c000 {
7d740f87
SG		 191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
194 reg = <0x0200c000 0x4000>;
275c08b5 195 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 196 clocks = <&clks 113>, <&clks 113>;
197 clock-names = "ipg", "per";
7d740f87
SG		 198 status = "disabled";
199 };
200
7b7d6727 201 ecspi3: ecspi@02010000 {
7d740f87
SG		 202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
205 reg = <0x02010000 0x4000>;
275c08b5 206 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 207 clocks = <&clks 114>, <&clks 114>;
208 clock-names = "ipg", "per";
7d740f87
SG		 209 status = "disabled";
210 };
211
7b7d6727 212 ecspi4: ecspi@02014000 {
7d740f87
SG		 213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
216 reg = <0x02014000 0x4000>;
275c08b5 217 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 218 clocks = <&clks 115>, <&clks 115>;
219 clock-names = "ipg", "per";
7d740f87
SG		 220 status = "disabled";
221 };
222
0c456cfa 223 uart1: serial@02020000 {
7d740f87
SG		 224 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
225 reg = <0x02020000 0x4000>;
275c08b5 226 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 227 clocks = <&clks 160>, <&clks 161>;
228 clock-names = "ipg", "per";
72a5cebf
HS		 229 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
230 dma-names = "rx", "tx";
7d740f87
SG		 231 status = "disabled";
232 };
233
7b7d6727 234 esai: esai@02024000 {
7d740f87 235 reg = <0x02024000 0x4000>;
275c08b5 236 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 237 };
238
b1a5da8e
RZ		 239 ssi1: ssi@02028000 {
240 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87 241 reg = <0x02028000 0x4000>;
275c08b5 242 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 243 clocks = <&clks 178>;
5da826ab
SG		 244 dmas = <&sdma 37 1 0>,
245 <&sdma 38 1 0>;
246 dma-names = "rx", "tx";
b1a5da8e
RZ		 247 fsl,fifo-depth = <15>;
248 fsl,ssi-dma-events = <38 37>;
249 status = "disabled";
7d740f87
SG		 250 };
251
b1a5da8e
RZ		 252 ssi2: ssi@0202c000 {
253 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87 254 reg = <0x0202c000 0x4000>;
275c08b5 255 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 256 clocks = <&clks 179>;
5da826ab
SG		 257 dmas = <&sdma 41 1 0>,
258 <&sdma 42 1 0>;
259 dma-names = "rx", "tx";
b1a5da8e
RZ		 260 fsl,fifo-depth = <15>;
261 fsl,ssi-dma-events = <42 41>;
262 status = "disabled";
7d740f87
SG		 263 };
264
b1a5da8e
RZ		 265 ssi3: ssi@02030000 {
266 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87 267 reg = <0x02030000 0x4000>;
275c08b5 268 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 269 clocks = <&clks 180>;
5da826ab
SG		 270 dmas = <&sdma 45 1 0>,
271 <&sdma 46 1 0>;
272 dma-names = "rx", "tx";
b1a5da8e
RZ		 273 fsl,fifo-depth = <15>;
274 fsl,ssi-dma-events = <46 45>;
275 status = "disabled";
7d740f87
SG		 276 };
277
7b7d6727 278 asrc: asrc@02034000 {
7d740f87 279 reg = <0x02034000 0x4000>;
275c08b5 280 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 281 };
282
283 spba@0203c000 {
284 reg = <0x0203c000 0x4000>;
285 };
286 };
287
7b7d6727 288 vpu: vpu@02040000 {
7d740f87 289 reg = <0x02040000 0x3c000>;
275c08b5
TK		 290 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
291 <0 12 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 292 };
293
294 aipstz@0207c000 { /* AIPSTZ1 */
295 reg = <0x0207c000 0x4000>;
296 };
297
7b7d6727 298 pwm1: pwm@02080000 {
33b38587
SH		 299 #pwm-cells = <2>;
300 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 301 reg = <0x02080000 0x4000>;
275c08b5 302 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 303 clocks = <&clks 62>, <&clks 145>;
304 clock-names = "ipg", "per";
7d740f87
SG		 305 };
306
7b7d6727 307 pwm2: pwm@02084000 {
33b38587
SH		 308 #pwm-cells = <2>;
309 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 310 reg = <0x02084000 0x4000>;
275c08b5 311 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 312 clocks = <&clks 62>, <&clks 146>;
313 clock-names = "ipg", "per";
7d740f87
SG		 314 };
315
7b7d6727 316 pwm3: pwm@02088000 {
33b38587
SH		 317 #pwm-cells = <2>;
318 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 319 reg = <0x02088000 0x4000>;
275c08b5 320 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 321 clocks = <&clks 62>, <&clks 147>;
322 clock-names = "ipg", "per";
7d740f87
SG		 323 };
324
7b7d6727 325 pwm4: pwm@0208c000 {
33b38587
SH		 326 #pwm-cells = <2>;
327 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 328 reg = <0x0208c000 0x4000>;
275c08b5 329 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 330 clocks = <&clks 62>, <&clks 148>;
331 clock-names = "ipg", "per";
7d740f87
SG		 332 };
333
7b7d6727 334 can1: flexcan@02090000 {
0f225212 335 compatible = "fsl,imx6q-flexcan";
7d740f87 336 reg = <0x02090000 0x4000>;
275c08b5 337 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
0f225212
SH		 338 clocks = <&clks 108>, <&clks 109>;
339 clock-names = "ipg", "per";
a1135337 340 status = "disabled";
7d740f87
SG		 341 };
342
7b7d6727 343 can2: flexcan@02094000 {
0f225212 344 compatible = "fsl,imx6q-flexcan";
7d740f87 345 reg = <0x02094000 0x4000>;
275c08b5 346 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
0f225212
SH		 347 clocks = <&clks 110>, <&clks 111>;
348 clock-names = "ipg", "per";
a1135337 349 status = "disabled";
7d740f87
SG		 350 };
351
7b7d6727 352 gpt: gpt@02098000 {
97b108f9 353 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
7d740f87 354 reg = <0x02098000 0x4000>;
275c08b5 355 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
4efccadd
SH		 356 clocks = <&clks 119>, <&clks 120>;
357 clock-names = "ipg", "per";
7d740f87
SG		 358 };
359
4d191868 360 gpio1: gpio@0209c000 {
aeb27748 361 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 362 reg = <0x0209c000 0x4000>;
275c08b5
TK		 363 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
364 <0 67 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 365 gpio-controller;
366 #gpio-cells = <2>;
367 interrupt-controller;
88cde8b7 368 #interrupt-cells = <2>;
7d740f87
SG		 369 };
370
4d191868 371 gpio2: gpio@020a0000 {
aeb27748 372 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 373 reg = <0x020a0000 0x4000>;
275c08b5
TK		 374 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
375 <0 69 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 376 gpio-controller;
377 #gpio-cells = <2>;
378 interrupt-controller;
88cde8b7 379 #interrupt-cells = <2>;
7d740f87
SG		 380 };
381
4d191868 382 gpio3: gpio@020a4000 {
aeb27748 383 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 384 reg = <0x020a4000 0x4000>;
275c08b5
TK		 385 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
386 <0 71 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 387 gpio-controller;
388 #gpio-cells = <2>;
389 interrupt-controller;
88cde8b7 390 #interrupt-cells = <2>;
7d740f87
SG		 391 };
392
4d191868 393 gpio4: gpio@020a8000 {
aeb27748 394 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 395 reg = <0x020a8000 0x4000>;
275c08b5
TK		 396 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
397 <0 73 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 398 gpio-controller;
399 #gpio-cells = <2>;
400 interrupt-controller;
88cde8b7 401 #interrupt-cells = <2>;
7d740f87
SG		 402 };
403
4d191868 404 gpio5: gpio@020ac000 {
aeb27748 405 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 406 reg = <0x020ac000 0x4000>;
275c08b5
TK		 407 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
408 <0 75 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupt-controller;
88cde8b7 412 #interrupt-cells = <2>;
7d740f87
SG		 413 };
414
4d191868 415 gpio6: gpio@020b0000 {
aeb27748 416 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 417 reg = <0x020b0000 0x4000>;
275c08b5
TK		 418 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
419 <0 77 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
88cde8b7 423 #interrupt-cells = <2>;
7d740f87
SG		 424 };
425
4d191868 426 gpio7: gpio@020b4000 {
aeb27748 427 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 428 reg = <0x020b4000 0x4000>;
275c08b5
TK		 429 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
430 <0 79 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
88cde8b7 434 #interrupt-cells = <2>;
7d740f87
SG		 435 };
436
7b7d6727 437 kpp: kpp@020b8000 {
7d740f87 438 reg = <0x020b8000 0x4000>;
275c08b5 439 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 440 };
441
7b7d6727 442 wdog1: wdog@020bc000 {
7d740f87
SG		 443 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
444 reg = <0x020bc000 0x4000>;
275c08b5 445 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 446 clocks = <&clks 0>;
7d740f87
SG		 447 };
448
7b7d6727 449 wdog2: wdog@020c0000 {
7d740f87
SG		 450 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
451 reg = <0x020c0000 0x4000>;
275c08b5 452 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 453 clocks = <&clks 0>;
7d740f87
SG		 454 status = "disabled";
455 };
456
0e87e043 457 clks: ccm@020c4000 {
7d740f87
SG		 458 compatible = "fsl,imx6q-ccm";
459 reg = <0x020c4000 0x4000>;
275c08b5
TK		 460 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
461 <0 88 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 462 #clock-cells = <1>;
7d740f87
SG		 463 };
464
baa64151
DA		 465 anatop: anatop@020c8000 {
466 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87 467 reg = <0x020c8000 0x1000>;
275c08b5
TK		 468 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
469 <0 54 IRQ_TYPE_LEVEL_HIGH>,
470 <0 127 IRQ_TYPE_LEVEL_HIGH>;
a1e327e6
YCLP		 471
472 regulator-1p1@110 {
473 compatible = "fsl,anatop-regulator";
474 regulator-name = "vdd1p1";
475 regulator-min-microvolt = <800000>;
476 regulator-max-microvolt = <1375000>;
477 regulator-always-on;
478 anatop-reg-offset = <0x110>;
479 anatop-vol-bit-shift = <8>;
480 anatop-vol-bit-width = <5>;
481 anatop-min-bit-val = <4>;
482 anatop-min-voltage = <800000>;
483 anatop-max-voltage = <1375000>;
484 };
485
486 regulator-3p0@120 {
487 compatible = "fsl,anatop-regulator";
488 regulator-name = "vdd3p0";
489 regulator-min-microvolt = <2800000>;
490 regulator-max-microvolt = <3150000>;
491 regulator-always-on;
492 anatop-reg-offset = <0x120>;
493 anatop-vol-bit-shift = <8>;
494 anatop-vol-bit-width = <5>;
495 anatop-min-bit-val = <0>;
496 anatop-min-voltage = <2625000>;
497 anatop-max-voltage = <3400000>;
498 };
499
500 regulator-2p5@130 {
501 compatible = "fsl,anatop-regulator";
502 regulator-name = "vdd2p5";
503 regulator-min-microvolt = <2000000>;
504 regulator-max-microvolt = <2750000>;
505 regulator-always-on;
506 anatop-reg-offset = <0x130>;
507 anatop-vol-bit-shift = <8>;
508 anatop-vol-bit-width = <5>;
509 anatop-min-bit-val = <0>;
510 anatop-min-voltage = <2000000>;
511 anatop-max-voltage = <2750000>;
512 };
513
96574a6d 514 reg_arm: regulator-vddcore@140 {
a1e327e6 515 compatible = "fsl,anatop-regulator";
118c98a6 516 regulator-name = "vddarm";
a1e327e6
YCLP		 517 regulator-min-microvolt = <725000>;
518 regulator-max-microvolt = <1450000>;
519 regulator-always-on;
520 anatop-reg-offset = <0x140>;
521 anatop-vol-bit-shift = <0>;
522 anatop-vol-bit-width = <5>;
46743dd6
AH		 523 anatop-delay-reg-offset = <0x170>;
524 anatop-delay-bit-shift = <24>;
525 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 526 anatop-min-bit-val = <1>;
527 anatop-min-voltage = <725000>;
528 anatop-max-voltage = <1450000>;
529 };
530
96574a6d 531 reg_pu: regulator-vddpu@140 {
a1e327e6
YCLP		 532 compatible = "fsl,anatop-regulator";
533 regulator-name = "vddpu";
534 regulator-min-microvolt = <725000>;
535 regulator-max-microvolt = <1450000>;
536 regulator-always-on;
537 anatop-reg-offset = <0x140>;
538 anatop-vol-bit-shift = <9>;
539 anatop-vol-bit-width = <5>;
46743dd6
AH		 540 anatop-delay-reg-offset = <0x170>;
541 anatop-delay-bit-shift = <26>;
542 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 543 anatop-min-bit-val = <1>;
544 anatop-min-voltage = <725000>;
545 anatop-max-voltage = <1450000>;
546 };
547
96574a6d 548 reg_soc: regulator-vddsoc@140 {
a1e327e6
YCLP		 549 compatible = "fsl,anatop-regulator";
550 regulator-name = "vddsoc";
551 regulator-min-microvolt = <725000>;
552 regulator-max-microvolt = <1450000>;
553 regulator-always-on;
554 anatop-reg-offset = <0x140>;
555 anatop-vol-bit-shift = <18>;
556 anatop-vol-bit-width = <5>;
46743dd6
AH		 557 anatop-delay-reg-offset = <0x170>;
558 anatop-delay-bit-shift = <28>;
559 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 560 anatop-min-bit-val = <1>;
561 anatop-min-voltage = <725000>;
562 anatop-max-voltage = <1450000>;
563 };
7d740f87
SG		 564 };
565
3fe6373b
SG		 566 tempmon: tempmon {
567 compatible = "fsl,imx6q-tempmon";
275c08b5 568 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
3fe6373b
SG		 569 fsl,tempmon = <&anatop>;
570 fsl,tempmon-data = <&ocotp>;
f430d19c 571 clocks = <&clks 172>;
3fe6373b
SG		 572 };
573
74bd88f7
RZ		 574 usbphy1: usbphy@020c9000 {
575 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87 576 reg = <0x020c9000 0x1000>;
275c08b5 577 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 578 clocks = <&clks 182>;
7d740f87
SG		 579 };
580
74bd88f7
RZ		 581 usbphy2: usbphy@020ca000 {
582 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87 583 reg = <0x020ca000 0x1000>;
275c08b5 584 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 585 clocks = <&clks 183>;
7d740f87
SG		 586 };
587
588 snvs@020cc000 {
c9250388
SG		 589 compatible = "fsl,sec-v4.0-mon", "simple-bus";
590 #address-cells = <1>;
591 #size-cells = <1>;
592 ranges = <0 0x020cc000 0x4000>;
593
594 snvs-rtc-lp@34 {
595 compatible = "fsl,sec-v4.0-mon-rtc-lp";
596 reg = <0x34 0x58>;
275c08b5
TK		 597 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
598 <0 20 IRQ_TYPE_LEVEL_HIGH>;
c9250388 599 };
7d740f87
SG		 600 };
601
7b7d6727 602 epit1: epit@020d0000 { /* EPIT1 */
7d740f87 603 reg = <0x020d0000 0x4000>;
275c08b5 604 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 605 };
606
7b7d6727 607 epit2: epit@020d4000 { /* EPIT2 */
7d740f87 608 reg = <0x020d4000 0x4000>;
275c08b5 609 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 610 };
611
7b7d6727 612 src: src@020d8000 {
bd3d924d 613 compatible = "fsl,imx6q-src", "fsl,imx51-src";
7d740f87 614 reg = <0x020d8000 0x4000>;
275c08b5
TK		 615 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
616 <0 96 IRQ_TYPE_LEVEL_HIGH>;
09ebf366 617 #reset-cells = <1>;
7d740f87
SG		 618 };
619
7b7d6727 620 gpc: gpc@020dc000 {
7d740f87
SG		 621 compatible = "fsl,imx6q-gpc";
622 reg = <0x020dc000 0x4000>;
275c08b5
TK		 623 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
624 <0 90 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 625 };
626
df37e0c0
DA		 627 gpr: iomuxc-gpr@020e0000 {
628 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
629 reg = <0x020e0000 0x38>;
630 };
631
c56009b2
SG		 632 iomuxc: iomuxc@020e0000 {
633 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
634 reg = <0x020e0000 0x4000>;
c56009b2
SG		 635 };
636
41c04342
ST		 637 ldb: ldb@020e0008 {
638 #address-cells = <1>;
639 #size-cells = <0>;
640 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
641 gpr = <&gpr>;
642 status = "disabled";
643
644 lvds-channel@0 {
645 reg = <0>;
41c04342
ST		 646 status = "disabled";
647 };
648
649 lvds-channel@1 {
650 reg = <1>;
41c04342
ST		 651 status = "disabled";
652 };
653 };
654
7b7d6727 655 dcic1: dcic@020e4000 {
7d740f87 656 reg = <0x020e4000 0x4000>;
275c08b5 657 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 658 };
659
7b7d6727 660 dcic2: dcic@020e8000 {
7d740f87 661 reg = <0x020e8000 0x4000>;
275c08b5 662 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 663 };
664
7b7d6727 665 sdma: sdma@020ec000 {
7d740f87
SG		 666 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
667 reg = <0x020ec000 0x4000>;
275c08b5 668 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 669 clocks = <&clks 155>, <&clks 155>;
670 clock-names = "ipg", "ahb";
fb72bb21 671 #dma-cells = <3>;
d6b9c591 672 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 673 };
674 };
675
676 aips-bus@02100000 { /* AIPS2 */
677 compatible = "fsl,aips-bus", "simple-bus";
678 #address-cells = <1>;
679 #size-cells = <1>;
680 reg = <0x02100000 0x100000>;
681 ranges;
682
683 caam@02100000 {
684 reg = <0x02100000 0x40000>;
275c08b5
TK		 685 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
686 <0 106 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 687 };
688
689 aipstz@0217c000 { /* AIPSTZ2 */
690 reg = <0x0217c000 0x4000>;
691 };
692
7b7d6727 693 usbotg: usb@02184000 {
74bd88f7
RZ		 694 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
695 reg = <0x02184000 0x200>;
275c08b5 696 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 697 clocks = <&clks 162>;
74bd88f7 698 fsl,usbphy = <&usbphy1>;
28342c61 699 fsl,usbmisc = <&usbmisc 0>;
74bd88f7
RZ		 700 status = "disabled";
701 };
702
7b7d6727 703 usbh1: usb@02184200 {
74bd88f7
RZ		 704 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
705 reg = <0x02184200 0x200>;
275c08b5 706 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 707 clocks = <&clks 162>;
74bd88f7 708 fsl,usbphy = <&usbphy2>;
28342c61 709 fsl,usbmisc = <&usbmisc 1>;
74bd88f7
RZ		 710 status = "disabled";
711 };
712
7b7d6727 713 usbh2: usb@02184400 {
74bd88f7
RZ		 714 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
715 reg = <0x02184400 0x200>;
275c08b5 716 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 717 clocks = <&clks 162>;
28342c61 718 fsl,usbmisc = <&usbmisc 2>;
74bd88f7
RZ		 719 status = "disabled";
720 };
721
7b7d6727 722 usbh3: usb@02184600 {
74bd88f7
RZ		 723 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
724 reg = <0x02184600 0x200>;
275c08b5 725 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 726 clocks = <&clks 162>;
28342c61 727 fsl,usbmisc = <&usbmisc 3>;
74bd88f7
RZ		 728 status = "disabled";
729 };
730
60984bdf 731 usbmisc: usbmisc@02184800 {
28342c61
RZ		 732 #index-cells = <1>;
733 compatible = "fsl,imx6q-usbmisc";
734 reg = <0x02184800 0x200>;
735 clocks = <&clks 162>;
736 };
737
7b7d6727 738 fec: ethernet@02188000 {
7d740f87
SG		 739 compatible = "fsl,imx6q-fec";
740 reg = <0x02188000 0x4000>;
275c08b5
TK		 741 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
742 <0 119 IRQ_TYPE_LEVEL_HIGH>;
8dd5c66b 743 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
7629838c 744 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 745 status = "disabled";
746 };
747
748 mlb@0218c000 {
749 reg = <0x0218c000 0x4000>;
275c08b5
TK		 750 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
751 <0 117 IRQ_TYPE_LEVEL_HIGH>,
752 <0 126 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 753 };
754
7b7d6727 755 usdhc1: usdhc@02190000 {
7d740f87
SG		 756 compatible = "fsl,imx6q-usdhc";
757 reg = <0x02190000 0x4000>;
275c08b5 758 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 759 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
760 clock-names = "ipg", "ahb", "per";
c104b6a2 761 bus-width = <4>;
7d740f87
SG		 762 status = "disabled";
763 };
764
7b7d6727 765 usdhc2: usdhc@02194000 {
7d740f87
SG		 766 compatible = "fsl,imx6q-usdhc";
767 reg = <0x02194000 0x4000>;
275c08b5 768 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 769 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
770 clock-names = "ipg", "ahb", "per";
c104b6a2 771 bus-width = <4>;
7d740f87
SG		 772 status = "disabled";
773 };
774
7b7d6727 775 usdhc3: usdhc@02198000 {
7d740f87
SG		 776 compatible = "fsl,imx6q-usdhc";
777 reg = <0x02198000 0x4000>;
275c08b5 778 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 779 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
780 clock-names = "ipg", "ahb", "per";
c104b6a2 781 bus-width = <4>;
7d740f87
SG		 782 status = "disabled";
783 };
784
7b7d6727 785 usdhc4: usdhc@0219c000 {
7d740f87
SG		 786 compatible = "fsl,imx6q-usdhc";
787 reg = <0x0219c000 0x4000>;
275c08b5 788 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 789 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
790 clock-names = "ipg", "ahb", "per";
c104b6a2 791 bus-width = <4>;
7d740f87
SG		 792 status = "disabled";
793 };
794
7b7d6727 795 i2c1: i2c@021a0000 {
7d740f87
SG		 796 #address-cells = <1>;
797 #size-cells = <0>;
5bdfba29 798 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 799 reg = <0x021a0000 0x4000>;
275c08b5 800 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 801 clocks = <&clks 125>;
7d740f87
SG		 802 status = "disabled";
803 };
804
7b7d6727 805 i2c2: i2c@021a4000 {
7d740f87
SG		 806 #address-cells = <1>;
807 #size-cells = <0>;
5bdfba29 808 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 809 reg = <0x021a4000 0x4000>;
275c08b5 810 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 811 clocks = <&clks 126>;
7d740f87
SG		 812 status = "disabled";
813 };
814
7b7d6727 815 i2c3: i2c@021a8000 {
7d740f87
SG		 816 #address-cells = <1>;
817 #size-cells = <0>;
5bdfba29 818 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 819 reg = <0x021a8000 0x4000>;
275c08b5 820 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 821 clocks = <&clks 127>;
7d740f87
SG		 822 status = "disabled";
823 };
824
825 romcp@021ac000 {
826 reg = <0x021ac000 0x4000>;
827 };
828
7b7d6727 829 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 830 compatible = "fsl,imx6q-mmdc";
831 reg = <0x021b0000 0x4000>;
832 };
833
7b7d6727 834 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 835 reg = <0x021b4000 0x4000>;
836 };
837
05e3f8e7
HS		 838 weim: weim@021b8000 {
839 compatible = "fsl,imx6q-weim";
7d740f87 840 reg = <0x021b8000 0x4000>;
275c08b5 841 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
05e3f8e7 842 clocks = <&clks 196>;
7d740f87
SG		 843 };
844
3fe6373b
SG		 845 ocotp: ocotp@021bc000 {
846 compatible = "fsl,imx6q-ocotp", "syscon";
7d740f87
SG		 847 reg = <0x021bc000 0x4000>;
848 };
849
7d740f87
SG		 850 tzasc@021d0000 { /* TZASC1 */
851 reg = <0x021d0000 0x4000>;
275c08b5 852 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 853 };
854
855 tzasc@021d4000 { /* TZASC2 */
856 reg = <0x021d4000 0x4000>;
275c08b5 857 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 858 };
859
7b7d6727 860 audmux: audmux@021d8000 {
f965cd55 861 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 862 reg = <0x021d8000 0x4000>;
f965cd55 863 status = "disabled";
7d740f87
SG		 864 };
865
5e0c7cd4 866 mipi_csi: mipi@021dc000 {
7d740f87
SG		 867 reg = <0x021dc000 0x4000>;
868 };
869
870 mipi@021e0000 { /* MIPI-DSI */
871 reg = <0x021e0000 0x4000>;
872 };
873
874 vdoa@021e4000 {
875 reg = <0x021e4000 0x4000>;
275c08b5 876 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 877 };
878
0c456cfa 879 uart2: serial@021e8000 {
7d740f87
SG		 880 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
881 reg = <0x021e8000 0x4000>;
275c08b5 882 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 883 clocks = <&clks 160>, <&clks 161>;
884 clock-names = "ipg", "per";
72a5cebf
HS		 885 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
886 dma-names = "rx", "tx";
7d740f87
SG		 887 status = "disabled";
888 };
889
0c456cfa 890 uart3: serial@021ec000 {
7d740f87
SG		 891 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
892 reg = <0x021ec000 0x4000>;
275c08b5 893 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 894 clocks = <&clks 160>, <&clks 161>;
895 clock-names = "ipg", "per";
72a5cebf
HS		 896 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
897 dma-names = "rx", "tx";
7d740f87
SG		 898 status = "disabled";
899 };
900
0c456cfa 901 uart4: serial@021f0000 {
7d740f87
SG		 902 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
903 reg = <0x021f0000 0x4000>;
275c08b5 904 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 905 clocks = <&clks 160>, <&clks 161>;
906 clock-names = "ipg", "per";
72a5cebf
HS		 907 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
908 dma-names = "rx", "tx";
7d740f87
SG		 909 status = "disabled";
910 };
911
0c456cfa 912 uart5: serial@021f4000 {
7d740f87
SG		 913 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
914 reg = <0x021f4000 0x4000>;
275c08b5 915 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 916 clocks = <&clks 160>, <&clks 161>;
917 clock-names = "ipg", "per";
72a5cebf
HS		 918 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
919 dma-names = "rx", "tx";
7d740f87
SG		 920 status = "disabled";
921 };
922 };
91660d74
SH		 923
924 ipu1: ipu@02400000 {
925 #crtc-cells = <1>;
926 compatible = "fsl,imx6q-ipu";
927 reg = <0x02400000 0x400000>;
275c08b5
TK		 928 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
929 <0 5 IRQ_TYPE_LEVEL_HIGH>;
91660d74
SH		 930 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
931 clock-names = "bus", "di0", "di1";
09ebf366 932 resets = <&src 2>;
91660d74 933 };
7d740f87
SG		 934 };
935};
Linux kernel - Deliverables
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