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ARM: dts: imx6qdl: Add mmc aliases
[deliverable/linux.git] / arch / arm / boot / dts / imx6qdl.dtsi
CommitLineData
7d740f87
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
7d740f87
SG		 14
15/ {
16 aliases {
5f8fbc2c
LW		 17 can0 = &can1;
18 can1 = &can2;
5230f8fe
SG		 19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 gpio5 = &gpio6;
25 gpio6 = &gpio7;
80fa0584
SH		 26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
fb06d65c
SH		 29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 mmc2 = &usdhc3;
32 mmc3 = &usdhc4;
80fa0584
SH		 33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 serial4 = &uart5;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
8189c51f
PC		 42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
7d740f87
SG		 44 };
45
7d740f87
SG		 46 intc: interrupt-controller@00a01000 {
47 compatible = "arm,cortex-a9-gic";
48 #interrupt-cells = <3>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-controller;
52 reg = <0x00a01000 0x1000>,
53 <0x00a00100 0x100>;
54 };
55
56 clocks {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 ckil {
61 compatible = "fsl,imx-ckil", "fixed-clock";
62 clock-frequency = <32768>;
63 };
64
65 ckih1 {
66 compatible = "fsl,imx-ckih1", "fixed-clock";
67 clock-frequency = <0>;
68 };
69
70 osc {
71 compatible = "fsl,imx-osc", "fixed-clock";
72 clock-frequency = <24000000>;
73 };
74 };
75
76 soc {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
81 ranges;
82
f30fb03d 83 dma_apbh: dma-apbh@00110000 {
e5d0f9f5
HS		 84 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
85 reg = <0x00110000 0x2000>;
275c08b5
TK		 86 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>,
88 <0 13 IRQ_TYPE_LEVEL_HIGH>,
89 <0 13 IRQ_TYPE_LEVEL_HIGH>;
f30fb03d
SG		 90 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
91 #dma-cells = <1>;
92 dma-channels = <4>;
0e87e043 93 clocks = <&clks 106>;
e5d0f9f5
HS		 94 };
95
be4ccfce 96 gpmi: gpmi-nand@00112000 {
0e87e043
SG		 97 compatible = "fsl,imx6q-gpmi-nand";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
101 reg-names = "gpmi-nand", "bch";
275c08b5 102 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
c7aa12a6 103 interrupt-names = "bch";
0e87e043
SG		 104 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
105 <&clks 150>, <&clks 149>;
106 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
107 "gpmi_bch_apb", "per1_bch";
f30fb03d
SG		 108 dmas = <&dma_apbh 0>;
109 dma-names = "rx-tx";
0e87e043 110 status = "disabled";
cf922fa8
HS		 111 };
112
7d740f87 113 timer@00a00600 {
58458e03
MZ		 114 compatible = "arm,cortex-a9-twd-timer";
115 reg = <0x00a00600 0x20>;
116 interrupts = <1 13 0xf01>;
2bb4b70b 117 clocks = <&clks 15>;
7d740f87
SG		 118 };
119
120 L2: l2-cache@00a02000 {
121 compatible = "arm,pl310-cache";
122 reg = <0x00a02000 0x1000>;
275c08b5 123 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 124 cache-unified;
125 cache-level = <2>;
5a5ca56e
DB		 126 arm,tag-latency = <4 2 3>;
127 arm,data-latency = <4 2 3>;
7d740f87
SG		 128 };
129
3a57291f
SC		 130 pcie: pcie@0x01000000 {
131 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
132 reg = <0x01ffc000 0x4000>; /* DBI */
133 #address-cells = <3>;
134 #size-cells = <2>;
135 device_type = "pci";
136 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
137 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
138 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
139 num-lanes = <1>;
275c08b5 140 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
3a57291f
SC		 141 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
142 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
143 status = "disabled";
144 };
145
218abe6f
DB		 146 pmu {
147 compatible = "arm,cortex-a9-pmu";
275c08b5 148 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
218abe6f
DB		 149 };
150
7d740f87
SG		 151 aips-bus@02000000 { /* AIPS1 */
152 compatible = "fsl,aips-bus", "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 reg = <0x02000000 0x100000>;
156 ranges;
157
158 spba-bus@02000000 {
159 compatible = "fsl,spba-bus", "simple-bus";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 reg = <0x02000000 0x40000>;
163 ranges;
164
7b7d6727 165 spdif: spdif@02004000 {
c9d96df2 166 compatible = "fsl,imx35-spdif";
7d740f87 167 reg = <0x02004000 0x4000>;
275c08b5 168 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
c9d96df2
FE		 169 dmas = <&sdma 14 18 0>,
170 <&sdma 15 18 0>;
171 dma-names = "rx", "tx";
172 clocks = <&clks 197>, <&clks 3>,
173 <&clks 197>, <&clks 107>,
174 <&clks 0>, <&clks 118>,
793b4b10 175 <&clks 0>, <&clks 139>,
c9d96df2
FE		 176 <&clks 0>;
177 clock-names = "core", "rxtx0",
178 "rxtx1", "rxtx2",
179 "rxtx3", "rxtx4",
180 "rxtx5", "rxtx6",
181 "rxtx7";
182 status = "disabled";
7d740f87
SG		 183 };
184
7b7d6727 185 ecspi1: ecspi@02008000 {
7d740f87
SG		 186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02008000 0x4000>;
275c08b5 190 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 191 clocks = <&clks 112>, <&clks 112>;
192 clock-names = "ipg", "per";
b3810c3d
FL		 193 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
194 dma-names = "rx", "tx";
7d740f87
SG		 195 status = "disabled";
196 };
197
7b7d6727 198 ecspi2: ecspi@0200c000 {
7d740f87
SG		 199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
202 reg = <0x0200c000 0x4000>;
275c08b5 203 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 204 clocks = <&clks 113>, <&clks 113>;
205 clock-names = "ipg", "per";
b3810c3d
FL		 206 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
207 dma-names = "rx", "tx";
7d740f87
SG		 208 status = "disabled";
209 };
210
7b7d6727 211 ecspi3: ecspi@02010000 {
7d740f87
SG		 212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
215 reg = <0x02010000 0x4000>;
275c08b5 216 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 217 clocks = <&clks 114>, <&clks 114>;
218 clock-names = "ipg", "per";
b3810c3d
FL		 219 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
220 dma-names = "rx", "tx";
7d740f87
SG		 221 status = "disabled";
222 };
223
7b7d6727 224 ecspi4: ecspi@02014000 {
7d740f87
SG		 225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
228 reg = <0x02014000 0x4000>;
275c08b5 229 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 230 clocks = <&clks 115>, <&clks 115>;
231 clock-names = "ipg", "per";
b3810c3d
FL		 232 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
233 dma-names = "rx", "tx";
7d740f87
SG		 234 status = "disabled";
235 };
236
0c456cfa 237 uart1: serial@02020000 {
7d740f87
SG		 238 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
239 reg = <0x02020000 0x4000>;
275c08b5 240 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 241 clocks = <&clks 160>, <&clks 161>;
242 clock-names = "ipg", "per";
72a5cebf
HS		 243 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
244 dma-names = "rx", "tx";
7d740f87
SG		 245 status = "disabled";
246 };
247
7b7d6727 248 esai: esai@02024000 {
7d740f87 249 reg = <0x02024000 0x4000>;
275c08b5 250 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 251 };
252
b1a5da8e
RZ		 253 ssi1: ssi@02028000 {
254 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87 255 reg = <0x02028000 0x4000>;
275c08b5 256 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 257 clocks = <&clks 178>;
5da826ab
SG		 258 dmas = <&sdma 37 1 0>,
259 <&sdma 38 1 0>;
260 dma-names = "rx", "tx";
b1a5da8e
RZ		 261 fsl,fifo-depth = <15>;
262 fsl,ssi-dma-events = <38 37>;
263 status = "disabled";
7d740f87
SG		 264 };
265
b1a5da8e
RZ		 266 ssi2: ssi@0202c000 {
267 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87 268 reg = <0x0202c000 0x4000>;
275c08b5 269 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 270 clocks = <&clks 179>;
5da826ab
SG		 271 dmas = <&sdma 41 1 0>,
272 <&sdma 42 1 0>;
273 dma-names = "rx", "tx";
b1a5da8e
RZ		 274 fsl,fifo-depth = <15>;
275 fsl,ssi-dma-events = <42 41>;
276 status = "disabled";
7d740f87
SG		 277 };
278
b1a5da8e
RZ		 279 ssi3: ssi@02030000 {
280 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
7d740f87 281 reg = <0x02030000 0x4000>;
275c08b5 282 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 283 clocks = <&clks 180>;
5da826ab
SG		 284 dmas = <&sdma 45 1 0>,
285 <&sdma 46 1 0>;
286 dma-names = "rx", "tx";
b1a5da8e
RZ		 287 fsl,fifo-depth = <15>;
288 fsl,ssi-dma-events = <46 45>;
289 status = "disabled";
7d740f87
SG		 290 };
291
7b7d6727 292 asrc: asrc@02034000 {
7d740f87 293 reg = <0x02034000 0x4000>;
275c08b5 294 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 295 };
296
297 spba@0203c000 {
298 reg = <0x0203c000 0x4000>;
299 };
300 };
301
7b7d6727 302 vpu: vpu@02040000 {
7d740f87 303 reg = <0x02040000 0x3c000>;
275c08b5
TK		 304 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
305 <0 12 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 306 };
307
308 aipstz@0207c000 { /* AIPSTZ1 */
309 reg = <0x0207c000 0x4000>;
310 };
311
7b7d6727 312 pwm1: pwm@02080000 {
33b38587
SH		 313 #pwm-cells = <2>;
314 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 315 reg = <0x02080000 0x4000>;
275c08b5 316 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 317 clocks = <&clks 62>, <&clks 145>;
318 clock-names = "ipg", "per";
7d740f87
SG		 319 };
320
7b7d6727 321 pwm2: pwm@02084000 {
33b38587
SH		 322 #pwm-cells = <2>;
323 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 324 reg = <0x02084000 0x4000>;
275c08b5 325 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 326 clocks = <&clks 62>, <&clks 146>;
327 clock-names = "ipg", "per";
7d740f87
SG		 328 };
329
7b7d6727 330 pwm3: pwm@02088000 {
33b38587
SH		 331 #pwm-cells = <2>;
332 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 333 reg = <0x02088000 0x4000>;
275c08b5 334 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 335 clocks = <&clks 62>, <&clks 147>;
336 clock-names = "ipg", "per";
7d740f87
SG		 337 };
338
7b7d6727 339 pwm4: pwm@0208c000 {
33b38587
SH		 340 #pwm-cells = <2>;
341 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
7d740f87 342 reg = <0x0208c000 0x4000>;
275c08b5 343 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
33b38587
SH		 344 clocks = <&clks 62>, <&clks 148>;
345 clock-names = "ipg", "per";
7d740f87
SG		 346 };
347
7b7d6727 348 can1: flexcan@02090000 {
0f225212 349 compatible = "fsl,imx6q-flexcan";
7d740f87 350 reg = <0x02090000 0x4000>;
275c08b5 351 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
0f225212
SH		 352 clocks = <&clks 108>, <&clks 109>;
353 clock-names = "ipg", "per";
a1135337 354 status = "disabled";
7d740f87
SG		 355 };
356
7b7d6727 357 can2: flexcan@02094000 {
0f225212 358 compatible = "fsl,imx6q-flexcan";
7d740f87 359 reg = <0x02094000 0x4000>;
275c08b5 360 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
0f225212
SH		 361 clocks = <&clks 110>, <&clks 111>;
362 clock-names = "ipg", "per";
a1135337 363 status = "disabled";
7d740f87
SG		 364 };
365
7b7d6727 366 gpt: gpt@02098000 {
97b108f9 367 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
7d740f87 368 reg = <0x02098000 0x4000>;
275c08b5 369 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
4efccadd
SH		 370 clocks = <&clks 119>, <&clks 120>;
371 clock-names = "ipg", "per";
7d740f87
SG		 372 };
373
4d191868 374 gpio1: gpio@0209c000 {
aeb27748 375 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 376 reg = <0x0209c000 0x4000>;
275c08b5
TK		 377 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
378 <0 67 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
88cde8b7 382 #interrupt-cells = <2>;
7d740f87
SG		 383 };
384
4d191868 385 gpio2: gpio@020a0000 {
aeb27748 386 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 387 reg = <0x020a0000 0x4000>;
275c08b5
TK		 388 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
389 <0 69 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
88cde8b7 393 #interrupt-cells = <2>;
7d740f87
SG		 394 };
395
4d191868 396 gpio3: gpio@020a4000 {
aeb27748 397 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 398 reg = <0x020a4000 0x4000>;
275c08b5
TK		 399 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
400 <0 71 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
88cde8b7 404 #interrupt-cells = <2>;
7d740f87
SG		 405 };
406
4d191868 407 gpio4: gpio@020a8000 {
aeb27748 408 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 409 reg = <0x020a8000 0x4000>;
275c08b5
TK		 410 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
411 <0 73 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 412 gpio-controller;
413 #gpio-cells = <2>;
414 interrupt-controller;
88cde8b7 415 #interrupt-cells = <2>;
7d740f87
SG		 416 };
417
4d191868 418 gpio5: gpio@020ac000 {
aeb27748 419 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 420 reg = <0x020ac000 0x4000>;
275c08b5
TK		 421 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
422 <0 75 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 423 gpio-controller;
424 #gpio-cells = <2>;
425 interrupt-controller;
88cde8b7 426 #interrupt-cells = <2>;
7d740f87
SG		 427 };
428
4d191868 429 gpio6: gpio@020b0000 {
aeb27748 430 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 431 reg = <0x020b0000 0x4000>;
275c08b5
TK		 432 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
433 <0 77 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 434 gpio-controller;
435 #gpio-cells = <2>;
436 interrupt-controller;
88cde8b7 437 #interrupt-cells = <2>;
7d740f87
SG		 438 };
439
4d191868 440 gpio7: gpio@020b4000 {
aeb27748 441 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
7d740f87 442 reg = <0x020b4000 0x4000>;
275c08b5
TK		 443 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
444 <0 79 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
88cde8b7 448 #interrupt-cells = <2>;
7d740f87
SG		 449 };
450
7b7d6727 451 kpp: kpp@020b8000 {
7d740f87 452 reg = <0x020b8000 0x4000>;
275c08b5 453 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 454 };
455
7b7d6727 456 wdog1: wdog@020bc000 {
7d740f87
SG		 457 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
458 reg = <0x020bc000 0x4000>;
275c08b5 459 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 460 clocks = <&clks 0>;
7d740f87
SG		 461 };
462
7b7d6727 463 wdog2: wdog@020c0000 {
7d740f87
SG		 464 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
465 reg = <0x020c0000 0x4000>;
275c08b5 466 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 467 clocks = <&clks 0>;
7d740f87
SG		 468 status = "disabled";
469 };
470
0e87e043 471 clks: ccm@020c4000 {
7d740f87
SG		 472 compatible = "fsl,imx6q-ccm";
473 reg = <0x020c4000 0x4000>;
275c08b5
TK		 474 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
475 <0 88 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 476 #clock-cells = <1>;
7d740f87
SG		 477 };
478
baa64151
DA		 479 anatop: anatop@020c8000 {
480 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
7d740f87 481 reg = <0x020c8000 0x1000>;
275c08b5
TK		 482 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
483 <0 54 IRQ_TYPE_LEVEL_HIGH>,
484 <0 127 IRQ_TYPE_LEVEL_HIGH>;
a1e327e6
YCLP		 485
486 regulator-1p1@110 {
487 compatible = "fsl,anatop-regulator";
488 regulator-name = "vdd1p1";
489 regulator-min-microvolt = <800000>;
490 regulator-max-microvolt = <1375000>;
491 regulator-always-on;
492 anatop-reg-offset = <0x110>;
493 anatop-vol-bit-shift = <8>;
494 anatop-vol-bit-width = <5>;
495 anatop-min-bit-val = <4>;
496 anatop-min-voltage = <800000>;
497 anatop-max-voltage = <1375000>;
498 };
499
500 regulator-3p0@120 {
501 compatible = "fsl,anatop-regulator";
502 regulator-name = "vdd3p0";
503 regulator-min-microvolt = <2800000>;
504 regulator-max-microvolt = <3150000>;
505 regulator-always-on;
506 anatop-reg-offset = <0x120>;
507 anatop-vol-bit-shift = <8>;
508 anatop-vol-bit-width = <5>;
509 anatop-min-bit-val = <0>;
510 anatop-min-voltage = <2625000>;
511 anatop-max-voltage = <3400000>;
512 };
513
514 regulator-2p5@130 {
515 compatible = "fsl,anatop-regulator";
516 regulator-name = "vdd2p5";
517 regulator-min-microvolt = <2000000>;
518 regulator-max-microvolt = <2750000>;
519 regulator-always-on;
520 anatop-reg-offset = <0x130>;
521 anatop-vol-bit-shift = <8>;
522 anatop-vol-bit-width = <5>;
523 anatop-min-bit-val = <0>;
524 anatop-min-voltage = <2000000>;
525 anatop-max-voltage = <2750000>;
526 };
527
96574a6d 528 reg_arm: regulator-vddcore@140 {
a1e327e6 529 compatible = "fsl,anatop-regulator";
118c98a6 530 regulator-name = "vddarm";
a1e327e6
YCLP		 531 regulator-min-microvolt = <725000>;
532 regulator-max-microvolt = <1450000>;
533 regulator-always-on;
534 anatop-reg-offset = <0x140>;
535 anatop-vol-bit-shift = <0>;
536 anatop-vol-bit-width = <5>;
46743dd6
AH		 537 anatop-delay-reg-offset = <0x170>;
538 anatop-delay-bit-shift = <24>;
539 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 540 anatop-min-bit-val = <1>;
541 anatop-min-voltage = <725000>;
542 anatop-max-voltage = <1450000>;
543 };
544
96574a6d 545 reg_pu: regulator-vddpu@140 {
a1e327e6
YCLP		 546 compatible = "fsl,anatop-regulator";
547 regulator-name = "vddpu";
548 regulator-min-microvolt = <725000>;
549 regulator-max-microvolt = <1450000>;
550 regulator-always-on;
551 anatop-reg-offset = <0x140>;
552 anatop-vol-bit-shift = <9>;
553 anatop-vol-bit-width = <5>;
46743dd6
AH		 554 anatop-delay-reg-offset = <0x170>;
555 anatop-delay-bit-shift = <26>;
556 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 557 anatop-min-bit-val = <1>;
558 anatop-min-voltage = <725000>;
559 anatop-max-voltage = <1450000>;
560 };
561
96574a6d 562 reg_soc: regulator-vddsoc@140 {
a1e327e6
YCLP		 563 compatible = "fsl,anatop-regulator";
564 regulator-name = "vddsoc";
565 regulator-min-microvolt = <725000>;
566 regulator-max-microvolt = <1450000>;
567 regulator-always-on;
568 anatop-reg-offset = <0x140>;
569 anatop-vol-bit-shift = <18>;
570 anatop-vol-bit-width = <5>;
46743dd6
AH		 571 anatop-delay-reg-offset = <0x170>;
572 anatop-delay-bit-shift = <28>;
573 anatop-delay-bit-width = <2>;
a1e327e6
YCLP		 574 anatop-min-bit-val = <1>;
575 anatop-min-voltage = <725000>;
576 anatop-max-voltage = <1450000>;
577 };
7d740f87
SG		 578 };
579
3fe6373b
SG		 580 tempmon: tempmon {
581 compatible = "fsl,imx6q-tempmon";
275c08b5 582 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
3fe6373b
SG		 583 fsl,tempmon = <&anatop>;
584 fsl,tempmon-data = <&ocotp>;
f430d19c 585 clocks = <&clks 172>;
3fe6373b
SG		 586 };
587
74bd88f7
RZ		 588 usbphy1: usbphy@020c9000 {
589 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87 590 reg = <0x020c9000 0x1000>;
275c08b5 591 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 592 clocks = <&clks 182>;
76a38855 593 fsl,anatop = <&anatop>;
7d740f87
SG		 594 };
595
74bd88f7
RZ		 596 usbphy2: usbphy@020ca000 {
597 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
7d740f87 598 reg = <0x020ca000 0x1000>;
275c08b5 599 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 600 clocks = <&clks 183>;
76a38855 601 fsl,anatop = <&anatop>;
7d740f87
SG		 602 };
603
604 snvs@020cc000 {
c9250388
SG		 605 compatible = "fsl,sec-v4.0-mon", "simple-bus";
606 #address-cells = <1>;
607 #size-cells = <1>;
608 ranges = <0 0x020cc000 0x4000>;
609
610 snvs-rtc-lp@34 {
611 compatible = "fsl,sec-v4.0-mon-rtc-lp";
612 reg = <0x34 0x58>;
275c08b5
TK		 613 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
614 <0 20 IRQ_TYPE_LEVEL_HIGH>;
c9250388 615 };
7d740f87
SG		 616 };
617
7b7d6727 618 epit1: epit@020d0000 { /* EPIT1 */
7d740f87 619 reg = <0x020d0000 0x4000>;
275c08b5 620 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 621 };
622
7b7d6727 623 epit2: epit@020d4000 { /* EPIT2 */
7d740f87 624 reg = <0x020d4000 0x4000>;
275c08b5 625 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 626 };
627
7b7d6727 628 src: src@020d8000 {
bd3d924d 629 compatible = "fsl,imx6q-src", "fsl,imx51-src";
7d740f87 630 reg = <0x020d8000 0x4000>;
275c08b5
TK		 631 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
632 <0 96 IRQ_TYPE_LEVEL_HIGH>;
09ebf366 633 #reset-cells = <1>;
7d740f87
SG		 634 };
635
7b7d6727 636 gpc: gpc@020dc000 {
7d740f87
SG		 637 compatible = "fsl,imx6q-gpc";
638 reg = <0x020dc000 0x4000>;
275c08b5
TK		 639 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
640 <0 90 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 641 };
642
df37e0c0
DA		 643 gpr: iomuxc-gpr@020e0000 {
644 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
645 reg = <0x020e0000 0x38>;
646 };
647
c56009b2
SG		 648 iomuxc: iomuxc@020e0000 {
649 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
650 reg = <0x020e0000 0x4000>;
c56009b2
SG		 651 };
652
41c04342
ST		 653 ldb: ldb@020e0008 {
654 #address-cells = <1>;
655 #size-cells = <0>;
656 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
657 gpr = <&gpr>;
658 status = "disabled";
659
660 lvds-channel@0 {
661 reg = <0>;
41c04342
ST		 662 status = "disabled";
663 };
664
665 lvds-channel@1 {
666 reg = <1>;
41c04342
ST		 667 status = "disabled";
668 };
669 };
670
7b7d6727 671 dcic1: dcic@020e4000 {
7d740f87 672 reg = <0x020e4000 0x4000>;
275c08b5 673 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 674 };
675
7b7d6727 676 dcic2: dcic@020e8000 {
7d740f87 677 reg = <0x020e8000 0x4000>;
275c08b5 678 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 679 };
680
7b7d6727 681 sdma: sdma@020ec000 {
7d740f87
SG		 682 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
683 reg = <0x020ec000 0x4000>;
275c08b5 684 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 685 clocks = <&clks 155>, <&clks 155>;
686 clock-names = "ipg", "ahb";
fb72bb21 687 #dma-cells = <3>;
d6b9c591 688 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
7d740f87
SG		 689 };
690 };
691
692 aips-bus@02100000 { /* AIPS2 */
693 compatible = "fsl,aips-bus", "simple-bus";
694 #address-cells = <1>;
695 #size-cells = <1>;
696 reg = <0x02100000 0x100000>;
697 ranges;
698
699 caam@02100000 {
700 reg = <0x02100000 0x40000>;
275c08b5
TK		 701 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
702 <0 106 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 703 };
704
705 aipstz@0217c000 { /* AIPSTZ2 */
706 reg = <0x0217c000 0x4000>;
707 };
708
7b7d6727 709 usbotg: usb@02184000 {
74bd88f7
RZ		 710 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
711 reg = <0x02184000 0x200>;
275c08b5 712 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 713 clocks = <&clks 162>;
74bd88f7 714 fsl,usbphy = <&usbphy1>;
28342c61 715 fsl,usbmisc = <&usbmisc 0>;
74bd88f7
RZ		 716 status = "disabled";
717 };
718
7b7d6727 719 usbh1: usb@02184200 {
74bd88f7
RZ		 720 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
721 reg = <0x02184200 0x200>;
275c08b5 722 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 723 clocks = <&clks 162>;
74bd88f7 724 fsl,usbphy = <&usbphy2>;
28342c61 725 fsl,usbmisc = <&usbmisc 1>;
74bd88f7
RZ		 726 status = "disabled";
727 };
728
7b7d6727 729 usbh2: usb@02184400 {
74bd88f7
RZ		 730 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
731 reg = <0x02184400 0x200>;
275c08b5 732 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 733 clocks = <&clks 162>;
28342c61 734 fsl,usbmisc = <&usbmisc 2>;
74bd88f7
RZ		 735 status = "disabled";
736 };
737
7b7d6727 738 usbh3: usb@02184600 {
74bd88f7
RZ		 739 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
740 reg = <0x02184600 0x200>;
275c08b5 741 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 742 clocks = <&clks 162>;
28342c61 743 fsl,usbmisc = <&usbmisc 3>;
74bd88f7
RZ		 744 status = "disabled";
745 };
746
60984bdf 747 usbmisc: usbmisc@02184800 {
28342c61
RZ		 748 #index-cells = <1>;
749 compatible = "fsl,imx6q-usbmisc";
750 reg = <0x02184800 0x200>;
751 clocks = <&clks 162>;
752 };
753
7b7d6727 754 fec: ethernet@02188000 {
7d740f87
SG		 755 compatible = "fsl,imx6q-fec";
756 reg = <0x02188000 0x4000>;
454cf8f5
TK		 757 interrupts-extended =
758 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
759 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
8dd5c66b 760 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
7629838c 761 clock-names = "ipg", "ahb", "ptp";
7d740f87
SG		 762 status = "disabled";
763 };
764
765 mlb@0218c000 {
766 reg = <0x0218c000 0x4000>;
275c08b5
TK		 767 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
768 <0 117 IRQ_TYPE_LEVEL_HIGH>,
769 <0 126 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 770 };
771
7b7d6727 772 usdhc1: usdhc@02190000 {
7d740f87
SG		 773 compatible = "fsl,imx6q-usdhc";
774 reg = <0x02190000 0x4000>;
275c08b5 775 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 776 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
777 clock-names = "ipg", "ahb", "per";
c104b6a2 778 bus-width = <4>;
7d740f87
SG		 779 status = "disabled";
780 };
781
7b7d6727 782 usdhc2: usdhc@02194000 {
7d740f87
SG		 783 compatible = "fsl,imx6q-usdhc";
784 reg = <0x02194000 0x4000>;
275c08b5 785 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 786 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
787 clock-names = "ipg", "ahb", "per";
c104b6a2 788 bus-width = <4>;
7d740f87
SG		 789 status = "disabled";
790 };
791
7b7d6727 792 usdhc3: usdhc@02198000 {
7d740f87
SG		 793 compatible = "fsl,imx6q-usdhc";
794 reg = <0x02198000 0x4000>;
275c08b5 795 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 796 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
797 clock-names = "ipg", "ahb", "per";
c104b6a2 798 bus-width = <4>;
7d740f87
SG		 799 status = "disabled";
800 };
801
7b7d6727 802 usdhc4: usdhc@0219c000 {
7d740f87
SG		 803 compatible = "fsl,imx6q-usdhc";
804 reg = <0x0219c000 0x4000>;
275c08b5 805 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 806 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
807 clock-names = "ipg", "ahb", "per";
c104b6a2 808 bus-width = <4>;
7d740f87
SG		 809 status = "disabled";
810 };
811
7b7d6727 812 i2c1: i2c@021a0000 {
7d740f87
SG		 813 #address-cells = <1>;
814 #size-cells = <0>;
5bdfba29 815 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 816 reg = <0x021a0000 0x4000>;
275c08b5 817 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 818 clocks = <&clks 125>;
7d740f87
SG		 819 status = "disabled";
820 };
821
7b7d6727 822 i2c2: i2c@021a4000 {
7d740f87
SG		 823 #address-cells = <1>;
824 #size-cells = <0>;
5bdfba29 825 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 826 reg = <0x021a4000 0x4000>;
275c08b5 827 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 828 clocks = <&clks 126>;
7d740f87
SG		 829 status = "disabled";
830 };
831
7b7d6727 832 i2c3: i2c@021a8000 {
7d740f87
SG		 833 #address-cells = <1>;
834 #size-cells = <0>;
5bdfba29 835 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
7d740f87 836 reg = <0x021a8000 0x4000>;
275c08b5 837 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
0e87e043 838 clocks = <&clks 127>;
7d740f87
SG		 839 status = "disabled";
840 };
841
842 romcp@021ac000 {
843 reg = <0x021ac000 0x4000>;
844 };
845
7b7d6727 846 mmdc0: mmdc@021b0000 { /* MMDC0 */
7d740f87
SG		 847 compatible = "fsl,imx6q-mmdc";
848 reg = <0x021b0000 0x4000>;
849 };
850
7b7d6727 851 mmdc1: mmdc@021b4000 { /* MMDC1 */
7d740f87
SG		 852 reg = <0x021b4000 0x4000>;
853 };
854
05e3f8e7
HS		 855 weim: weim@021b8000 {
856 compatible = "fsl,imx6q-weim";
7d740f87 857 reg = <0x021b8000 0x4000>;
275c08b5 858 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
05e3f8e7 859 clocks = <&clks 196>;
7d740f87
SG		 860 };
861
3fe6373b
SG		 862 ocotp: ocotp@021bc000 {
863 compatible = "fsl,imx6q-ocotp", "syscon";
7d740f87
SG		 864 reg = <0x021bc000 0x4000>;
865 };
866
7d740f87
SG		 867 tzasc@021d0000 { /* TZASC1 */
868 reg = <0x021d0000 0x4000>;
275c08b5 869 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 870 };
871
872 tzasc@021d4000 { /* TZASC2 */
873 reg = <0x021d4000 0x4000>;
275c08b5 874 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 875 };
876
7b7d6727 877 audmux: audmux@021d8000 {
f965cd55 878 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
7d740f87 879 reg = <0x021d8000 0x4000>;
f965cd55 880 status = "disabled";
7d740f87
SG		 881 };
882
5e0c7cd4 883 mipi_csi: mipi@021dc000 {
7d740f87
SG		 884 reg = <0x021dc000 0x4000>;
885 };
886
887 mipi@021e0000 { /* MIPI-DSI */
888 reg = <0x021e0000 0x4000>;
889 };
890
891 vdoa@021e4000 {
892 reg = <0x021e4000 0x4000>;
275c08b5 893 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
7d740f87
SG		 894 };
895
0c456cfa 896 uart2: serial@021e8000 {
7d740f87
SG		 897 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
898 reg = <0x021e8000 0x4000>;
275c08b5 899 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 900 clocks = <&clks 160>, <&clks 161>;
901 clock-names = "ipg", "per";
72a5cebf
HS		 902 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
903 dma-names = "rx", "tx";
7d740f87
SG		 904 status = "disabled";
905 };
906
0c456cfa 907 uart3: serial@021ec000 {
7d740f87
SG		 908 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
909 reg = <0x021ec000 0x4000>;
275c08b5 910 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 911 clocks = <&clks 160>, <&clks 161>;
912 clock-names = "ipg", "per";
72a5cebf
HS		 913 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
914 dma-names = "rx", "tx";
7d740f87
SG		 915 status = "disabled";
916 };
917
0c456cfa 918 uart4: serial@021f0000 {
7d740f87
SG		 919 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
920 reg = <0x021f0000 0x4000>;
275c08b5 921 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 922 clocks = <&clks 160>, <&clks 161>;
923 clock-names = "ipg", "per";
72a5cebf
HS		 924 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
925 dma-names = "rx", "tx";
7d740f87
SG		 926 status = "disabled";
927 };
928
0c456cfa 929 uart5: serial@021f4000 {
7d740f87
SG		 930 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
931 reg = <0x021f4000 0x4000>;
275c08b5 932 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
0e87e043
SG		 933 clocks = <&clks 160>, <&clks 161>;
934 clock-names = "ipg", "per";
72a5cebf
HS		 935 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
936 dma-names = "rx", "tx";
7d740f87
SG		 937 status = "disabled";
938 };
939 };
91660d74
SH		 940
941 ipu1: ipu@02400000 {
942 #crtc-cells = <1>;
943 compatible = "fsl,imx6q-ipu";
944 reg = <0x02400000 0x400000>;
275c08b5
TK		 945 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
946 <0 5 IRQ_TYPE_LEVEL_HIGH>;
91660d74
SH		 947 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
948 clock-names = "bus", "di0", "di1";
09ebf366 949 resets = <&src 2>;
91660d74 950 };
7d740f87
SG		 951 };
952};
Linux kernel - Deliverables
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