Commit | Line | Data |
---|---|---|
27b0b9d8 OS |
1 | /* |
2 | * Copyright 2014, 2015 O.S. Systems Software LTDA. | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public | |
20 | * License along with this file; if not, write to the Free | |
21 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
22 | * MA 02110-1301 USA | |
23 | * | |
24 | * Or, alternatively, | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use, | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
46 | */ | |
47 | ||
48 | /dts-v1/; | |
49 | ||
159097f8 | 50 | #include <dt-bindings/gpio/gpio.h> |
27b0b9d8 OS |
51 | #include "imx6sl.dtsi" |
52 | ||
53 | / { | |
54 | model = "WaRP Board"; | |
55 | compatible = "warp,imx6sl-warp", "fsl,imx6sl"; | |
56 | ||
57 | memory { | |
58 | reg = <0x80000000 0x20000000>; | |
59 | }; | |
60 | ||
159097f8 FE |
61 | usdhc3_pwrseq: usdhc3_pwrseq { |
62 | compatible = "mmc-pwrseq-simple"; | |
63 | reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ | |
d23dfefa | 64 | <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ |
159097f8 | 65 | <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ |
d23dfefa | 66 | <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ |
159097f8 FE |
67 | <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ |
68 | <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ | |
69 | }; | |
27b0b9d8 OS |
70 | }; |
71 | ||
72 | &uart1 { | |
73 | pinctrl-names = "default"; | |
74 | pinctrl-0 = <&pinctrl_uart1>; | |
75 | status = "okay"; | |
76 | }; | |
77 | ||
d23dfefa | 78 | &uart3 { |
159097f8 | 79 | pinctrl-names = "default"; |
d23dfefa | 80 | pinctrl-0 = <&pinctrl_uart3>; |
159097f8 FE |
81 | status = "okay"; |
82 | }; | |
83 | ||
d23dfefa | 84 | &uart5 { |
27b0b9d8 | 85 | pinctrl-names = "default"; |
d23dfefa FE |
86 | pinctrl-0 = <&pinctrl_uart5>; |
87 | fsl,uart-has-rtscts; | |
27b0b9d8 OS |
88 | status = "okay"; |
89 | }; | |
90 | ||
91 | &usbotg1 { | |
0c1e1896 | 92 | dr_mode = "peripheral"; |
27b0b9d8 OS |
93 | disable-over-current; |
94 | status = "okay"; | |
95 | }; | |
96 | ||
97 | &usbotg2 { | |
0c1e1896 | 98 | dr_mode = "host"; |
27b0b9d8 OS |
99 | disable-over-current; |
100 | status = "okay"; | |
101 | }; | |
102 | ||
103 | &usdhc2 { | |
104 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
105 | pinctrl-0 = <&pinctrl_usdhc2>; | |
106 | pinctrl-1 = <&pinctrl_usdhc2_100mhz>; | |
107 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>; | |
649b1fe8 | 108 | bus-width = <8>; |
27b0b9d8 OS |
109 | non-removable; |
110 | status = "okay"; | |
111 | }; | |
112 | ||
159097f8 FE |
113 | &usdhc3 { |
114 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
115 | pinctrl-0 = <&pinctrl_usdhc3>; | |
116 | pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | |
117 | pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
118 | bus-width = <4>; | |
119 | non-removable; | |
120 | keep-power-in-suspend; | |
26cefdd1 | 121 | wakeup-source; |
159097f8 FE |
122 | mmc-pwrseq = <&usdhc3_pwrseq>; |
123 | status = "okay"; | |
124 | }; | |
125 | ||
27b0b9d8 OS |
126 | &iomuxc { |
127 | imx6sl-warp { | |
128 | pinctrl_uart1: uart1grp { | |
129 | fsl,pins = < | |
130 | MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 | |
131 | MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 | |
132 | >; | |
133 | }; | |
134 | ||
159097f8 | 135 | |
27b0b9d8 OS |
136 | pinctrl_uart3: uart3grp { |
137 | fsl,pins = < | |
138 | MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 | |
139 | MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 | |
140 | >; | |
141 | }; | |
142 | ||
d23dfefa FE |
143 | pinctrl_uart5: uart5grp { |
144 | fsl,pins = < | |
145 | MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 | |
146 | MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 | |
147 | MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 | |
148 | MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 | |
149 | >; | |
150 | }; | |
151 | ||
27b0b9d8 OS |
152 | pinctrl_usdhc2: usdhc2grp { |
153 | fsl,pins = < | |
154 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 | |
155 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 | |
156 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 | |
157 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 | |
158 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 | |
159 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 | |
160 | MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 | |
161 | MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 | |
162 | MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 | |
163 | MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 | |
6e2a92b2 | 164 | MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 |
27b0b9d8 OS |
165 | >; |
166 | }; | |
167 | ||
168 | pinctrl_usdhc2_100mhz: usdhc2grp100mhz { | |
169 | fsl,pins = < | |
170 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 | |
171 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 | |
172 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 | |
173 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 | |
174 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 | |
175 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 | |
176 | MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 | |
177 | MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 | |
178 | MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 | |
179 | MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 | |
6e2a92b2 | 180 | MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 |
27b0b9d8 OS |
181 | >; |
182 | }; | |
183 | ||
184 | pinctrl_usdhc2_200mhz: usdhc2grp200mhz { | |
185 | fsl,pins = < | |
186 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 | |
187 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 | |
188 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 | |
189 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 | |
190 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 | |
191 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 | |
192 | MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 | |
193 | MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 | |
194 | MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 | |
195 | MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 | |
6e2a92b2 | 196 | MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 |
27b0b9d8 OS |
197 | >; |
198 | }; | |
159097f8 FE |
199 | |
200 | pinctrl_usdhc3: usdhc3grp { | |
201 | fsl,pins = < | |
202 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 | |
203 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 | |
204 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 | |
205 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 | |
206 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 | |
207 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 | |
208 | >; | |
209 | }; | |
210 | ||
211 | pinctrl_usdhc3_100mhz: usdhc3grp100mhz { | |
212 | fsl,pins = < | |
213 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 | |
214 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 | |
215 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 | |
216 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 | |
217 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 | |
218 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 | |
219 | >; | |
220 | }; | |
221 | ||
222 | pinctrl_usdhc3_200mhz: usdhc3grp200mhz { | |
223 | fsl,pins = < | |
224 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 | |
225 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 | |
226 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 | |
227 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 | |
228 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 | |
229 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 | |
230 | >; | |
231 | }; | |
27b0b9d8 OS |
232 | }; |
233 | }; |