[deliverable/linux.git] / arch / arm / boot / dts / imx6sl-warp.dts

/*
 * Copyright 2014, 2015 O.S. Systems Software LTDA.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"

/ {
	model = "WaRP Board";
	compatible = "warp,imx6sl-warp", "fsl,imx6sl";

	memory {
		reg = <0x80000000 0x20000000>;
	};

	usdhc3_pwrseq: usdhc3_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, 	/* WL_REG_ON */
			      <&gpio3 25 GPIO_ACTIVE_LOW>, 	/* BT_REG_ON */
			      <&gpio4 4 GPIO_ACTIVE_LOW>, 	/* BT_WAKE */
			      <&gpio4 6 GPIO_ACTIVE_LOW>; 	/* BT_RST_N */
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <4>;
	non-removable;
	keep-power-in-suspend;
	enable-sdio-wakeup;
	mmc-pwrseq = <&usdhc3_pwrseq>;
	status = "okay";
};

&iomuxc {
	imx6sl-warp {
		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x41b0b1
				MX6SL_PAD_UART1_TXD__UART1_TX_DATA	0x41b0b1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6SL_PAD_EPDC_D12__UART2_RX_DATA	0x41b0b1
				MX6SL_PAD_EPDC_D13__UART2_TX_DATA	0x41b0b1
				MX6SL_PAD_EPDC_D14__UART2_RTS_B		0x4130B1
				MX6SL_PAD_EPDC_D15__UART2_CTS_B		0x4130B1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6SL_PAD_AUD_RXC__UART3_RX_DATA	0x41b0b1
				MX6SL_PAD_AUD_RXC__UART3_TX_DATA	0x41b0b1
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6SL_PAD_SD2_CMD__SD2_CMD		0x417059
				MX6SL_PAD_SD2_CLK__SD2_CLK		0x410059
				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x417059
				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x417059
				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x417059
				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x417059
				MX6SL_PAD_SD2_DAT4__SD2_DATA4		0x417059
				MX6SL_PAD_SD2_DAT5__SD2_DATA5		0x417059
				MX6SL_PAD_SD2_DAT6__SD2_DATA6		0x417059
				MX6SL_PAD_SD2_DAT7__SD2_DATA7		0x417059
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				MX6SL_PAD_SD2_CMD__SD2_CMD		0x4170b9
				MX6SL_PAD_SD2_CLK__SD2_CLK		0x4100b9
				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x4170b9
				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x4170b9
				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x4170b9
				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x4170b9
				MX6SL_PAD_SD2_DAT4__SD2_DATA4		0x4170b9
				MX6SL_PAD_SD2_DAT5__SD2_DATA5		0x4170b9
				MX6SL_PAD_SD2_DAT6__SD2_DATA6		0x4170b9
				MX6SL_PAD_SD2_DAT7__SD2_DATA7		0x4170b9
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				MX6SL_PAD_SD2_CMD__SD2_CMD		0x4170f9
				MX6SL_PAD_SD2_CLK__SD2_CLK		0x4100f9
				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x4170f9
				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x4170f9
				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x4170f9
				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x4170f9
				MX6SL_PAD_SD2_DAT4__SD2_DATA4		0x4170f9
				MX6SL_PAD_SD2_DAT5__SD2_DATA5		0x4170f9
				MX6SL_PAD_SD2_DAT6__SD2_DATA6		0x4170f9
				MX6SL_PAD_SD2_DAT7__SD2_DATA7		0x4170f9
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6SL_PAD_SD3_CMD__SD3_CMD		0x417059
				MX6SL_PAD_SD3_CLK__SD3_CLK		0x410059
				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x417059
				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x417059
				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x417059
				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x417059
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				MX6SL_PAD_SD3_CMD__SD3_CMD		0x4170b9
				MX6SL_PAD_SD3_CLK__SD3_CLK		0x4100b9
				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x4170b9
				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x4170b9
				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x4170b9
				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x4170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				MX6SL_PAD_SD3_CMD__SD3_CMD		0x4170f9
				MX6SL_PAD_SD3_CLK__SD3_CLK		0x4100f9
				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x4170f9
				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x4170f9
				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x4170f9
				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x4170f9
			>;
		};
	};
};
Commit	Line	Data
27b0b9d8 OS	1	/*
	2	* Copyright 2014, 2015 O.S. Systems Software LTDA.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public
	20	* License along with this file; if not, write to the Free
	21	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	22	* MA 02110-1301 USA
	23	*
	24	* Or, alternatively,
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use,
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
	48	/dts-v1/;
	49
159097f8	50	#include <dt-bindings/gpio/gpio.h>
27b0b9d8 OS	51	#include "imx6sl.dtsi"
	52
	53	/ {
	54	model = "WaRP Board";
	55	compatible = "warp,imx6sl-warp", "fsl,imx6sl";
	56
	57	memory {
	58	reg = <0x80000000 0x20000000>;
	59	};
	60
159097f8 FE	61	usdhc3_pwrseq: usdhc3_pwrseq {
	62	compatible = "mmc-pwrseq-simple";
	63	reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
	64	<&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
	65	<&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
	66	<&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
	67	};
27b0b9d8 OS	68	};
	69
	70	&uart1 {
	71	pinctrl-names = "default";
	72	pinctrl-0 = <&pinctrl_uart1>;
	73	status = "okay";
	74	};
	75
159097f8 FE	76	&uart2 {
	77	pinctrl-names = "default";
	78	pinctrl-0 = <&pinctrl_uart2>;
	79	fsl,uart-has-rtscts;
	80	status = "okay";
	81	};
	82
27b0b9d8 OS	83	&uart3 {
	84	pinctrl-names = "default";
	85	pinctrl-0 = <&pinctrl_uart3>;
	86	status = "okay";
	87	};
	88
	89	&usbotg1 {
0c1e1896	90	dr_mode = "peripheral";
27b0b9d8 OS	91	disable-over-current;
	92	status = "okay";
	93	};
	94
	95	&usbotg2 {
0c1e1896	96	dr_mode = "host";
27b0b9d8 OS	97	disable-over-current;
	98	status = "okay";
	99	};
	100
	101	&usdhc2 {
	102	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	103	pinctrl-0 = <&pinctrl_usdhc2>;
	104	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	105	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
649b1fe8	106	bus-width = <8>;
27b0b9d8 OS	107	non-removable;
	108	status = "okay";
	109	};
	110
159097f8 FE	111	&usdhc3 {
	112	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	113	pinctrl-0 = <&pinctrl_usdhc3>;
	114	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	115	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	116	bus-width = <4>;
	117	non-removable;
	118	keep-power-in-suspend;
	119	enable-sdio-wakeup;
	120	mmc-pwrseq = <&usdhc3_pwrseq>;
	121	status = "okay";
	122	};
	123
27b0b9d8 OS	124	&iomuxc {
	125	imx6sl-warp {
	126	pinctrl_uart1: uart1grp {
	127	fsl,pins = <
	128	MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1
	129	MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1
	130	>;
	131	};
	132
159097f8 FE	133	pinctrl_uart2: uart2grp {
	134	fsl,pins = <
	135	MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
	136	MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
	137	MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
	138	MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
	139	>;
	140	};
	141
27b0b9d8 OS	142	pinctrl_uart3: uart3grp {
	143	fsl,pins = <
	144	MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1
	145	MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1
	146	>;
	147	};
	148
	149	pinctrl_usdhc2: usdhc2grp {
	150	fsl,pins = <
	151	MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
	152	MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059
	153	MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059
	154	MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059
	155	MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059
	156	MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059
	157	MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059
	158	MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
	159	MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
	160	MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
	161	>;
	162	};
	163
	164	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
	165	fsl,pins = <
	166	MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9
	167	MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9
	168	MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9
	169	MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9
	170	MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9
	171	MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9
	172	MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9
	173	MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
	174	MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
	175	MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
	176	>;
	177	};
	178
	179	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
	180	fsl,pins = <
	181	MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9
	182	MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9
	183	MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9
	184	MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9
	185	MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9
	186	MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9
	187	MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9
	188	MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
	189	MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
	190	MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
	191	>;
	192	};
159097f8 FE	193
	194	pinctrl_usdhc3: usdhc3grp {
	195	fsl,pins = <
	196	MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059
	197	MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059
	198	MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059
	199	MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059
	200	MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059
	201	MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059
	202	>;
	203	};
	204
	205	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	206	fsl,pins = <
	207	MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9
	208	MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9
	209	MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9
	210	MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9
	211	MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9
	212	MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9
	213	>;
	214	};
	215
	216	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	217	fsl,pins = <
	218	MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9
	219	MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9
	220	MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9
	221	MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9
	222	MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9
	223	MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9
	224	>;
	225	};
27b0b9d8 OS	226	};
27b0b9d8 OS	227	};