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Merge tag 'efm32-for-4.4-rc1' of git://git.pengutronix.de/git/ukl/linux into next...
[deliverable/linux.git] / arch / arm / boot / dts / imx6sl.dtsi
CommitLineData
e29fe21c
SG		 1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
13088c23 10#include <dt-bindings/interrupt-controller/irq.h>
e29fe21c
SG		 11#include "skeleton.dtsi"
12#include "imx6sl-pinfunc.h"
13#include <dt-bindings/clock/imx6sl-clock.h>
14
15/ {
16 aliases {
22970070 17 ethernet0 = &fec;
e29fe21c
SG		 18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
640a7f3f
FE		 23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 spi0 = &ecspi1;
29 spi1 = &ecspi2;
30 spi2 = &ecspi3;
31 spi3 = &ecspi4;
8189c51f
PC		 32 usbphy0 = &usbphy1;
33 usbphy1 = &usbphy2;
e29fe21c
SG		 34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0x0>;
44 next-level-cache = <&L2>;
b0d300d3
JT		 45 operating-points = <
46 /* kHz uV */
47 996000 1275000
48 792000 1175000
49 396000 975000
50 >;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
53 996000 1225000
54 792000 1175000
55 396000 1175000
56 >;
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <&reg_arm>;
64 pu-supply = <&reg_pu>;
65 soc-supply = <&reg_soc>;
e29fe21c
SG		 66 };
67 };
68
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
e29fe21c
SG		 72 interrupt-controller;
73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>;
b923ff6a 75 interrupt-parent = <&intc>;
e29fe21c
SG		 76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fixed-clock";
4b2b4043 84 #clock-cells = <0>;
e29fe21c
SG		 85 clock-frequency = <32768>;
86 };
87
88 osc {
89 compatible = "fixed-clock";
4b2b4043 90 #clock-cells = <0>;
e29fe21c
SG		 91 clock-frequency = <24000000>;
92 };
93 };
94
95 soc {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "simple-bus";
b923ff6a 99 interrupt-parent = <&gpc>;
e29fe21c
SG		 100 ranges;
101
248f15a3
AH		 102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x20000>;
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
106 };
107
e29fe21c
SG		 108 L2: l2-cache@00a02000 {
109 compatible = "arm,pl310-cache";
110 reg = <0x00a02000 0x1000>;
13088c23 111 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 112 cache-unified;
113 cache-level = <2>;
114 arm,tag-latency = <4 2 3>;
115 arm,data-latency = <4 2 3>;
116 };
117
118 pmu {
119 compatible = "arm,cortex-a9-pmu";
13088c23 120 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 121 };
122
123 aips1: aips-bus@02000000 {
124 compatible = "fsl,aips-bus", "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x02000000 0x100000>;
128 ranges;
129
130 spba: spba-bus@02000000 {
131 compatible = "fsl,spba-bus", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 reg = <0x02000000 0x40000>;
135 ranges;
136
137 spdif: spdif@02004000 {
138 reg = <0x02004000 0x4000>;
13088c23 139 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 140 };
141
142 ecspi1: ecspi@02008000 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
146 reg = <0x02008000 0x4000>;
13088c23 147 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 148 clocks = <&clks IMX6SL_CLK_ECSPI1>,
149 <&clks IMX6SL_CLK_ECSPI1>;
150 clock-names = "ipg", "per";
151 status = "disabled";
152 };
153
154 ecspi2: ecspi@0200c000 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
158 reg = <0x0200c000 0x4000>;
13088c23 159 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 160 clocks = <&clks IMX6SL_CLK_ECSPI2>,
161 <&clks IMX6SL_CLK_ECSPI2>;
162 clock-names = "ipg", "per";
163 status = "disabled";
164 };
165
166 ecspi3: ecspi@02010000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
170 reg = <0x02010000 0x4000>;
13088c23 171 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 172 clocks = <&clks IMX6SL_CLK_ECSPI3>,
173 <&clks IMX6SL_CLK_ECSPI3>;
174 clock-names = "ipg", "per";
175 status = "disabled";
176 };
177
178 ecspi4: ecspi@02014000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
182 reg = <0x02014000 0x4000>;
13088c23 183 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 184 clocks = <&clks IMX6SL_CLK_ECSPI4>,
185 <&clks IMX6SL_CLK_ECSPI4>;
186 clock-names = "ipg", "per";
187 status = "disabled";
188 };
189
190 uart5: serial@02018000 {
6eb85f91
HS		 191 compatible = "fsl,imx6sl-uart",
192 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 193 reg = <0x02018000 0x4000>;
13088c23 194 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 195 clocks = <&clks IMX6SL_CLK_UART>,
196 <&clks IMX6SL_CLK_UART_SERIAL>;
197 clock-names = "ipg", "per";
72a5cebf
HS		 198 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
199 dma-names = "rx", "tx";
e29fe21c
SG		 200 status = "disabled";
201 };
202
203 uart1: serial@02020000 {
6eb85f91
HS		 204 compatible = "fsl,imx6sl-uart",
205 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 206 reg = <0x02020000 0x4000>;
13088c23 207 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 208 clocks = <&clks IMX6SL_CLK_UART>,
209 <&clks IMX6SL_CLK_UART_SERIAL>;
210 clock-names = "ipg", "per";
72a5cebf
HS		 211 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
212 dma-names = "rx", "tx";
e29fe21c
SG		 213 status = "disabled";
214 };
215
216 uart2: serial@02024000 {
6eb85f91
HS		 217 compatible = "fsl,imx6sl-uart",
218 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 219 reg = <0x02024000 0x4000>;
13088c23 220 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 221 clocks = <&clks IMX6SL_CLK_UART>,
222 <&clks IMX6SL_CLK_UART_SERIAL>;
223 clock-names = "ipg", "per";
72a5cebf
HS		 224 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
225 dma-names = "rx", "tx";
e29fe21c
SG		 226 status = "disabled";
227 };
228
229 ssi1: ssi@02028000 {
6ff7f51e 230 #sound-dai-cells = <0>;
98ea6ad2 231 compatible = "fsl,imx6sl-ssi",
4c03527e 232 "fsl,imx51-ssi";
e29fe21c 233 reg = <0x02028000 0x4000>;
13088c23 234 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
50a8835b
SW		 235 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
236 <&clks IMX6SL_CLK_SSI1>;
237 clock-names = "ipg", "baud";
5da826ab
SG		 238 dmas = <&sdma 37 1 0>,
239 <&sdma 38 1 0>;
240 dma-names = "rx", "tx";
e29fe21c
SG		 241 fsl,fifo-depth = <15>;
242 status = "disabled";
243 };
244
245 ssi2: ssi@0202c000 {
6ff7f51e 246 #sound-dai-cells = <0>;
98ea6ad2 247 compatible = "fsl,imx6sl-ssi",
4c03527e 248 "fsl,imx51-ssi";
e29fe21c 249 reg = <0x0202c000 0x4000>;
13088c23 250 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
50a8835b
SW		 251 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
252 <&clks IMX6SL_CLK_SSI2>;
253 clock-names = "ipg", "baud";
5da826ab
SG		 254 dmas = <&sdma 41 1 0>,
255 <&sdma 42 1 0>;
256 dma-names = "rx", "tx";
e29fe21c
SG		 257 fsl,fifo-depth = <15>;
258 status = "disabled";
259 };
260
261 ssi3: ssi@02030000 {
6ff7f51e 262 #sound-dai-cells = <0>;
98ea6ad2 263 compatible = "fsl,imx6sl-ssi",
4c03527e 264 "fsl,imx51-ssi";
e29fe21c 265 reg = <0x02030000 0x4000>;
13088c23 266 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
50a8835b
SW		 267 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
268 <&clks IMX6SL_CLK_SSI3>;
269 clock-names = "ipg", "baud";
5da826ab
SG		 270 dmas = <&sdma 45 1 0>,
271 <&sdma 46 1 0>;
272 dma-names = "rx", "tx";
e29fe21c
SG		 273 fsl,fifo-depth = <15>;
274 status = "disabled";
275 };
276
277 uart3: serial@02034000 {
6eb85f91
HS		 278 compatible = "fsl,imx6sl-uart",
279 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 280 reg = <0x02034000 0x4000>;
13088c23 281 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 282 clocks = <&clks IMX6SL_CLK_UART>,
283 <&clks IMX6SL_CLK_UART_SERIAL>;
284 clock-names = "ipg", "per";
72a5cebf
HS		 285 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
286 dma-names = "rx", "tx";
e29fe21c
SG		 287 status = "disabled";
288 };
289
290 uart4: serial@02038000 {
6eb85f91
HS		 291 compatible = "fsl,imx6sl-uart",
292 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 293 reg = <0x02038000 0x4000>;
13088c23 294 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 295 clocks = <&clks IMX6SL_CLK_UART>,
296 <&clks IMX6SL_CLK_UART_SERIAL>;
297 clock-names = "ipg", "per";
72a5cebf
HS		 298 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
299 dma-names = "rx", "tx";
e29fe21c
SG		 300 status = "disabled";
301 };
302 };
303
304 pwm1: pwm@02080000 {
305 #pwm-cells = <2>;
306 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
307 reg = <0x02080000 0x4000>;
13088c23 308 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 309 clocks = <&clks IMX6SL_CLK_PWM1>,
310 <&clks IMX6SL_CLK_PWM1>;
311 clock-names = "ipg", "per";
312 };
313
314 pwm2: pwm@02084000 {
315 #pwm-cells = <2>;
316 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
317 reg = <0x02084000 0x4000>;
13088c23 318 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 319 clocks = <&clks IMX6SL_CLK_PWM2>,
320 <&clks IMX6SL_CLK_PWM2>;
321 clock-names = "ipg", "per";
322 };
323
324 pwm3: pwm@02088000 {
325 #pwm-cells = <2>;
326 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
327 reg = <0x02088000 0x4000>;
13088c23 328 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 329 clocks = <&clks IMX6SL_CLK_PWM3>,
330 <&clks IMX6SL_CLK_PWM3>;
331 clock-names = "ipg", "per";
332 };
333
334 pwm4: pwm@0208c000 {
335 #pwm-cells = <2>;
336 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
337 reg = <0x0208c000 0x4000>;
13088c23 338 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 339 clocks = <&clks IMX6SL_CLK_PWM4>,
340 <&clks IMX6SL_CLK_PWM4>;
341 clock-names = "ipg", "per";
342 };
343
344 gpt: gpt@02098000 {
345 compatible = "fsl,imx6sl-gpt";
346 reg = <0x02098000 0x4000>;
13088c23 347 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 348 clocks = <&clks IMX6SL_CLK_GPT>,
349 <&clks IMX6SL_CLK_GPT_SERIAL>;
350 clock-names = "ipg", "per";
351 };
352
353 gpio1: gpio@0209c000 {
354 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
355 reg = <0x0209c000 0x4000>;
13088c23
TK		 356 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
357 <0 67 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 };
363
364 gpio2: gpio@020a0000 {
365 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
366 reg = <0x020a0000 0x4000>;
13088c23
TK		 367 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
368 <0 69 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 };
374
375 gpio3: gpio@020a4000 {
376 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
377 reg = <0x020a4000 0x4000>;
13088c23
TK		 378 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
379 <0 71 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 gpio4: gpio@020a8000 {
387 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
388 reg = <0x020a8000 0x4000>;
13088c23
TK		 389 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
390 <0 73 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
395 };
396
397 gpio5: gpio@020ac000 {
398 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
399 reg = <0x020ac000 0x4000>;
13088c23
TK		 400 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
401 <0 75 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 };
407
408 kpp: kpp@020b8000 {
4291b645 409 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
e29fe21c 410 reg = <0x020b8000 0x4000>;
13088c23 411 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
4291b645 412 clocks = <&clks IMX6SL_CLK_DUMMY>;
1b6f2368 413 status = "disabled";
e29fe21c
SG		 414 };
415
416 wdog1: wdog@020bc000 {
417 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
418 reg = <0x020bc000 0x4000>;
13088c23 419 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 420 clocks = <&clks IMX6SL_CLK_DUMMY>;
421 };
422
423 wdog2: wdog@020c0000 {
424 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
425 reg = <0x020c0000 0x4000>;
13088c23 426 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 427 clocks = <&clks IMX6SL_CLK_DUMMY>;
428 status = "disabled";
429 };
430
431 clks: ccm@020c4000 {
432 compatible = "fsl,imx6sl-ccm";
433 reg = <0x020c4000 0x4000>;
13088c23
TK		 434 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
435 <0 88 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 436 #clock-cells = <1>;
437 };
438
439 anatop: anatop@020c8000 {
d8ce823f
SG		 440 compatible = "fsl,imx6sl-anatop",
441 "fsl,imx6q-anatop",
442 "syscon", "simple-bus";
e29fe21c 443 reg = <0x020c8000 0x1000>;
13088c23
TK		 444 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
445 <0 54 IRQ_TYPE_LEVEL_HIGH>,
446 <0 127 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 447
448 regulator-1p1@110 {
449 compatible = "fsl,anatop-regulator";
450 regulator-name = "vdd1p1";
451 regulator-min-microvolt = <800000>;
452 regulator-max-microvolt = <1375000>;
453 regulator-always-on;
454 anatop-reg-offset = <0x110>;
455 anatop-vol-bit-shift = <8>;
456 anatop-vol-bit-width = <5>;
457 anatop-min-bit-val = <4>;
458 anatop-min-voltage = <800000>;
459 anatop-max-voltage = <1375000>;
460 };
461
462 regulator-3p0@120 {
463 compatible = "fsl,anatop-regulator";
464 regulator-name = "vdd3p0";
465 regulator-min-microvolt = <2800000>;
466 regulator-max-microvolt = <3150000>;
467 regulator-always-on;
468 anatop-reg-offset = <0x120>;
469 anatop-vol-bit-shift = <8>;
470 anatop-vol-bit-width = <5>;
471 anatop-min-bit-val = <0>;
472 anatop-min-voltage = <2625000>;
473 anatop-max-voltage = <3400000>;
474 };
475
476 regulator-2p5@130 {
477 compatible = "fsl,anatop-regulator";
478 regulator-name = "vdd2p5";
479 regulator-min-microvolt = <2100000>;
480 regulator-max-microvolt = <2850000>;
481 regulator-always-on;
482 anatop-reg-offset = <0x130>;
483 anatop-vol-bit-shift = <8>;
484 anatop-vol-bit-width = <5>;
485 anatop-min-bit-val = <0>;
486 anatop-min-voltage = <2100000>;
487 anatop-max-voltage = <2850000>;
488 };
489
490 reg_arm: regulator-vddcore@140 {
491 compatible = "fsl,anatop-regulator";
118c98a6 492 regulator-name = "vddarm";
e29fe21c
SG		 493 regulator-min-microvolt = <725000>;
494 regulator-max-microvolt = <1450000>;
495 regulator-always-on;
496 anatop-reg-offset = <0x140>;
497 anatop-vol-bit-shift = <0>;
498 anatop-vol-bit-width = <5>;
499 anatop-delay-reg-offset = <0x170>;
500 anatop-delay-bit-shift = <24>;
501 anatop-delay-bit-width = <2>;
502 anatop-min-bit-val = <1>;
503 anatop-min-voltage = <725000>;
504 anatop-max-voltage = <1450000>;
505 };
506
507 reg_pu: regulator-vddpu@140 {
508 compatible = "fsl,anatop-regulator";
509 regulator-name = "vddpu";
510 regulator-min-microvolt = <725000>;
511 regulator-max-microvolt = <1450000>;
512 regulator-always-on;
513 anatop-reg-offset = <0x140>;
514 anatop-vol-bit-shift = <9>;
515 anatop-vol-bit-width = <5>;
516 anatop-delay-reg-offset = <0x170>;
517 anatop-delay-bit-shift = <26>;
518 anatop-delay-bit-width = <2>;
519 anatop-min-bit-val = <1>;
520 anatop-min-voltage = <725000>;
521 anatop-max-voltage = <1450000>;
522 };
523
524 reg_soc: regulator-vddsoc@140 {
525 compatible = "fsl,anatop-regulator";
526 regulator-name = "vddsoc";
527 regulator-min-microvolt = <725000>;
528 regulator-max-microvolt = <1450000>;
529 regulator-always-on;
530 anatop-reg-offset = <0x140>;
531 anatop-vol-bit-shift = <18>;
532 anatop-vol-bit-width = <5>;
533 anatop-delay-reg-offset = <0x170>;
534 anatop-delay-bit-shift = <28>;
535 anatop-delay-bit-width = <2>;
536 anatop-min-bit-val = <1>;
537 anatop-min-voltage = <725000>;
538 anatop-max-voltage = <1450000>;
539 };
540 };
541
2998b332
AH		 542 tempmon: tempmon {
543 compatible = "fsl,imx6q-tempmon";
544 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
545 fsl,tempmon = <&anatop>;
546 fsl,tempmon-data = <&ocotp>;
547 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
548 };
549
e29fe21c
SG		 550 usbphy1: usbphy@020c9000 {
551 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
552 reg = <0x020c9000 0x1000>;
13088c23 553 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 554 clocks = <&clks IMX6SL_CLK_USBPHY1>;
76a38855 555 fsl,anatop = <&anatop>;
e29fe21c
SG		 556 };
557
558 usbphy2: usbphy@020ca000 {
559 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
560 reg = <0x020ca000 0x1000>;
13088c23 561 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 562 clocks = <&clks IMX6SL_CLK_USBPHY2>;
76a38855 563 fsl,anatop = <&anatop>;
e29fe21c
SG		 564 };
565
95d739b5
FL		 566 snvs: snvs@020cc000 {
567 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
568 reg = <0x020cc000 0x4000>;
e29fe21c 569
95d739b5 570 snvs_rtc: snvs-rtc-lp {
e29fe21c 571 compatible = "fsl,sec-v4.0-mon-rtc-lp";
95d739b5
FL		 572 regmap = <&snvs>;
573 offset = <0x34>;
13088c23
TK		 574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
575 <0 20 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 576 };
422b0676 577
95d739b5
FL		 578 snvs_poweroff: snvs-poweroff {
579 compatible = "syscon-poweroff";
580 regmap = <&snvs>;
581 offset = <0x38>;
582 mask = <0x60>;
422b0676
RG		 583 status = "disabled";
584 };
e29fe21c
SG		 585 };
586
587 epit1: epit@020d0000 {
588 reg = <0x020d0000 0x4000>;
13088c23 589 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 590 };
591
592 epit2: epit@020d4000 {
593 reg = <0x020d4000 0x4000>;
13088c23 594 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 595 };
596
597 src: src@020d8000 {
598 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
599 reg = <0x020d8000 0x4000>;
13088c23
TK		 600 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
601 <0 96 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 602 #reset-cells = <1>;
603 };
604
605 gpc: gpc@020dc000 {
606 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
607 reg = <0x020dc000 0x4000>;
b923ff6a
MZ		 608 interrupt-controller;
609 #interrupt-cells = <3>;
13088c23 610 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
b923ff6a 611 interrupt-parent = <&intc>;
016dbd7a
PZ		 612 pu-supply = <&reg_pu>;
613 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
614 <&clks IMX6SL_CLK_GPU2D_PODF>;
615 #power-domain-cells = <1>;
e29fe21c
SG		 616 };
617
e03d10f9 618 gpr: iomuxc-gpr@020e0000 {
5f7adc97
SG		 619 compatible = "fsl,imx6sl-iomuxc-gpr",
620 "fsl,imx6q-iomuxc-gpr", "syscon";
e03d10f9
FD		 621 reg = <0x020e0000 0x38>;
622 };
e29fe21c
SG		 623
624 iomuxc: iomuxc@020e0000 {
625 compatible = "fsl,imx6sl-iomuxc";
626 reg = <0x020e0000 0x4000>;
e29fe21c
SG		 627 };
628
629 csi: csi@020e4000 {
630 reg = <0x020e4000 0x4000>;
13088c23 631 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 632 };
633
634 spdc: spdc@020e8000 {
635 reg = <0x020e8000 0x4000>;
13088c23 636 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 637 };
638
639 sdma: sdma@020ec000 {
811e7685 640 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
e29fe21c 641 reg = <0x020ec000 0x4000>;
13088c23 642 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 643 clocks = <&clks IMX6SL_CLK_SDMA>,
644 <&clks IMX6SL_CLK_SDMA>;
645 clock-names = "ipg", "ahb";
fb72bb21 646 #dma-cells = <3>;
44a26877
SG		 647 /* imx6sl reuses imx6q sdma firmware */
648 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
e29fe21c
SG		 649 };
650
651 pxp: pxp@020f0000 {
652 reg = <0x020f0000 0x4000>;
13088c23 653 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 654 };
655
656 epdc: epdc@020f4000 {
657 reg = <0x020f4000 0x4000>;
13088c23 658 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 659 };
660
661 lcdif: lcdif@020f8000 {
e99b077b 662 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
e29fe21c 663 reg = <0x020f8000 0x4000>;
13088c23 664 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
e99b077b
FE		 665 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
666 <&clks IMX6SL_CLK_LCDIF_AXI>,
667 <&clks IMX6SL_CLK_DUMMY>;
668 clock-names = "pix", "axi", "disp_axi";
669 status = "disabled";
e29fe21c
SG		 670 };
671
672 dcp: dcp@020fc000 {
673 reg = <0x020fc000 0x4000>;
13088c23 674 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 675 };
676 };
677
678 aips2: aips-bus@02100000 {
679 compatible = "fsl,aips-bus", "simple-bus";
680 #address-cells = <1>;
681 #size-cells = <1>;
682 reg = <0x02100000 0x100000>;
683 ranges;
684
685 usbotg1: usb@02184000 {
686 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
687 reg = <0x02184000 0x200>;
13088c23 688 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 689 clocks = <&clks IMX6SL_CLK_USBOH3>;
690 fsl,usbphy = <&usbphy1>;
691 fsl,usbmisc = <&usbmisc 0>;
692 status = "disabled";
693 };
694
695 usbotg2: usb@02184200 {
696 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
697 reg = <0x02184200 0x200>;
13088c23 698 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 699 clocks = <&clks IMX6SL_CLK_USBOH3>;
700 fsl,usbphy = <&usbphy2>;
701 fsl,usbmisc = <&usbmisc 1>;
702 status = "disabled";
703 };
704
705 usbh: usb@02184400 {
706 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
707 reg = <0x02184400 0x200>;
13088c23 708 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 709 clocks = <&clks IMX6SL_CLK_USBOH3>;
710 fsl,usbmisc = <&usbmisc 2>;
3ec481ed 711 dr_mode = "host";
e29fe21c
SG		 712 status = "disabled";
713 };
714
715 usbmisc: usbmisc@02184800 {
716 #index-cells = <1>;
717 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
718 reg = <0x02184800 0x200>;
719 clocks = <&clks IMX6SL_CLK_USBOH3>;
720 };
721
722 fec: ethernet@02188000 {
723 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
724 reg = <0x02188000 0x4000>;
13088c23 725 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
8c562a1e 726 clocks = <&clks IMX6SL_CLK_ENET>,
e29fe21c
SG		 727 <&clks IMX6SL_CLK_ENET_REF>;
728 clock-names = "ipg", "ahb";
729 status = "disabled";
730 };
731
732 usdhc1: usdhc@02190000 {
733 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
734 reg = <0x02190000 0x4000>;
13088c23 735 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 736 clocks = <&clks IMX6SL_CLK_USDHC1>,
737 <&clks IMX6SL_CLK_USDHC1>,
738 <&clks IMX6SL_CLK_USDHC1>;
739 clock-names = "ipg", "ahb", "per";
740 bus-width = <4>;
741 status = "disabled";
742 };
743
744 usdhc2: usdhc@02194000 {
745 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
746 reg = <0x02194000 0x4000>;
13088c23 747 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 748 clocks = <&clks IMX6SL_CLK_USDHC2>,
749 <&clks IMX6SL_CLK_USDHC2>,
750 <&clks IMX6SL_CLK_USDHC2>;
751 clock-names = "ipg", "ahb", "per";
752 bus-width = <4>;
753 status = "disabled";
754 };
755
756 usdhc3: usdhc@02198000 {
757 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
758 reg = <0x02198000 0x4000>;
13088c23 759 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 760 clocks = <&clks IMX6SL_CLK_USDHC3>,
761 <&clks IMX6SL_CLK_USDHC3>,
762 <&clks IMX6SL_CLK_USDHC3>;
763 clock-names = "ipg", "ahb", "per";
764 bus-width = <4>;
765 status = "disabled";
766 };
767
768 usdhc4: usdhc@0219c000 {
769 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
770 reg = <0x0219c000 0x4000>;
13088c23 771 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 772 clocks = <&clks IMX6SL_CLK_USDHC4>,
773 <&clks IMX6SL_CLK_USDHC4>,
774 <&clks IMX6SL_CLK_USDHC4>;
775 clock-names = "ipg", "ahb", "per";
776 bus-width = <4>;
777 status = "disabled";
778 };
779
780 i2c1: i2c@021a0000 {
781 #address-cells = <1>;
782 #size-cells = <0>;
783 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
784 reg = <0x021a0000 0x4000>;
13088c23 785 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 786 clocks = <&clks IMX6SL_CLK_I2C1>;
787 status = "disabled";
788 };
789
790 i2c2: i2c@021a4000 {
791 #address-cells = <1>;
792 #size-cells = <0>;
793 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
794 reg = <0x021a4000 0x4000>;
13088c23 795 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 796 clocks = <&clks IMX6SL_CLK_I2C2>;
797 status = "disabled";
798 };
799
800 i2c3: i2c@021a8000 {
801 #address-cells = <1>;
802 #size-cells = <0>;
803 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
804 reg = <0x021a8000 0x4000>;
13088c23 805 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 806 clocks = <&clks IMX6SL_CLK_I2C3>;
807 status = "disabled";
808 };
809
810 mmdc: mmdc@021b0000 {
811 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
812 reg = <0x021b0000 0x4000>;
813 };
814
815 rngb: rngb@021b4000 {
816 reg = <0x021b4000 0x4000>;
13088c23 817 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 818 };
819
820 weim: weim@021b8000 {
821 reg = <0x021b8000 0x4000>;
13088c23 822 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 823 };
824
825 ocotp: ocotp@021bc000 {
2998b332 826 compatible = "fsl,imx6sl-ocotp", "syscon";
e29fe21c
SG		 827 reg = <0x021bc000 0x4000>;
828 };
829
830 audmux: audmux@021d8000 {
831 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
832 reg = <0x021d8000 0x4000>;
833 status = "disabled";
834 };
835 };
836 };
837};
Linux kernel - Deliverables
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