[deliverable/linux.git] / arch / arm / boot / dts / imx6sx-sdb.dtsi

/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"

/ {
	model = "Freescale i.MX6 SoloX SDB Board";
	compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";

	chosen {
		stdout-path = &uart1;
	};

	memory {
		reg = <0x80000000 0x40000000>;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		volume-up {
			label = "Volume Up";
			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEUP>;
		};

		volume-down {
			label = "Volume Down";
			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEDOWN>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		vcc_sd3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_vcc_sd3>;
			regulator-name = "VCC_SD3";
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg1_vbus: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb_otg1>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg2_vbus: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb_otg2>;
			regulator-name = "usb_otg2_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_psu_5v: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "PSU-5V0";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
		};

		reg_lcd_3v3: regulator@4 {
			compatible = "regulator-fixed";
			reg = <4>;
			regulator-name = "lcd-3v3";
			gpio = <&gpio3 27 0>;
			enable-active-high;
		};

		reg_peri_3v3: regulator@5 {
			compatible = "regulator-fixed";
			reg = <5>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_peri_3v3>;
			regulator-name = "peri_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			regulator-always-on;
		};

		reg_enet_3v3: regulator@6 {
			compatible = "regulator-fixed";
			reg = <6>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_enet_3v3>;
			regulator-name = "enet_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
		};
	};

	sound {
		compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		ssi-controller = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
		mux-int-port = <2>;
		mux-ext-port = <6>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-supply = <&reg_enet_3v3>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
		};

		ethphy2: ethernet-phy@2 {
			reg = <2>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&i2c4 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c4>;
        status = "okay";

	codec: wm8962@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clks IMX6SX_CLK_AUDIO>;
		DCVDD-supply = <&vgen4_reg>;
		DBVDD-supply = <&vgen4_reg>;
		AVDD-supply = <&vgen4_reg>;
		CPVDD-supply = <&vgen4_reg>;
		MICVDD-supply = <&vgen3_reg>;
		PLLVDD-supply = <&vgen4_reg>;
		SPKVDD1-supply = <&reg_psu_5v>;
		SPKVDD2-supply = <&reg_psu_5v>;
	};
};

&lcdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	lcd-supply = <&reg_lcd_3v3>;
	display = <&display0>;
	status = "okay";

	display0: display0 {
		bits-per-pixel = <16>;
		bus-width = <24>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <33500000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <89>;
				hfront-porch = <164>;
				vback-porch = <23>;
				vfront-porch = <10>;
				hsync-len = <10>;
				vsync-len = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&snvs_poweroff {
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "disabled";
};

&ssi2 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart5 { /* for bluetooth */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&vcc_sd3>;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&iomuxc {
	imx6x-sdb {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC	0x130b0
				MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS	0x130b0
				MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD	0x120b0
				MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD	0x130b0
				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK	0x130b0
			>;
		};

		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0xa0b1
				MX6SX_PAD_ENET1_MDC__ENET1_MDC		0xa0b1
				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0xa0b1
				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0xa0b1
				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0xa0b1
				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0xa0b1
				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK	0x3081
				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
			>;
		};

		pinctrl_enet_3v3: enet3v3grp {
			fsl,pins = <
				MX6SX_PAD_ENET2_COL__GPIO2_IO_6		0x80000000
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
			>;
		};

		pinctrl_gpio_keys: gpio_keysgrp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
				MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO01__I2C1_SDA		0x4001b8b1
				MX6SX_PAD_GPIO1_IO00__I2C1_SCL		0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW4__I2C3_SDA		0x4001b8b1
				MX6SX_PAD_KEY_COL4__I2C3_SCL		0x4001b8b1
			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA07__I2C4_SDA		0x4001b8b1
				MX6SX_PAD_CSI_DATA06__I2C4_SCL		0x4001b8b1
			>;
		};

		pinctrl_lcd: lcdgrp {
			fsl,pins = <
				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
				MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
				MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
				MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
				MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
				MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
				MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
				MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
				MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
				MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
				MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
				MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
				MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
				MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
				MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
				MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
				MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
				MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
				MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
				MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
				MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
				MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
				MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
				MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
				MX6SX_PAD_LCD1_CLK__LCDIF1_CLK	0x4001b0b0
				MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
				MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
				MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
			>;
		};

		pinctrl_peri_3v3: peri3v3grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
			>;
		};

		pinctrl_pwm3: pwm3grp-1 {
			fsl,pins = <
				MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
			>;
		};

		pinctrl_qspi2: qspi2grp {
			fsl,pins = <
				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
				MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
				MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
				MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
				MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
				MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
				MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
				MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
				MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
				MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
				MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
				MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
			>;
		};

		pinctrl_vcc_sd3: vccsd3grp {
			fsl,pins = <
				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
			>;
		};

		pinctrl_sai1: sai1grp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK	0x130b0
				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC	0x130b0
				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0	0x120b0
				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0	0x130b0
				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK	0x130b0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
				MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW3__UART5_RX		0x1b0b1
				MX6SX_PAD_KEY_COL3__UART5_TX		0x1b0b1
				MX6SX_PAD_KEY_ROW2__UART5_CTS_B		0x1b0b1
				MX6SX_PAD_KEY_COL2__UART5_RTS_B		0x1b0b1
			>;
		};

		pinctrl_usb_otg1: usbotg1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9	0x10b0
			>;
		};

		pinctrl_usb_otg1_id: usbotg1idgrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID	0x17059
			>;
		};

		pinctrl_usb_otg2: usbot2ggrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12	0x10b0
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6SX_PAD_SD2_CMD__USDHC2_CMD		0x17059
				MX6SX_PAD_SD2_CLK__USDHC2_CLK		0x10059
				MX6SX_PAD_SD2_DATA0__USDHC2_DATA0	0x17059
				MX6SX_PAD_SD2_DATA1__USDHC2_DATA1	0x17059
				MX6SX_PAD_SD2_DATA2__USDHC2_DATA2	0x17059
				MX6SX_PAD_SD2_DATA3__USDHC2_DATA3	0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17059
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x10059
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x17059
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x17059
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x17059
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x17059
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x17059
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x17059
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x17059
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x17059
				MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x17059 /* CD */
				MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x17059 /* WP */
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170b9
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100b9
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170b9
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170b9
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170b9
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170b9
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170b9
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170b9
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170b9
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170f9
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100f9
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170f9
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170f9
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170f9
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170f9
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170f9
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170f9
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170f9
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170f9
			>;
		};

		pinctrl_usdhc4: usdhc4grp {
			fsl,pins = <
				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
				MX6SX_PAD_SD4_DATA7__GPIO6_IO_21	0x17059 /* CD */
				MX6SX_PAD_SD4_DATA6__GPIO6_IO_20	0x17059 /* WP */
			>;
		};
	};
};
Commit	Line	Data
d2daa2f7 SG	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/dts-v1/;
	10
4014a4f7 AH	11	#include <dt-bindings/gpio/gpio.h>
4014a4f7 AH	12	#include <dt-bindings/input/input.h>
d2daa2f7 SG	13	#include "imx6sx.dtsi"
	14
	15	/ {
	16	model = "Freescale i.MX6 SoloX SDB Board";
	17	compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
	18
	19	chosen {
	20	stdout-path = &uart1;
	21	};
	22
	23	memory {
	24	reg = <0x80000000 0x40000000>;
	25	};
	26
31ffdbc8 FE	27	backlight {
	28	compatible = "pwm-backlight";
	29	pwms = <&pwm3 0 5000000>;
	30	brightness-levels = <0 4 8 16 32 64 128 255>;
	31	default-brightness-level = <6>;
	32	};
	33
4014a4f7 AH	34	gpio-keys {
	35	compatible = "gpio-keys";
	36	pinctrl-names = "default";
	37	pinctrl-0 = <&pinctrl_gpio_keys>;
	38
	39	volume-up {
	40	label = "Volume Up";
	41	gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
	42	linux,code = <KEY_VOLUMEUP>;
	43	};
	44
	45	volume-down {
	46	label = "Volume Down";
	47	gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	48	linux,code = <KEY_VOLUMEDOWN>;
	49	};
	50	};
	51
d2daa2f7 SG	52	regulators {
	53	compatible = "simple-bus";
	54	#address-cells = <1>;
	55	#size-cells = <0>;
	56
	57	vcc_sd3: regulator@0 {
	58	compatible = "regulator-fixed";
	59	reg = <0>;
	60	pinctrl-names = "default";
	61	pinctrl-0 = <&pinctrl_vcc_sd3>;
	62	regulator-name = "VCC_SD3";
	63	regulator-min-microvolt = <3000000>;
	64	regulator-max-microvolt = <3000000>;
	65	gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
	66	enable-active-high;
	67	};
960fefff FE	68
	69	reg_usb_otg1_vbus: regulator@1 {
	70	compatible = "regulator-fixed";
	71	reg = <1>;
	72	pinctrl-names = "default";
	73	pinctrl-0 = <&pinctrl_usb_otg1>;
	74	regulator-name = "usb_otg1_vbus";
	75	regulator-min-microvolt = <5000000>;
	76	regulator-max-microvolt = <5000000>;
	77	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	78	enable-active-high;
	79	};
	80
	81	reg_usb_otg2_vbus: regulator@2 {
	82	compatible = "regulator-fixed";
	83	reg = <2>;
	84	pinctrl-names = "default";
	85	pinctrl-0 = <&pinctrl_usb_otg2>;
	86	regulator-name = "usb_otg2_vbus";
	87	regulator-min-microvolt = <5000000>;
	88	regulator-max-microvolt = <5000000>;
	89	gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	90	enable-active-high;
	91	};
9c86ae8c FE	92
	93	reg_psu_5v: regulator@3 {
	94	compatible = "regulator-fixed";
	95	reg = <3>;
	96	regulator-name = "PSU-5V0";
	97	regulator-min-microvolt = <5000000>;
	98	regulator-max-microvolt = <5000000>;
	99	};
31ffdbc8 FE	100
	101	reg_lcd_3v3: regulator@4 {
	102	compatible = "regulator-fixed";
	103	reg = <4>;
	104	regulator-name = "lcd-3v3";
	105	gpio = <&gpio3 27 0>;
	106	enable-active-high;
	107	};
9863aba5 FD	108
	109	reg_peri_3v3: regulator@5 {
	110	compatible = "regulator-fixed";
	111	reg = <5>;
	112	pinctrl-names = "default";
	113	pinctrl-0 = <&pinctrl_peri_3v3>;
	114	regulator-name = "peri_3v3";
	115	regulator-min-microvolt = <3300000>;
	116	regulator-max-microvolt = <3300000>;
9a921459	117	gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
9863aba5 FD	118	enable-active-high;
	119	regulator-always-on;
	120	};
	121
	122	reg_enet_3v3: regulator@6 {
	123	compatible = "regulator-fixed";
	124	reg = <6>;
	125	pinctrl-names = "default";
	126	pinctrl-0 = <&pinctrl_enet_3v3>;
	127	regulator-name = "enet_3v3";
	128	regulator-min-microvolt = <3300000>;
	129	regulator-max-microvolt = <3300000>;
	130	gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
	131	};
9c86ae8c FE	132	};
	133
	134	sound {
	135	compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
	136	model = "wm8962-audio";
	137	ssi-controller = <&ssi2>;
	138	audio-codec = <&codec>;
	139	audio-routing =
	140	"Headphone Jack", "HPOUTL",
	141	"Headphone Jack", "HPOUTR",
	142	"Ext Spk", "SPKOUTL",
	143	"Ext Spk", "SPKOUTR",
	144	"AMIC", "MICBIAS",
	145	"IN3R", "AMIC";
	146	mux-int-port = <2>;
	147	mux-ext-port = <6>;
d2daa2f7 SG	148	};
	149	};
	150
9c86ae8c FE	151	&audmux {
	152	pinctrl-names = "default";
	153	pinctrl-0 = <&pinctrl_audmux>;
	154	status = "okay";
	155	};
	156
d2daa2f7 SG	157	&fec1 {
	158	pinctrl-names = "default";
	159	pinctrl-0 = <&pinctrl_enet1>;
9863aba5 FD	160	phy-supply = <&reg_enet_3v3>;
9863aba5 FD	161	phy-mode = "rgmii";
3d125f9c	162	phy-handle = <&ethphy1>;
9863aba5	163	status = "okay";
3d125f9c SA	164
	165	mdio {
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168
9143e398 NA	169	ethphy1: ethernet-phy@1 {
9143e398 NA	170	reg = <1>;
3d125f9c SA	171	};
3d125f9c SA	172
9143e398 NA	173	ethphy2: ethernet-phy@2 {
9143e398 NA	174	reg = <2>;
3d125f9c SA	175	};
3d125f9c SA	176	};
9863aba5 FD	177	};
	178
	179	&fec2 {
	180	pinctrl-names = "default";
	181	pinctrl-0 = <&pinctrl_enet2>;
d2daa2f7	182	phy-mode = "rgmii";
3d125f9c	183	phy-handle = <&ethphy2>;
d2daa2f7 SG	184	status = "okay";
	185	};
	186
b0e96f83 CF	187	&i2c3 {
	188	clock-frequency = <100000>;
	189	pinctrl-names = "default";
	190	pinctrl-0 = <&pinctrl_i2c3>;
	191	status = "okay";
	192	};
	193
9c86ae8c FE	194	&i2c4 {
	195	clock-frequency = <100000>;
	196	pinctrl-names = "default";
	197	pinctrl-0 = <&pinctrl_i2c4>;
	198	status = "okay";
	199
	200	codec: wm8962@1a {
	201	compatible = "wlf,wm8962";
	202	reg = <0x1a>;
	203	clocks = <&clks IMX6SX_CLK_AUDIO>;
	204	DCVDD-supply = <&vgen4_reg>;
	205	DBVDD-supply = <&vgen4_reg>;
	206	AVDD-supply = <&vgen4_reg>;
	207	CPVDD-supply = <&vgen4_reg>;
	208	MICVDD-supply = <&vgen3_reg>;
	209	PLLVDD-supply = <&vgen4_reg>;
	210	SPKVDD1-supply = <&reg_psu_5v>;
	211	SPKVDD2-supply = <&reg_psu_5v>;
	212	};
	213	};
	214
31ffdbc8 FE	215	&lcdif1 {
	216	pinctrl-names = "default";
	217	pinctrl-0 = <&pinctrl_lcd>;
	218	lcd-supply = <&reg_lcd_3v3>;
	219	display = <&display0>;
	220	status = "okay";
	221
	222	display0: display0 {
	223	bits-per-pixel = <16>;
	224	bus-width = <24>;
	225
	226	display-timings {
	227	native-mode = <&timing0>;
	228	timing0: timing0 {
	229	clock-frequency = <33500000>;
	230	hactive = <800>;
	231	vactive = <480>;
	232	hback-porch = <89>;
	233	hfront-porch = <164>;
	234	vback-porch = <23>;
	235	vfront-porch = <10>;
	236	hsync-len = <10>;
	237	vsync-len = <10>;
	238	hsync-active = <0>;
	239	vsync-active = <0>;
	240	de-active = <1>;
	241	pixelclk-active = <0>;
	242	};
	243	};
	244	};
	245	};
	246
	247	&pwm3 {
	248	pinctrl-names = "default";
	249	pinctrl-0 = <&pinctrl_pwm3>;
	250	status = "okay";
	251	};
	252
422b0676 RG	253	&snvs_poweroff {
	254	status = "okay";
	255	};
	256
29e88b6d FE	257	&sai1 {
	258	pinctrl-names = "default";
	259	pinctrl-0 = <&pinctrl_sai1>;
	260	status = "disabled";
	261	};
	262
9c86ae8c FE	263	&ssi2 {
	264	status = "okay";
	265	};
	266
d2daa2f7 SG	267	&uart1 {
	268	pinctrl-names = "default";
	269	pinctrl-0 = <&pinctrl_uart1>;
	270	status = "okay";
	271	};
	272
	273	&uart5 { /* for bluetooth */
	274	pinctrl-names = "default";
	275	pinctrl-0 = <&pinctrl_uart5>;
	276	fsl,uart-has-rtscts;
	277	status = "okay";
	278	};
	279
960fefff FE	280	&usbotg1 {
	281	vbus-supply = <&reg_usb_otg1_vbus>;
	282	pinctrl-names = "default";
	283	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	284	status = "okay";
	285	};
	286
	287	&usbotg2 {
	288	vbus-supply = <&reg_usb_otg2_vbus>;
	289	dr_mode = "host";
	290	status = "okay";
	291	};
	292
d2daa2f7 SG	293	&usdhc2 {
	294	pinctrl-names = "default";
	295	pinctrl-0 = <&pinctrl_usdhc2>;
	296	non-removable;
	297	no-1-8-v;
	298	keep-power-in-suspend;
26cefdd1	299	wakeup-source;
d2daa2f7 SG	300	status = "okay";
	301	};
	302
	303	&usdhc3 {
	304	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	305	pinctrl-0 = <&pinctrl_usdhc3>;
	306	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	307	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	308	bus-width = <8>;
89c1a8cf	309	cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
d2daa2f7 SG	310	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
d2daa2f7 SG	311	keep-power-in-suspend;
26cefdd1	312	wakeup-source;
d2daa2f7 SG	313	vmmc-supply = <&vcc_sd3>;
	314	status = "okay";
	315	};
	316
	317	&usdhc4 {
	318	pinctrl-names = "default";
	319	pinctrl-0 = <&pinctrl_usdhc4>;
89c1a8cf	320	cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
d2daa2f7 SG	321	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
	322	status = "okay";
	323	};
	324
	325	&iomuxc {
	326	imx6x-sdb {
9c86ae8c FE	327	pinctrl_audmux: audmuxgrp {
	328	fsl,pins = <
	329	MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
	330	MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
	331	MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
	332	MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
	333	MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
	334	>;
	335	};
	336
d2daa2f7 SG	337	pinctrl_enet1: enet1grp {
	338	fsl,pins = <
	339	MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
	340	MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
	341	MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
	342	MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
	343	MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
	344	MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
	345	MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
	346	MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
	347	MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
	348	MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
	349	MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
	350	MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
	351	MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
	352	MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
9863aba5 FD	353	MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
	354	>;
	355	};
	356
	357	pinctrl_enet_3v3: enet3v3grp {
	358	fsl,pins = <
	359	MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
	360	>;
	361	};
	362
	363	pinctrl_enet2: enet2grp {
	364	fsl,pins = <
	365	MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
	366	MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
	367	MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
	368	MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
	369	MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
	370	MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
	371	MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
	372	MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
	373	MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
	374	MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
	375	MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
	376	MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
d2daa2f7 SG	377	>;
	378	};
	379
4014a4f7 AH	380	pinctrl_gpio_keys: gpio_keysgrp {
	381	fsl,pins = <
	382	MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
	383	MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
	384	>;
	385	};
	386
b3d8e11f FE	387	pinctrl_i2c1: i2c1grp {
	388	fsl,pins = <
	389	MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
	390	MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
	391	>;
	392	};
	393
b0e96f83 CF	394	pinctrl_i2c3: i2c3grp {
	395	fsl,pins = <
	396	MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
	397	MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
	398	>;
	399	};
	400
9c86ae8c FE	401	pinctrl_i2c4: i2c4grp {
	402	fsl,pins = <
	403	MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
	404	MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
	405	>;
	406	};
	407
31ffdbc8 FE	408	pinctrl_lcd: lcdgrp {
	409	fsl,pins = <
	410	MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
	411	MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
	412	MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
	413	MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
	414	MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
	415	MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
	416	MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
	417	MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
	418	MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
	419	MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
	420	MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
	421	MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
	422	MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
	423	MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
	424	MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
	425	MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
	426	MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
	427	MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
	428	MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
	429	MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
	430	MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
	431	MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
	432	MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
	433	MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
	434	MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
	435	MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
	436	MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
	437	MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
	438	MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
	439	>;
	440	};
	441
9863aba5 FD	442	pinctrl_peri_3v3: peri3v3grp {
	443	fsl,pins = <
	444	MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
	445	>;
	446	};
	447
31ffdbc8 FE	448	pinctrl_pwm3: pwm3grp-1 {
	449	fsl,pins = <
	450	MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
	451	>;
	452	};
	453
c565e146 FE	454	pinctrl_qspi2: qspi2grp {
	455	fsl,pins = <
	456	MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
	457	MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
	458	MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
	459	MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
	460	MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
	461	MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
	462	MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
	463	MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
	464	MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
	465	MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
	466	MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
	467	MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
	468	>;
	469	};
	470
d2daa2f7 SG	471	pinctrl_vcc_sd3: vccsd3grp {
	472	fsl,pins = <
	473	MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
	474	>;
	475	};
	476
29e88b6d FE	477	pinctrl_sai1: sai1grp {
	478	fsl,pins = <
	479	MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
	480	MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
	481	MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
	482	MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
	483	MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
	484	>;
	485	};
	486
d2daa2f7 SG	487	pinctrl_uart1: uart1grp {
	488	fsl,pins = <
	489	MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
	490	MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
	491	>;
	492	};
	493
	494	pinctrl_uart5: uart5grp {
	495	fsl,pins = <
	496	MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
	497	MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
	498	MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
	499	MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
	500	>;
	501	};
	502
960fefff FE	503	pinctrl_usb_otg1: usbotg1grp {
	504	fsl,pins = <
	505	MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
	506	>;
	507	};
	508
	509	pinctrl_usb_otg1_id: usbotg1idgrp {
	510	fsl,pins = <
	511	MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
	512	>;
	513	};
	514
	515	pinctrl_usb_otg2: usbot2ggrp {
	516	fsl,pins = <
	517	MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
	518	>;
	519	};
	520
d2daa2f7 SG	521	pinctrl_usdhc2: usdhc2grp {
	522	fsl,pins = <
	523	MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
	524	MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
	525	MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
	526	MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
	527	MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
	528	MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
	529	>;
	530	};
	531
	532	pinctrl_usdhc3: usdhc3grp {
	533	fsl,pins = <
	534	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
	535	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
	536	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
	537	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
	538	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
	539	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
	540	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
	541	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
	542	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
	543	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
	544	MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
	545	MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
	546	>;
	547	};
	548
	549	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
	550	fsl,pins = <
	551	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
	552	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
	553	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
	554	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
	555	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
	556	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
	557	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
	558	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
	559	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
	560	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
	561	>;
	562	};
	563
	564	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
	565	fsl,pins = <
	566	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
	567	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
	568	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
	569	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
	570	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
	571	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
	572	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
	573	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
	574	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
	575	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
	576	>;
	577	};
	578
	579	pinctrl_usdhc4: usdhc4grp {
	580	fsl,pins = <
	581	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
	582	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
	583	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
	584	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
585	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
586	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
587	MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
588	MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
589	>;
590	};
591	};
592	};