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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / boot / dts / imx6sx.dtsi
CommitLineData
b1d17f68
SG		 1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6sx-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
17 can0 = &flexcan1;
18 can1 = &flexcan2;
19 ethernet0 = &fec1;
20 ethernet1 = &fec2;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 mmc3 = &usdhc4;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 serial5 = &uart6;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
46 spi4 = &ecspi5;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu0: cpu@0 {
56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
58 reg = <0>;
59 next-level-cache = <&L2>;
60 operating-points = <
61 /* kHz uV */
62 996000 1250000
63 792000 1175000
64 396000 1075000
65 >;
66 fsl,soc-operating-points = <
67 /* ARM kHz SOC uV */
68 996000 1175000
69 792000 1175000
70 396000 1175000
71 >;
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <&reg_arm>;
81 soc-supply = <&reg_soc>;
82 };
83 };
84
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 interrupt-controller;
89 reg = <0x00a01000 0x1000>,
90 <0x00a00100 0x100>;
b923ff6a 91 interrupt-parent = <&intc>;
b1d17f68
SG		 92 };
93
94 clocks {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 ckil: clock@0 {
99 compatible = "fixed-clock";
100 reg = <0>;
101 #clock-cells = <0>;
102 clock-frequency = <32768>;
103 clock-output-names = "ckil";
104 };
105
106 osc: clock@1 {
107 compatible = "fixed-clock";
108 reg = <1>;
109 #clock-cells = <0>;
110 clock-frequency = <24000000>;
111 clock-output-names = "osc";
112 };
113
114 ipp_di0: clock@2 {
115 compatible = "fixed-clock";
116 reg = <2>;
117 #clock-cells = <0>;
118 clock-frequency = <0>;
119 clock-output-names = "ipp_di0";
120 };
121
122 ipp_di1: clock@3 {
123 compatible = "fixed-clock";
124 reg = <3>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
127 clock-output-names = "ipp_di1";
128 };
129 };
130
131 soc {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "simple-bus";
b923ff6a 135 interrupt-parent = <&gpc>;
b1d17f68
SG		 136 ranges;
137
138 pmu {
139 compatible = "arm,cortex-a9-pmu";
140 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
141 };
142
143 ocram: sram@00900000 {
144 compatible = "mmio-sram";
145 reg = <0x00900000 0x20000>;
146 clocks = <&clks IMX6SX_CLK_OCRAM>;
147 };
148
149 L2: l2-cache@00a02000 {
150 compatible = "arm,pl310-cache";
151 reg = <0x00a02000 0x1000>;
152 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
153 cache-unified;
154 cache-level = <2>;
155 arm,tag-latency = <4 2 3>;
156 arm,data-latency = <4 2 3>;
157 };
158
159 dma_apbh: dma-apbh@01804000 {
160 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
161 reg = <0x01804000 0x2000>;
162 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
167 #dma-cells = <1>;
168 dma-channels = <4>;
169 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
170 };
171
172 gpmi: gpmi-nand@01806000{
173 compatible = "fsl,imx6sx-gpmi-nand";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
177 reg-names = "gpmi-nand", "bch";
178 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-names = "bch";
180 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
181 <&clks IMX6SX_CLK_GPMI_APB>,
182 <&clks IMX6SX_CLK_GPMI_BCH>,
183 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
184 <&clks IMX6SX_CLK_PER1_BCH>;
185 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
186 "gpmi_bch_apb", "per1_bch";
187 dmas = <&dma_apbh 0>;
188 dma-names = "rx-tx";
189 status = "disabled";
190 };
191
192 aips1: aips-bus@02000000 {
193 compatible = "fsl,aips-bus", "simple-bus";
194 #address-cells = <1>;
195 #size-cells = <1>;
196 reg = <0x02000000 0x100000>;
197 ranges;
198
199 spba-bus@02000000 {
200 compatible = "fsl,spba-bus", "simple-bus";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 reg = <0x02000000 0x40000>;
204 ranges;
205
206 spdif: spdif@02004000 {
207 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
208 reg = <0x02004000 0x4000>;
209 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
210 dmas = <&sdma 14 18 0>,
211 <&sdma 15 18 0>;
212 dma-names = "rx", "tx";
213 clocks = <&clks IMX6SX_CLK_SPDIF>,
214 <&clks IMX6SX_CLK_OSC>,
215 <&clks IMX6SX_CLK_SPDIF>,
216 <&clks 0>, <&clks 0>, <&clks 0>,
217 <&clks IMX6SX_CLK_IPG>,
218 <&clks 0>, <&clks 0>,
219 <&clks IMX6SX_CLK_SPBA>;
220 clock-names = "core", "rxtx0",
221 "rxtx1", "rxtx2",
222 "rxtx3", "rxtx4",
223 "rxtx5", "rxtx6",
224 "rxtx7", "dma";
225 status = "disabled";
226 };
227
228 ecspi1: ecspi@02008000 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
232 reg = <0x02008000 0x4000>;
233 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6SX_CLK_ECSPI1>,
235 <&clks IMX6SX_CLK_ECSPI1>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
239
240 ecspi2: ecspi@0200c000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
244 reg = <0x0200c000 0x4000>;
245 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clks IMX6SX_CLK_ECSPI2>,
247 <&clks IMX6SX_CLK_ECSPI2>;
248 clock-names = "ipg", "per";
249 status = "disabled";
250 };
251
252 ecspi3: ecspi@02010000 {
253 #address-cells = <1>;
254 #size-cells = <0>;
255 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
256 reg = <0x02010000 0x4000>;
257 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clks IMX6SX_CLK_ECSPI3>,
259 <&clks IMX6SX_CLK_ECSPI3>;
260 clock-names = "ipg", "per";
261 status = "disabled";
262 };
263
264 ecspi4: ecspi@02014000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
268 reg = <0x02014000 0x4000>;
269 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clks IMX6SX_CLK_ECSPI4>,
271 <&clks IMX6SX_CLK_ECSPI4>;
272 clock-names = "ipg", "per";
273 status = "disabled";
274 };
275
276 uart1: serial@02020000 {
277 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
278 reg = <0x02020000 0x4000>;
279 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6SX_CLK_UART_IPG>,
281 <&clks IMX6SX_CLK_UART_SERIAL>;
282 clock-names = "ipg", "per";
283 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
284 dma-names = "rx", "tx";
285 status = "disabled";
286 };
287
288 esai: esai@02024000 {
289 reg = <0x02024000 0x4000>;
290 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
292 <&clks IMX6SX_CLK_ESAI_MEM>,
293 <&clks IMX6SX_CLK_ESAI_EXTAL>,
294 <&clks IMX6SX_CLK_ESAI_IPG>,
295 <&clks IMX6SX_CLK_SPBA>;
296 clock-names = "core", "mem", "extal",
297 "fsys", "dma";
298 status = "disabled";
299 };
300
301 ssi1: ssi@02028000 {
6ff7f51e 302 #sound-dai-cells = <0>;
4c03527e 303 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
b1d17f68
SG		 304 reg = <0x02028000 0x4000>;
305 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
307 <&clks IMX6SX_CLK_SSI1>;
308 clock-names = "ipg", "baud";
309 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
310 dma-names = "rx", "tx";
3a462a62 311 fsl,fifo-depth = <15>;
b1d17f68
SG		 312 status = "disabled";
313 };
314
315 ssi2: ssi@0202c000 {
6ff7f51e 316 #sound-dai-cells = <0>;
4c03527e 317 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
b1d17f68
SG		 318 reg = <0x0202c000 0x4000>;
319 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
321 <&clks IMX6SX_CLK_SSI2>;
322 clock-names = "ipg", "baud";
323 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
324 dma-names = "rx", "tx";
3a462a62 325 fsl,fifo-depth = <15>;
b1d17f68
SG		 326 status = "disabled";
327 };
328
329 ssi3: ssi@02030000 {
6ff7f51e 330 #sound-dai-cells = <0>;
4c03527e 331 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
b1d17f68
SG		 332 reg = <0x02030000 0x4000>;
333 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
335 <&clks IMX6SX_CLK_SSI3>;
336 clock-names = "ipg", "baud";
337 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
338 dma-names = "rx", "tx";
3a462a62 339 fsl,fifo-depth = <15>;
b1d17f68
SG		 340 status = "disabled";
341 };
342
343 asrc: asrc@02034000 {
344 reg = <0x02034000 0x4000>;
345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
347 <&clks IMX6SX_CLK_ASRC_IPG>,
348 <&clks IMX6SX_CLK_SPDIF>,
349 <&clks IMX6SX_CLK_SPBA>;
350 clock-names = "mem", "ipg", "asrck", "dma";
351 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
352 <&sdma 19 20 1>, <&sdma 20 20 1>,
353 <&sdma 21 20 1>, <&sdma 22 20 1>;
354 dma-names = "rxa", "rxb", "rxc",
355 "txa", "txb", "txc";
356 status = "okay";
357 };
358 };
359
360 pwm1: pwm@02080000 {
361 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
362 reg = <0x02080000 0x4000>;
363 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6SX_CLK_PWM1>,
365 <&clks IMX6SX_CLK_PWM1>;
366 clock-names = "ipg", "per";
367 #pwm-cells = <2>;
368 };
369
370 pwm2: pwm@02084000 {
371 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
372 reg = <0x02084000 0x4000>;
373 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6SX_CLK_PWM2>,
375 <&clks IMX6SX_CLK_PWM2>;
376 clock-names = "ipg", "per";
377 #pwm-cells = <2>;
378 };
379
380 pwm3: pwm@02088000 {
381 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
382 reg = <0x02088000 0x4000>;
383 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clks IMX6SX_CLK_PWM3>,
385 <&clks IMX6SX_CLK_PWM3>;
386 clock-names = "ipg", "per";
387 #pwm-cells = <2>;
388 };
389
390 pwm4: pwm@0208c000 {
391 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
392 reg = <0x0208c000 0x4000>;
393 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX6SX_CLK_PWM4>,
395 <&clks IMX6SX_CLK_PWM4>;
396 clock-names = "ipg", "per";
397 #pwm-cells = <2>;
398 };
399
400 flexcan1: can@02090000 {
401 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
402 reg = <0x02090000 0x4000>;
403 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
405 <&clks IMX6SX_CLK_CAN1_SERIAL>;
406 clock-names = "ipg", "per";
407 status = "disabled";
408 };
409
410 flexcan2: can@02094000 {
411 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
412 reg = <0x02094000 0x4000>;
413 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
415 <&clks IMX6SX_CLK_CAN2_SERIAL>;
416 clock-names = "ipg", "per";
417 status = "disabled";
418 };
419
420 gpt: gpt@02098000 {
421 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
422 reg = <0x02098000 0x4000>;
423 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
2b2244a3 425 <&clks IMX6SX_CLK_GPT_3M>;
b1d17f68
SG		 426 clock-names = "ipg", "per";
427 };
428
429 gpio1: gpio@0209c000 {
430 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
431 reg = <0x0209c000 0x4000>;
432 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
434 gpio-controller;
435 #gpio-cells = <2>;
436 interrupt-controller;
437 #interrupt-cells = <2>;
438 };
439
440 gpio2: gpio@020a0000 {
441 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
442 reg = <0x020a0000 0x4000>;
443 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 };
450
451 gpio3: gpio@020a4000 {
452 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
453 reg = <0x020a4000 0x4000>;
454 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
456 gpio-controller;
457 #gpio-cells = <2>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 };
461
462 gpio4: gpio@020a8000 {
463 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
464 reg = <0x020a8000 0x4000>;
465 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 };
472
473 gpio5: gpio@020ac000 {
474 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
475 reg = <0x020ac000 0x4000>;
476 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
478 gpio-controller;
479 #gpio-cells = <2>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
482 };
483
484 gpio6: gpio@020b0000 {
485 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
486 reg = <0x020b0000 0x4000>;
487 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 };
494
495 gpio7: gpio@020b4000 {
496 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
497 reg = <0x020b4000 0x4000>;
498 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
500 gpio-controller;
501 #gpio-cells = <2>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
504 };
505
506 kpp: kpp@020b8000 {
507 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
508 reg = <0x020b8000 0x4000>;
509 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clks IMX6SX_CLK_DUMMY>;
511 status = "disabled";
512 };
513
514 wdog1: wdog@020bc000 {
515 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
516 reg = <0x020bc000 0x4000>;
517 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6SX_CLK_DUMMY>;
519 };
520
521 wdog2: wdog@020c0000 {
522 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
523 reg = <0x020c0000 0x4000>;
524 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clks IMX6SX_CLK_DUMMY>;
526 status = "disabled";
527 };
528
529 clks: ccm@020c4000 {
530 compatible = "fsl,imx6sx-ccm";
531 reg = <0x020c4000 0x4000>;
532 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
534 #clock-cells = <1>;
535 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
536 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
537 };
538
539 anatop: anatop@020c8000 {
540 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
541 "syscon", "simple-bus";
542 reg = <0x020c8000 0x1000>;
543 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
546
547 regulator-1p1@110 {
548 compatible = "fsl,anatop-regulator";
549 regulator-name = "vdd1p1";
550 regulator-min-microvolt = <800000>;
551 regulator-max-microvolt = <1375000>;
552 regulator-always-on;
553 anatop-reg-offset = <0x110>;
554 anatop-vol-bit-shift = <8>;
555 anatop-vol-bit-width = <5>;
556 anatop-min-bit-val = <4>;
557 anatop-min-voltage = <800000>;
558 anatop-max-voltage = <1375000>;
559 };
560
561 regulator-3p0@120 {
562 compatible = "fsl,anatop-regulator";
563 regulator-name = "vdd3p0";
564 regulator-min-microvolt = <2800000>;
565 regulator-max-microvolt = <3150000>;
566 regulator-always-on;
567 anatop-reg-offset = <0x120>;
568 anatop-vol-bit-shift = <8>;
569 anatop-vol-bit-width = <5>;
570 anatop-min-bit-val = <0>;
571 anatop-min-voltage = <2625000>;
572 anatop-max-voltage = <3400000>;
573 };
574
575 regulator-2p5@130 {
576 compatible = "fsl,anatop-regulator";
577 regulator-name = "vdd2p5";
578 regulator-min-microvolt = <2100000>;
579 regulator-max-microvolt = <2875000>;
580 regulator-always-on;
581 anatop-reg-offset = <0x130>;
582 anatop-vol-bit-shift = <8>;
583 anatop-vol-bit-width = <5>;
584 anatop-min-bit-val = <0>;
585 anatop-min-voltage = <2100000>;
586 anatop-max-voltage = <2875000>;
587 };
588
589 reg_arm: regulator-vddcore@140 {
590 compatible = "fsl,anatop-regulator";
f78a5975 591 regulator-name = "vddarm";
b1d17f68
SG		 592 regulator-min-microvolt = <725000>;
593 regulator-max-microvolt = <1450000>;
594 regulator-always-on;
595 anatop-reg-offset = <0x140>;
596 anatop-vol-bit-shift = <0>;
597 anatop-vol-bit-width = <5>;
598 anatop-delay-reg-offset = <0x170>;
599 anatop-delay-bit-shift = <24>;
600 anatop-delay-bit-width = <2>;
601 anatop-min-bit-val = <1>;
602 anatop-min-voltage = <725000>;
603 anatop-max-voltage = <1450000>;
604 };
605
606 reg_pcie: regulator-vddpcie@140 {
607 compatible = "fsl,anatop-regulator";
608 regulator-name = "vddpcie";
609 regulator-min-microvolt = <725000>;
610 regulator-max-microvolt = <1450000>;
611 anatop-reg-offset = <0x140>;
612 anatop-vol-bit-shift = <9>;
613 anatop-vol-bit-width = <5>;
614 anatop-delay-reg-offset = <0x170>;
615 anatop-delay-bit-shift = <26>;
616 anatop-delay-bit-width = <2>;
617 anatop-min-bit-val = <1>;
618 anatop-min-voltage = <725000>;
619 anatop-max-voltage = <1450000>;
620 };
621
622 reg_soc: regulator-vddsoc@140 {
623 compatible = "fsl,anatop-regulator";
624 regulator-name = "vddsoc";
625 regulator-min-microvolt = <725000>;
626 regulator-max-microvolt = <1450000>;
627 regulator-always-on;
628 anatop-reg-offset = <0x140>;
629 anatop-vol-bit-shift = <18>;
630 anatop-vol-bit-width = <5>;
631 anatop-delay-reg-offset = <0x170>;
632 anatop-delay-bit-shift = <28>;
633 anatop-delay-bit-width = <2>;
634 anatop-min-bit-val = <1>;
635 anatop-min-voltage = <725000>;
636 anatop-max-voltage = <1450000>;
637 };
638 };
639
640 tempmon: tempmon {
641 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
642 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
643 fsl,tempmon = <&anatop>;
644 fsl,tempmon-data = <&ocotp>;
645 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
646 };
647
648 usbphy1: usbphy@020c9000 {
649 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
650 reg = <0x020c9000 0x1000>;
651 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&clks IMX6SX_CLK_USBPHY1>;
653 fsl,anatop = <&anatop>;
654 };
655
656 usbphy2: usbphy@020ca000 {
657 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
658 reg = <0x020ca000 0x1000>;
659 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&clks IMX6SX_CLK_USBPHY2>;
661 fsl,anatop = <&anatop>;
662 };
663
664 snvs: snvs@020cc000 {
665 compatible = "fsl,sec-v4.0-mon", "simple-bus";
666 #address-cells = <1>;
667 #size-cells = <1>;
668 ranges = <0 0x020cc000 0x4000>;
669
6f9dbfda 670 snvs_rtc: snvs-rtc-lp@34 {
b1d17f68
SG		 671 compatible = "fsl,sec-v4.0-mon-rtc-lp";
672 reg = <0x34 0x58>;
673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
674 };
422b0676
RG		 675
676 snvs_poweroff: snvs-poweroff@38 {
677 compatible = "fsl,sec-v4.0-poweroff";
678 reg = <0x38 0x4>;
679 status = "disabled";
680 };
b1d17f68
SG		 681 };
682
683 epit1: epit@020d0000 {
684 reg = <0x020d0000 0x4000>;
685 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
686 };
687
688 epit2: epit@020d4000 {
689 reg = <0x020d4000 0x4000>;
690 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
691 };
692
693 src: src@020d8000 {
694 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
695 reg = <0x020d8000 0x4000>;
696 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
698 #reset-cells = <1>;
699 };
700
701 gpc: gpc@020dc000 {
702 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
703 reg = <0x020dc000 0x4000>;
b923ff6a
MZ		 704 interrupt-controller;
705 #interrupt-cells = <3>;
b1d17f68 706 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
b923ff6a 707 interrupt-parent = <&intc>;
b1d17f68
SG		 708 };
709
710 iomuxc: iomuxc@020e0000 {
711 compatible = "fsl,imx6sx-iomuxc";
712 reg = <0x020e0000 0x4000>;
713 };
714
715 gpr: iomuxc-gpr@020e4000 {
77e0d1cc
AH		 716 compatible = "fsl,imx6sx-iomuxc-gpr",
717 "fsl,imx6q-iomuxc-gpr", "syscon";
b1d17f68
SG		 718 reg = <0x020e4000 0x4000>;
719 };
720
721 sdma: sdma@020ec000 {
811e7685 722 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
b1d17f68
SG		 723 reg = <0x020ec000 0x4000>;
724 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX6SX_CLK_SDMA>,
726 <&clks IMX6SX_CLK_SDMA>;
727 clock-names = "ipg", "ahb";
728 #dma-cells = <3>;
aeb88538
FE		 729 /* imx6sx reuses imx6q sdma firmware */
730 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
b1d17f68
SG		 731 };
732 };
733
734 aips2: aips-bus@02100000 {
735 compatible = "fsl,aips-bus", "simple-bus";
736 #address-cells = <1>;
737 #size-cells = <1>;
738 reg = <0x02100000 0x100000>;
739 ranges;
740
b15e9ea5
VM		 741 crypto: caam@2100000 {
742 compatible = "fsl,sec-v4.0";
743 fsl,sec-era = <4>;
744 #address-cells = <1>;
745 #size-cells = <1>;
746 reg = <0x2100000 0x10000>;
747 ranges = <0 0x2100000 0x10000>;
748 interrupt-parent = <&intc>;
749 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
750 <&clks IMX6SX_CLK_CAAM_ACLK>,
751 <&clks IMX6SX_CLK_CAAM_IPG>,
752 <&clks IMX6SX_CLK_EIM_SLOW>;
753 clock-names = "mem", "aclk", "ipg", "emi_slow";
754
755 sec_jr0: jr0@1000 {
756 compatible = "fsl,sec-v4.0-job-ring";
757 reg = <0x1000 0x1000>;
758 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
759 };
760
761 sec_jr1: jr1@2000 {
762 compatible = "fsl,sec-v4.0-job-ring";
763 reg = <0x2000 0x1000>;
764 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
765 };
766 };
767
b1d17f68
SG		 768 usbotg1: usb@02184000 {
769 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
770 reg = <0x02184000 0x200>;
771 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clks IMX6SX_CLK_USBOH3>;
773 fsl,usbphy = <&usbphy1>;
774 fsl,usbmisc = <&usbmisc 0>;
775 fsl,anatop = <&anatop>;
776 status = "disabled";
777 };
778
779 usbotg2: usb@02184200 {
780 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
781 reg = <0x02184200 0x200>;
782 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&clks IMX6SX_CLK_USBOH3>;
784 fsl,usbphy = <&usbphy2>;
785 fsl,usbmisc = <&usbmisc 1>;
786 status = "disabled";
787 };
788
789 usbh: usb@02184400 {
790 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
791 reg = <0x02184400 0x200>;
792 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clks IMX6SX_CLK_USBOH3>;
794 fsl,usbmisc = <&usbmisc 2>;
795 phy_type = "hsic";
796 fsl,anatop = <&anatop>;
3ec481ed 797 dr_mode = "host";
b1d17f68
SG		 798 status = "disabled";
799 };
800
801 usbmisc: usbmisc@02184800 {
802 #index-cells = <1>;
b29f4fa1 803 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
b1d17f68
SG		 804 reg = <0x02184800 0x200>;
805 clocks = <&clks IMX6SX_CLK_USBOH3>;
806 };
807
808 fec1: ethernet@02188000 {
809 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
810 reg = <0x02188000 0x4000>;
811 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clks IMX6SX_CLK_ENET>,
814 <&clks IMX6SX_CLK_ENET_AHB>,
815 <&clks IMX6SX_CLK_ENET_PTP>,
816 <&clks IMX6SX_CLK_ENET_REF>,
817 <&clks IMX6SX_CLK_ENET_PTP>;
818 clock-names = "ipg", "ahb", "ptp",
819 "enet_clk_ref", "enet_out";
0afdfe95
FL		 820 fsl,num-tx-queues=<3>;
821 fsl,num-rx-queues=<3>;
b1d17f68
SG		 822 status = "disabled";
823 };
824
825 mlb: mlb@0218c000 {
826 reg = <0x0218c000 0x4000>;
827 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clks IMX6SX_CLK_MLB>;
831 status = "disabled";
832 };
833
834 usdhc1: usdhc@02190000 {
835 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
836 reg = <0x02190000 0x4000>;
837 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&clks IMX6SX_CLK_USDHC1>,
839 <&clks IMX6SX_CLK_USDHC1>,
840 <&clks IMX6SX_CLK_USDHC1>;
841 clock-names = "ipg", "ahb", "per";
842 bus-width = <4>;
843 status = "disabled";
844 };
845
846 usdhc2: usdhc@02194000 {
847 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
848 reg = <0x02194000 0x4000>;
849 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clks IMX6SX_CLK_USDHC2>,
851 <&clks IMX6SX_CLK_USDHC2>,
852 <&clks IMX6SX_CLK_USDHC2>;
853 clock-names = "ipg", "ahb", "per";
854 bus-width = <4>;
855 status = "disabled";
856 };
857
858 usdhc3: usdhc@02198000 {
859 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
860 reg = <0x02198000 0x4000>;
861 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&clks IMX6SX_CLK_USDHC3>,
863 <&clks IMX6SX_CLK_USDHC3>,
864 <&clks IMX6SX_CLK_USDHC3>;
865 clock-names = "ipg", "ahb", "per";
866 bus-width = <4>;
867 status = "disabled";
868 };
869
870 usdhc4: usdhc@0219c000 {
871 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
872 reg = <0x0219c000 0x4000>;
873 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&clks IMX6SX_CLK_USDHC4>,
875 <&clks IMX6SX_CLK_USDHC4>,
876 <&clks IMX6SX_CLK_USDHC4>;
877 clock-names = "ipg", "ahb", "per";
878 bus-width = <4>;
879 status = "disabled";
880 };
881
882 i2c1: i2c@021a0000 {
883 #address-cells = <1>;
884 #size-cells = <0>;
885 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
886 reg = <0x021a0000 0x4000>;
887 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clks IMX6SX_CLK_I2C1>;
889 status = "disabled";
890 };
891
892 i2c2: i2c@021a4000 {
893 #address-cells = <1>;
894 #size-cells = <0>;
895 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
896 reg = <0x021a4000 0x4000>;
897 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX6SX_CLK_I2C2>;
899 status = "disabled";
900 };
901
902 i2c3: i2c@021a8000 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
906 reg = <0x021a8000 0x4000>;
907 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks IMX6SX_CLK_I2C3>;
909 status = "disabled";
910 };
911
912 mmdc: mmdc@021b0000 {
913 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
914 reg = <0x021b0000 0x4000>;
915 };
916
917 fec2: ethernet@021b4000 {
9863aba5 918 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
b1d17f68
SG		 919 reg = <0x021b4000 0x4000>;
920 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&clks IMX6SX_CLK_ENET>,
923 <&clks IMX6SX_CLK_ENET_AHB>,
924 <&clks IMX6SX_CLK_ENET_PTP>,
925 <&clks IMX6SX_CLK_ENET2_REF_125M>,
926 <&clks IMX6SX_CLK_ENET_PTP>;
927 clock-names = "ipg", "ahb", "ptp",
928 "enet_clk_ref", "enet_out";
929 status = "disabled";
930 };
931
932 weim: weim@021b8000 {
933 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
934 reg = <0x021b8000 0x4000>;
935 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
937 };
938
939 ocotp: ocotp@021bc000 {
940 compatible = "fsl,imx6sx-ocotp", "syscon";
941 reg = <0x021bc000 0x4000>;
942 clocks = <&clks IMX6SX_CLK_OCOTP>;
943 };
944
945 sai1: sai@021d4000 {
946 compatible = "fsl,imx6sx-sai";
947 reg = <0x021d4000 0x4000>;
948 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
950 <&clks IMX6SX_CLK_SAI1>,
951 <&clks 0>, <&clks 0>;
952 clock-names = "bus", "mclk1", "mclk2", "mclk3";
953 dma-names = "rx", "tx";
954 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
955 dma-source = <&gpr 0 15 0 16>;
956 status = "disabled";
957 };
958
959 audmux: audmux@021d8000 {
960 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
961 reg = <0x021d8000 0x4000>;
962 status = "disabled";
963 };
964
965 sai2: sai@021dc000 {
966 compatible = "fsl,imx6sx-sai";
967 reg = <0x021dc000 0x4000>;
968 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
970 <&clks IMX6SX_CLK_SAI2>,
971 <&clks 0>, <&clks 0>;
972 clock-names = "bus", "mclk1", "mclk2", "mclk3";
973 dma-names = "rx", "tx";
974 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
975 dma-source = <&gpr 0 17 0 18>;
976 status = "disabled";
977 };
978
979 qspi1: qspi@021e0000 {
980 #address-cells = <1>;
981 #size-cells = <0>;
982 compatible = "fsl,imx6sx-qspi";
983 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
984 reg-names = "QuadSPI", "QuadSPI-memory";
985 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&clks IMX6SX_CLK_QSPI1>,
987 <&clks IMX6SX_CLK_QSPI1>;
988 clock-names = "qspi_en", "qspi";
989 status = "disabled";
990 };
991
992 qspi2: qspi@021e4000 {
993 #address-cells = <1>;
994 #size-cells = <0>;
995 compatible = "fsl,imx6sx-qspi";
996 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
997 reg-names = "QuadSPI", "QuadSPI-memory";
998 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks IMX6SX_CLK_QSPI2>,
1000 <&clks IMX6SX_CLK_QSPI2>;
1001 clock-names = "qspi_en", "qspi";
1002 status = "disabled";
1003 };
1004
1005 uart2: serial@021e8000 {
1006 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1007 reg = <0x021e8000 0x4000>;
1008 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1010 <&clks IMX6SX_CLK_UART_SERIAL>;
1011 clock-names = "ipg", "per";
1012 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1013 dma-names = "rx", "tx";
1014 status = "disabled";
1015 };
1016
1017 uart3: serial@021ec000 {
1018 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1019 reg = <0x021ec000 0x4000>;
1020 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1022 <&clks IMX6SX_CLK_UART_SERIAL>;
1023 clock-names = "ipg", "per";
1024 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1025 dma-names = "rx", "tx";
1026 status = "disabled";
1027 };
1028
1029 uart4: serial@021f0000 {
1030 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1031 reg = <0x021f0000 0x4000>;
1032 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1034 <&clks IMX6SX_CLK_UART_SERIAL>;
1035 clock-names = "ipg", "per";
1036 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1037 dma-names = "rx", "tx";
1038 status = "disabled";
1039 };
1040
1041 uart5: serial@021f4000 {
1042 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1043 reg = <0x021f4000 0x4000>;
1044 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1046 <&clks IMX6SX_CLK_UART_SERIAL>;
1047 clock-names = "ipg", "per";
1048 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1049 dma-names = "rx", "tx";
1050 status = "disabled";
1051 };
1052
1053 i2c4: i2c@021f8000 {
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1057 reg = <0x021f8000 0x4000>;
1058 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX6SX_CLK_I2C4>;
1060 status = "disabled";
1061 };
1062 };
1063
1064 aips3: aips-bus@02200000 {
1065 compatible = "fsl,aips-bus", "simple-bus";
1066 #address-cells = <1>;
1067 #size-cells = <1>;
1068 reg = <0x02200000 0x100000>;
1069 ranges;
1070
1071 spba-bus@02200000 {
1072 compatible = "fsl,spba-bus", "simple-bus";
1073 #address-cells = <1>;
1074 #size-cells = <1>;
1075 reg = <0x02240000 0x40000>;
1076 ranges;
1077
1078 csi1: csi@02214000 {
1079 reg = <0x02214000 0x4000>;
1080 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1082 <&clks IMX6SX_CLK_CSI>,
1083 <&clks IMX6SX_CLK_DCIC1>;
1084 clock-names = "disp-axi", "csi_mclk", "dcic";
1085 status = "disabled";
1086 };
1087
1088 pxp: pxp@02218000 {
1089 reg = <0x02218000 0x4000>;
1090 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1092 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1093 clock-names = "pxp-axi", "disp-axi";
1094 status = "disabled";
1095 };
1096
1097 csi2: csi@0221c000 {
1098 reg = <0x0221c000 0x4000>;
1099 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1101 <&clks IMX6SX_CLK_CSI>,
1102 <&clks IMX6SX_CLK_DCIC2>;
1103 clock-names = "disp-axi", "csi_mclk", "dcic";
1104 status = "disabled";
1105 };
1106
1107 lcdif1: lcdif@02220000 {
8c78c407 1108 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
b1d17f68
SG		 1109 reg = <0x02220000 0x4000>;
1110 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1112 <&clks IMX6SX_CLK_LCDIF_APB>,
1113 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1114 clock-names = "pix", "axi", "disp_axi";
1115 status = "disabled";
1116 };
1117
1118 lcdif2: lcdif@02224000 {
8c78c407 1119 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
b1d17f68
SG		 1120 reg = <0x02224000 0x4000>;
1121 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1122 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1123 <&clks IMX6SX_CLK_LCDIF_APB>,
1124 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1125 clock-names = "pix", "axi", "disp_axi";
1126 status = "disabled";
1127 };
1128
1129 vadc: vadc@02228000 {
1130 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1131 reg-names = "vadc-vafe", "vadc-vdec";
1132 clocks = <&clks IMX6SX_CLK_VADC>,
1133 <&clks IMX6SX_CLK_CSI>;
1134 clock-names = "vadc", "csi";
1135 status = "disabled";
1136 };
1137 };
1138
1139 adc1: adc@02280000 {
1140 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1141 reg = <0x02280000 0x4000>;
1142 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&clks IMX6SX_CLK_IPG>;
1144 clock-names = "adc";
1145 status = "disabled";
1146 };
1147
1148 adc2: adc@02284000 {
1149 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1150 reg = <0x02284000 0x4000>;
1151 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&clks IMX6SX_CLK_IPG>;
1153 clock-names = "adc";
1154 status = "disabled";
1155 };
1156
1157 wdog3: wdog@02288000 {
1158 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1159 reg = <0x02288000 0x4000>;
1160 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&clks IMX6SX_CLK_DUMMY>;
1162 status = "disabled";
1163 };
1164
1165 ecspi5: ecspi@0228c000 {
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1169 reg = <0x0228c000 0x4000>;
1170 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1172 <&clks IMX6SX_CLK_ECSPI5>;
1173 clock-names = "ipg", "per";
1174 status = "disabled";
1175 };
1176
1177 uart6: serial@022a0000 {
1178 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1179 reg = <0x022a0000 0x4000>;
1180 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1182 <&clks IMX6SX_CLK_UART_SERIAL>;
1183 clock-names = "ipg", "per";
1184 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1185 dma-names = "rx", "tx";
1186 status = "disabled";
1187 };
1188
1189 pwm5: pwm@022a4000 {
1190 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1191 reg = <0x022a4000 0x4000>;
1192 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_PWM5>,
1194 <&clks IMX6SX_CLK_PWM5>;
1195 clock-names = "ipg", "per";
1196 #pwm-cells = <2>;
1197 };
1198
1199 pwm6: pwm@022a8000 {
1200 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1201 reg = <0x022a8000 0x4000>;
1202 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX6SX_CLK_PWM6>,
1204 <&clks IMX6SX_CLK_PWM6>;
1205 clock-names = "ipg", "per";
1206 #pwm-cells = <2>;
1207 };
1208
1209 pwm7: pwm@022ac000 {
1210 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1211 reg = <0x022ac000 0x4000>;
1212 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clks IMX6SX_CLK_PWM7>,
1214 <&clks IMX6SX_CLK_PWM7>;
1215 clock-names = "ipg", "per";
1216 #pwm-cells = <2>;
1217 };
1218
1219 pwm8: pwm@0022b0000 {
1220 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1221 reg = <0x0022b0000 0x4000>;
1222 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clks IMX6SX_CLK_PWM8>,
1224 <&clks IMX6SX_CLK_PWM8>;
1225 clock-names = "ipg", "per";
1226 #pwm-cells = <2>;
1227 };
1228 };
1229
1230 pcie: pcie@0x08000000 {
1231 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1232 reg = <0x08ffc000 0x4000>; /* DBI */
1233 #address-cells = <3>;
1234 #size-cells = <2>;
1235 device_type = "pci";
1236 /* configuration space */
1237 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1238 /* downstream I/O */
1239 0x81000000 0 0 0x08f80000 0 0x00010000
1240 /* non-prefetchable memory */
1241 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1242 num-lanes = <1>;
1243 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1245 <&clks IMX6SX_CLK_PCIE_AXI>,
1246 <&clks IMX6SX_CLK_LVDS1_OUT>,
1247 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1248 clock-names = "pcie_ref_125m", "pcie_axi",
1249 "lvds_gate", "display_axi";
1250 status = "disabled";
1251 };
1252 };
1253};
Linux kernel - Deliverables
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