[deliverable/linux.git] / arch / arm / boot / dts / imx6ul-14x14-evk.dts

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"

/ {
	model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
	compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";

	chosen {
		stdout-path = &uart1;
	};

	memory {
		reg = <0x80000000 0x20000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_sd1_vmmc: sd1_regulator {
			compatible = "regulator-fixed";
			regulator-name = "VSD_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};
};

&cpu0 {
	arm-supply = <&reg_arm>;
	soc-supply = <&reg_soc>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	enable-sdio-wakeup;
	vmmc-supply = <&reg_sd1_vmmc>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	keep-power-in-suspend;
	enable-sdio-wakeup;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_csi1: csi1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
			MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
			MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
			MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
			MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
			MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
			MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
			MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
			MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
			MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
			MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
			MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x17059
		>;
	};

	pinctrl_flexcan1: flexcan1grp{
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp{
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
			/* used for lcd reset */
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
		>;
	};

	pinctrl_sim2: sim2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0xb808
			MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x31
			MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0xb808
			MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0xb808
			MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0xb809
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x3008
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9

		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
		>;
	};
};
Commit	Line	Data
a5fcccbc FL	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/dts-v1/;
	10
	11	#include <dt-bindings/input/input.h>
	12	#include "imx6ul.dtsi"
	13
	14	/ {
	15	model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
	16	compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
	17
	18	chosen {
	19	stdout-path = &uart1;
	20	};
	21
	22	memory {
	23	reg = <0x80000000 0x20000000>;
	24	};
	25
	26	regulators {
	27	compatible = "simple-bus";
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	reg_sd1_vmmc: sd1_regulator {
	32	compatible = "regulator-fixed";
	33	regulator-name = "VSD_3V3";
	34	regulator-min-microvolt = <3300000>;
	35	regulator-max-microvolt = <3300000>;
	36	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	37	enable-active-high;
	38	};
	39	};
	40	};
	41
	42	&cpu0 {
	43	arm-supply = <&reg_arm>;
	44	soc-supply = <&reg_soc>;
	45	};
	46
	47	&uart1 {
	48	pinctrl-names = "default";
	49	pinctrl-0 = <&pinctrl_uart1>;
	50	status = "okay";
	51	};
	52
	53	&uart2 {
	54	pinctrl-names = "default";
	55	pinctrl-0 = <&pinctrl_uart2>;
	56	fsl,uart-has-rtscts;
	57	status = "okay";
	58	};
	59
cad2cb69 FL	60	&usbotg1 {
	61	dr_mode = "peripheral";
	62	status = "okay";
	63	};
	64
	65	&usbotg2 {
	66	dr_mode = "host";
	67	disable-over-current;
	68	status = "okay";
	69	};
	70
a5fcccbc FL	71	&usdhc1 {
	72	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	73	pinctrl-0 = <&pinctrl_usdhc1>;
	74	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	75	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	76	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	77	keep-power-in-suspend;
	78	enable-sdio-wakeup;
	79	vmmc-supply = <&reg_sd1_vmmc>;
	80	status = "okay";
	81	};
	82
	83	&usdhc2 {
	84	pinctrl-names = "default";
	85	pinctrl-0 = <&pinctrl_usdhc2>;
	86	no-1-8-v;
	87	keep-power-in-suspend;
	88	enable-sdio-wakeup;
	89	status = "okay";
	90	};
	91
	92	&iomuxc {
	93	pinctrl-names = "default";
	94
	95	pinctrl_csi1: csi1grp {
	96	fsl,pins = <
	97	MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
	98	MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
	99	MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
	100	MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
	101	MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
	102	MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
	103	MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
	104	MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
	105	MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
	106	MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
	107	MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
	108	MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
	109	>;
	110	};
	111
	112	pinctrl_enet1: enet1grp {
	113	fsl,pins = <
	114	MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
	115	MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
	116	MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
	117	MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
	118	MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
	119	MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
	120	MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
	121	MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
	122	>;
	123	};
	124
	125	pinctrl_enet2: enet2grp {
	126	fsl,pins = <
	127	MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
	128	MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
	129	MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
	130	MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
	131	MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
	132	MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
	133	MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
	134	MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
135	MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
136	MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
137	MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
138	>;
139	};
140
141	pinctrl_flexcan1: flexcan1grp{
142	fsl,pins = <
143	MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
144	MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
145	>;
146	};
147
148	pinctrl_flexcan2: flexcan2grp{
149	fsl,pins = <
150	MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
151	MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
152	>;
153	};
154
155	pinctrl_i2c1: i2c1grp {
156	fsl,pins = <
157	MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
158	MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
159	>;
160	};
161
162	pinctrl_i2c2: i2c2grp {
163	fsl,pins = <
164	MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
165	MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
166	>;
167	};
168
169	pinctrl_lcdif_dat: lcdifdatgrp {
170	fsl,pins = <
171	MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
172	MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
173	MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
174	MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
175	MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
176	MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
177	MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
178	MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
179	MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
180	MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
181	MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
182	MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
183	MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
184	MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
185	MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
186	MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
187	MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
188	MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
189	MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
190	MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
191	MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
192	MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
193	MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
194	MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
195	>;
196	};
197
198	pinctrl_lcdif_ctrl: lcdifctrlgrp {
199	fsl,pins = <
200	MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
201	MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
202	MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
203	MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
204	/* used for lcd reset */
205	MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
206	>;
207	};
208
209	pinctrl_pwm1: pwm1grp {
210	fsl,pins = <
211	MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
212	>;
213	};
214
215	pinctrl_sim2: sim2grp {
216	fsl,pins = <
217	MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
218	MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
219	MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
220	MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
221	MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
222	MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
223	>;
224	};
225
226	pinctrl_uart1: uart1grp {
227	fsl,pins = <
228	MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
229	MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
230	>;
231	};
232
233	pinctrl_uart2: uart2grp {
234	fsl,pins = <
235	MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
236	MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
237	MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
238	MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
239	>;
240	};
241
242	pinctrl_usdhc1: usdhc1grp {
243	fsl,pins = <
244	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
245	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
246	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
247	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
248	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
249	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
250	MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
251	MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
252	MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
253	>;
254	};
255
256	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
257	fsl,pins = <
258	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
259	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
260	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
261	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
262	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
263	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
264
265	>;
266	};
267
268	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
269	fsl,pins = <
270	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
271	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
272	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
273	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
274	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
275	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
276	>;
277	};
278
279	pinctrl_usdhc2: usdhc2grp {
280	fsl,pins = <
281	MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
282	MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
283	MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
284	MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
285	MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
286	MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
287	>;
288	};
289	};