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a5fcccbc FL |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/clock/imx6ul-clock.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
12 | #include "imx6ul-pinfunc.h" | |
13 | #include "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
17 | gpio0 = &gpio1; | |
18 | gpio1 = &gpio2; | |
19 | gpio2 = &gpio3; | |
20 | gpio3 = &gpio4; | |
21 | gpio4 = &gpio5; | |
22 | i2c0 = &i2c1; | |
23 | i2c1 = &i2c2; | |
24 | i2c2 = &i2c3; | |
25 | i2c3 = &i2c4; | |
26 | mmc0 = &usdhc1; | |
27 | mmc1 = &usdhc2; | |
28 | serial0 = &uart1; | |
29 | serial1 = &uart2; | |
30 | serial2 = &uart3; | |
31 | serial3 = &uart4; | |
32 | serial4 = &uart5; | |
33 | serial5 = &uart6; | |
34 | serial6 = &uart7; | |
35 | serial7 = &uart8; | |
36 | spi0 = &ecspi1; | |
37 | spi1 = &ecspi2; | |
38 | spi2 = &ecspi3; | |
39 | spi3 = &ecspi4; | |
40 | usbphy0 = &usbphy1; | |
41 | usbphy1 = &usbphy2; | |
42 | }; | |
43 | ||
44 | cpus { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <0>; | |
47 | ||
48 | cpu0: cpu@0 { | |
49 | compatible = "arm,cortex-a7"; | |
50 | device_type = "cpu"; | |
51 | reg = <0>; | |
52 | clock-latency = <61036>; /* two CLK32 periods */ | |
53 | operating-points = < | |
54 | /* kHz uV */ | |
55 | 528000 1250000 | |
56 | 396000 1150000 | |
57 | 198000 1150000 | |
58 | >; | |
59 | fsl,soc-operating-points = < | |
60 | /* KHz uV */ | |
61 | 528000 1250000 | |
62 | 396000 1150000 | |
63 | 198000 1150000 | |
64 | >; | |
65 | clocks = <&clks IMX6UL_CLK_ARM>, | |
66 | <&clks IMX6UL_CLK_PLL2_BUS>, | |
67 | <&clks IMX6UL_CLK_PLL2_PFD2>, | |
68 | <&clks IMX6UL_CA7_SECONDARY_SEL>, | |
69 | <&clks IMX6UL_CLK_STEP>, | |
70 | <&clks IMX6UL_CLK_PLL1_SW>, | |
71 | <&clks IMX6UL_CLK_PLL1_SYS>, | |
72 | <&clks IMX6UL_PLL1_BYPASS>, | |
73 | <&clks IMX6UL_CLK_PLL1>, | |
74 | <&clks IMX6UL_PLL1_BYPASS_SRC>, | |
75 | <&clks IMX6UL_CLK_OSC>; | |
76 | clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", | |
77 | "secondary_sel", "step", "pll1_sw", | |
78 | "pll1_sys", "pll1_bypass", "pll1", | |
79 | "pll1_bypass_src", "osc"; | |
80 | arm-supply = <®_arm>; | |
81 | soc-supply = <®_soc>; | |
82 | }; | |
83 | }; | |
84 | ||
85 | intc: interrupt-controller@00a01000 { | |
86 | compatible = "arm,cortex-a7-gic"; | |
87 | #interrupt-cells = <3>; | |
88 | interrupt-controller; | |
89 | reg = <0x00a01000 0x1000>, | |
90 | <0x00a02000 0x1000>, | |
91 | <0x00a04000 0x2000>, | |
92 | <0x00a06000 0x2000>; | |
93 | }; | |
94 | ||
95 | ckil: clock-cli { | |
96 | compatible = "fixed-clock"; | |
97 | #clock-cells = <0>; | |
98 | clock-frequency = <32768>; | |
99 | clock-output-names = "ckil"; | |
100 | }; | |
101 | ||
102 | osc: clock-osc { | |
103 | compatible = "fixed-clock"; | |
104 | #clock-cells = <0>; | |
105 | clock-frequency = <24000000>; | |
106 | clock-output-names = "osc"; | |
107 | }; | |
108 | ||
109 | ipp_di0: clock-di0 { | |
110 | compatible = "fixed-clock"; | |
111 | #clock-cells = <0>; | |
112 | clock-frequency = <0>; | |
113 | clock-output-names = "ipp_di0"; | |
114 | }; | |
115 | ||
116 | ipp_di1: clock-di1 { | |
117 | compatible = "fixed-clock"; | |
118 | #clock-cells = <0>; | |
119 | clock-frequency = <0>; | |
120 | clock-output-names = "ipp_di1"; | |
121 | }; | |
122 | ||
123 | soc { | |
124 | #address-cells = <1>; | |
125 | #size-cells = <1>; | |
126 | compatible = "simple-bus"; | |
127 | interrupt-parent = <&intc>; | |
128 | ranges; | |
129 | ||
130 | pmu { | |
131 | compatible = "arm,cortex-a7-pmu"; | |
132 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
133 | status = "disabled"; | |
134 | }; | |
135 | ||
136 | aips1: aips-bus@02000000 { | |
137 | compatible = "fsl,aips-bus", "simple-bus"; | |
138 | #address-cells = <1>; | |
139 | #size-cells = <1>; | |
140 | reg = <0x02000000 0x100000>; | |
141 | ranges; | |
142 | ||
143 | spba-bus@02000000 { | |
144 | compatible = "fsl,spba-bus", "simple-bus"; | |
145 | #address-cells = <1>; | |
146 | #size-cells = <1>; | |
147 | reg = <0x02000000 0x40000>; | |
148 | ranges; | |
149 | ||
150 | ecspi1: ecspi@02008000 { | |
151 | #address-cells = <1>; | |
152 | #size-cells = <0>; | |
153 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
154 | reg = <0x02008000 0x4000>; | |
155 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
156 | clocks = <&clks IMX6UL_CLK_ECSPI1>, | |
157 | <&clks IMX6UL_CLK_ECSPI1>; | |
158 | clock-names = "ipg", "per"; | |
159 | status = "disabled"; | |
160 | }; | |
161 | ||
162 | ecspi2: ecspi@0200c000 { | |
163 | #address-cells = <1>; | |
164 | #size-cells = <0>; | |
165 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
166 | reg = <0x0200c000 0x4000>; | |
167 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
168 | clocks = <&clks IMX6UL_CLK_ECSPI2>, | |
169 | <&clks IMX6UL_CLK_ECSPI2>; | |
170 | clock-names = "ipg", "per"; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | ecspi3: ecspi@02010000 { | |
175 | #address-cells = <1>; | |
176 | #size-cells = <0>; | |
177 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
178 | reg = <0x02010000 0x4000>; | |
179 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
180 | clocks = <&clks IMX6UL_CLK_ECSPI3>, | |
181 | <&clks IMX6UL_CLK_ECSPI3>; | |
182 | clock-names = "ipg", "per"; | |
183 | status = "disabled"; | |
184 | }; | |
185 | ||
186 | ecspi4: ecspi@02014000 { | |
187 | #address-cells = <1>; | |
188 | #size-cells = <0>; | |
189 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
190 | reg = <0x02014000 0x4000>; | |
191 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
192 | clocks = <&clks IMX6UL_CLK_ECSPI4>, | |
193 | <&clks IMX6UL_CLK_ECSPI4>; | |
194 | clock-names = "ipg", "per"; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
198 | uart7: serial@02018000 { | |
199 | compatible = "fsl,imx6ul-uart", | |
200 | "fsl,imx6q-uart"; | |
201 | reg = <0x02018000 0x4000>; | |
202 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
203 | clocks = <&clks IMX6UL_CLK_UART7_IPG>, | |
204 | <&clks IMX6UL_CLK_UART7_SERIAL>; | |
205 | clock-names = "ipg", "per"; | |
206 | status = "disabled"; | |
207 | }; | |
208 | ||
209 | uart1: serial@02020000 { | |
210 | compatible = "fsl,imx6ul-uart", | |
211 | "fsl,imx6q-uart"; | |
212 | reg = <0x02020000 0x4000>; | |
213 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
214 | clocks = <&clks IMX6UL_CLK_UART1_IPG>, | |
215 | <&clks IMX6UL_CLK_UART1_SERIAL>; | |
216 | clock-names = "ipg", "per"; | |
217 | status = "disabled"; | |
218 | }; | |
219 | ||
220 | uart8: serial@02024000 { | |
221 | compatible = "fsl,imx6ul-uart", | |
222 | "fsl,imx6q-uart"; | |
223 | reg = <0x02024000 0x4000>; | |
224 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
225 | clocks = <&clks IMX6UL_CLK_UART8_IPG>, | |
226 | <&clks IMX6UL_CLK_UART8_SERIAL>; | |
227 | clock-names = "ipg", "per"; | |
228 | status = "disabled"; | |
229 | }; | |
230 | }; | |
231 | ||
232 | gpt1: gpt@02098000 { | |
233 | compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
234 | reg = <0x02098000 0x4000>; | |
235 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
236 | clocks = <&clks IMX6UL_CLK_GPT1_BUS>, | |
237 | <&clks IMX6UL_CLK_GPT1_SERIAL>; | |
238 | clock-names = "ipg", "per"; | |
239 | }; | |
240 | ||
241 | gpio1: gpio@0209c000 { | |
242 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
243 | reg = <0x0209c000 0x4000>; | |
244 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
245 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
246 | gpio-controller; | |
247 | #gpio-cells = <2>; | |
248 | interrupt-controller; | |
249 | #interrupt-cells = <2>; | |
250 | }; | |
251 | ||
252 | gpio2: gpio@020a0000 { | |
253 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
254 | reg = <0x020a0000 0x4000>; | |
255 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
256 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
257 | gpio-controller; | |
258 | #gpio-cells = <2>; | |
259 | interrupt-controller; | |
260 | #interrupt-cells = <2>; | |
261 | }; | |
262 | ||
263 | gpio3: gpio@020a4000 { | |
264 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
265 | reg = <0x020a4000 0x4000>; | |
266 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
267 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
268 | gpio-controller; | |
269 | #gpio-cells = <2>; | |
270 | interrupt-controller; | |
271 | #interrupt-cells = <2>; | |
272 | }; | |
273 | ||
274 | gpio4: gpio@020a8000 { | |
275 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
276 | reg = <0x020a8000 0x4000>; | |
277 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
278 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
279 | gpio-controller; | |
280 | #gpio-cells = <2>; | |
281 | interrupt-controller; | |
282 | #interrupt-cells = <2>; | |
283 | }; | |
284 | ||
285 | gpio5: gpio@020ac000 { | |
286 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
287 | reg = <0x020ac000 0x4000>; | |
288 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
289 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
290 | gpio-controller; | |
291 | #gpio-cells = <2>; | |
292 | interrupt-controller; | |
293 | #interrupt-cells = <2>; | |
294 | }; | |
295 | ||
296 | wdog1: wdog@020bc000 { | |
297 | compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
298 | reg = <0x020bc000 0x4000>; | |
299 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
300 | clocks = <&clks IMX6UL_CLK_WDOG1>; | |
301 | }; | |
302 | ||
303 | wdog2: wdog@020c0000 { | |
304 | compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
305 | reg = <0x020c0000 0x4000>; | |
306 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
307 | clocks = <&clks IMX6UL_CLK_WDOG2>; | |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | clks: ccm@020c4000 { | |
312 | compatible = "fsl,imx6ul-ccm"; | |
313 | reg = <0x020c4000 0x4000>; | |
314 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
315 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
316 | #clock-cells = <1>; | |
317 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
318 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
319 | }; | |
320 | ||
321 | anatop: anatop@020c8000 { | |
322 | compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", | |
323 | "syscon", "simple-bus"; | |
324 | reg = <0x020c8000 0x1000>; | |
325 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
326 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
327 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
328 | ||
329 | reg_3p0: regulator-3p0@120 { | |
330 | compatible = "fsl,anatop-regulator"; | |
331 | regulator-name = "vdd3p0"; | |
332 | regulator-min-microvolt = <2625000>; | |
333 | regulator-max-microvolt = <3400000>; | |
334 | anatop-reg-offset = <0x120>; | |
335 | anatop-vol-bit-shift = <8>; | |
336 | anatop-vol-bit-width = <5>; | |
337 | anatop-min-bit-val = <0>; | |
338 | anatop-min-voltage = <2625000>; | |
339 | anatop-max-voltage = <3400000>; | |
340 | anatop-enable-bit = <0>; | |
341 | }; | |
342 | ||
343 | reg_arm: regulator-vddcore@140 { | |
344 | compatible = "fsl,anatop-regulator"; | |
345 | regulator-name = "cpu"; | |
346 | regulator-min-microvolt = <725000>; | |
347 | regulator-max-microvolt = <1450000>; | |
348 | regulator-always-on; | |
349 | anatop-reg-offset = <0x140>; | |
350 | anatop-vol-bit-shift = <0>; | |
351 | anatop-vol-bit-width = <5>; | |
352 | anatop-delay-reg-offset = <0x170>; | |
353 | anatop-delay-bit-shift = <24>; | |
354 | anatop-delay-bit-width = <2>; | |
355 | anatop-min-bit-val = <1>; | |
356 | anatop-min-voltage = <725000>; | |
357 | anatop-max-voltage = <1450000>; | |
358 | }; | |
359 | ||
360 | reg_soc: regulator-vddsoc@140 { | |
361 | compatible = "fsl,anatop-regulator"; | |
362 | regulator-name = "vddsoc"; | |
363 | regulator-min-microvolt = <725000>; | |
364 | regulator-max-microvolt = <1450000>; | |
365 | regulator-always-on; | |
366 | anatop-reg-offset = <0x140>; | |
367 | anatop-vol-bit-shift = <18>; | |
368 | anatop-vol-bit-width = <5>; | |
369 | anatop-delay-reg-offset = <0x170>; | |
370 | anatop-delay-bit-shift = <28>; | |
371 | anatop-delay-bit-width = <2>; | |
372 | anatop-min-bit-val = <1>; | |
373 | anatop-min-voltage = <725000>; | |
374 | anatop-max-voltage = <1450000>; | |
375 | }; | |
376 | }; | |
377 | ||
378 | usbphy1: usbphy@020c9000 { | |
379 | compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
380 | reg = <0x020c9000 0x1000>; | |
381 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
382 | clocks = <&clks IMX6UL_CLK_USBPHY1>; | |
383 | phy-3p0-supply = <®_3p0>; | |
384 | fsl,anatop = <&anatop>; | |
385 | }; | |
386 | ||
387 | usbphy2: usbphy@020ca000 { | |
388 | compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
389 | reg = <0x020ca000 0x1000>; | |
390 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
391 | clocks = <&clks IMX6UL_CLK_USBPHY2>; | |
392 | phy-3p0-supply = <®_3p0>; | |
393 | fsl,anatop = <&anatop>; | |
394 | }; | |
395 | ||
396 | epit1: epit@020d0000 { | |
397 | reg = <0x020d0000 0x4000>; | |
398 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
399 | }; | |
400 | ||
401 | epit2: epit@020d4000 { | |
402 | reg = <0x020d4000 0x4000>; | |
403 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
404 | }; | |
405 | ||
406 | src: src@020d8000 { | |
407 | compatible = "fsl,imx6ul-src", "fsl,imx51-src"; | |
408 | reg = <0x020d8000 0x4000>; | |
409 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
410 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
411 | #reset-cells = <1>; | |
412 | }; | |
413 | ||
414 | gpc: gpc@020dc000 { | |
415 | compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; | |
416 | reg = <0x020dc000 0x4000>; | |
417 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
418 | }; | |
419 | ||
420 | iomuxc: iomuxc@020e0000 { | |
421 | compatible = "fsl,imx6ul-iomuxc"; | |
422 | reg = <0x020e0000 0x4000>; | |
423 | }; | |
424 | ||
425 | gpr: iomuxc-gpr@020e4000 { | |
426 | compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; | |
427 | reg = <0x020e4000 0x4000>; | |
428 | }; | |
429 | ||
430 | gpt2: gpt@020e8000 { | |
431 | compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
432 | reg = <0x020e8000 0x4000>; | |
433 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
434 | clocks = <&clks IMX6UL_CLK_DUMMY>, | |
435 | <&clks IMX6UL_CLK_DUMMY>; | |
436 | clock-names = "ipg", "per"; | |
437 | }; | |
438 | ||
439 | pwm5: pwm@020f0000 { | |
440 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
441 | reg = <0x020f0000 0x4000>; | |
442 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
443 | clocks = <&clks IMX6UL_CLK_DUMMY>, | |
444 | <&clks IMX6UL_CLK_DUMMY>; | |
445 | clock-names = "ipg", "per"; | |
446 | #pwm-cells = <2>; | |
447 | }; | |
448 | ||
449 | pwm6: pwm@020f4000 { | |
450 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
451 | reg = <0x020f4000 0x4000>; | |
452 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
453 | clocks = <&clks IMX6UL_CLK_DUMMY>, | |
454 | <&clks IMX6UL_CLK_DUMMY>; | |
455 | clock-names = "ipg", "per"; | |
456 | #pwm-cells = <2>; | |
457 | }; | |
458 | ||
459 | pwm7: pwm@020f8000 { | |
460 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
461 | reg = <0x020f8000 0x4000>; | |
462 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
463 | clocks = <&clks IMX6UL_CLK_DUMMY>, | |
464 | <&clks IMX6UL_CLK_DUMMY>; | |
465 | clock-names = "ipg", "per"; | |
466 | #pwm-cells = <2>; | |
467 | }; | |
468 | ||
469 | pwm8: pwm@020fc000 { | |
470 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
471 | reg = <0x020fc000 0x4000>; | |
472 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
473 | clocks = <&clks IMX6UL_CLK_DUMMY>, | |
474 | <&clks IMX6UL_CLK_DUMMY>; | |
475 | clock-names = "ipg", "per"; | |
476 | #pwm-cells = <2>; | |
477 | }; | |
478 | }; | |
479 | ||
480 | aips2: aips-bus@02100000 { | |
481 | compatible = "fsl,aips-bus", "simple-bus"; | |
482 | #address-cells = <1>; | |
483 | #size-cells = <1>; | |
484 | reg = <0x02100000 0x100000>; | |
485 | ranges; | |
486 | ||
cad2cb69 FL |
487 | usbotg1: usb@02184000 { |
488 | compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
489 | reg = <0x02184000 0x200>; | |
490 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
491 | clocks = <&clks IMX6UL_CLK_USBOH3>; | |
492 | fsl,usbphy = <&usbphy1>; | |
493 | fsl,usbmisc = <&usbmisc 0>; | |
494 | fsl,anatop = <&anatop>; | |
495 | status = "disabled"; | |
496 | }; | |
497 | ||
498 | usbotg2: usb@02184200 { | |
499 | compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
500 | reg = <0x02184200 0x200>; | |
501 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
502 | clocks = <&clks IMX6UL_CLK_USBOH3>; | |
503 | fsl,usbphy = <&usbphy2>; | |
504 | fsl,usbmisc = <&usbmisc 1>; | |
505 | status = "disabled"; | |
506 | }; | |
507 | ||
508 | usbmisc: usbmisc@02184800 { | |
509 | #index-cells = <1>; | |
510 | compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; | |
511 | reg = <0x02184800 0x200>; | |
512 | }; | |
513 | ||
a5fcccbc FL |
514 | usdhc1: usdhc@02190000 { |
515 | compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
516 | reg = <0x02190000 0x4000>; | |
517 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
518 | clocks = <&clks IMX6UL_CLK_USDHC1>, | |
519 | <&clks IMX6UL_CLK_USDHC1>, | |
520 | <&clks IMX6UL_CLK_USDHC1>; | |
521 | clock-names = "ipg", "ahb", "per"; | |
522 | bus-width = <4>; | |
523 | status = "disabled"; | |
524 | }; | |
525 | ||
526 | usdhc2: usdhc@02194000 { | |
527 | compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
528 | reg = <0x02194000 0x4000>; | |
529 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
530 | clocks = <&clks IMX6UL_CLK_USDHC2>, | |
531 | <&clks IMX6UL_CLK_USDHC2>, | |
532 | <&clks IMX6UL_CLK_USDHC2>; | |
533 | clock-names = "ipg", "ahb", "per"; | |
534 | bus-width = <4>; | |
535 | status = "disabled"; | |
536 | }; | |
537 | ||
538 | i2c1: i2c@021a0000 { | |
539 | #address-cells = <1>; | |
540 | #size-cells = <0>; | |
541 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
542 | reg = <0x021a0000 0x4000>; | |
543 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
544 | clocks = <&clks IMX6UL_CLK_I2C1>; | |
545 | status = "disabled"; | |
546 | }; | |
547 | ||
548 | i2c2: i2c@021a4000 { | |
549 | #address-cells = <1>; | |
550 | #size-cells = <0>; | |
551 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
552 | reg = <0x021a4000 0x4000>; | |
553 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
554 | clocks = <&clks IMX6UL_CLK_I2C2>; | |
555 | status = "disabled"; | |
556 | }; | |
557 | ||
558 | i2c3: i2c@021a8000 { | |
559 | #address-cells = <1>; | |
560 | #size-cells = <0>; | |
561 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
562 | reg = <0x021a8000 0x4000>; | |
563 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
564 | clocks = <&clks IMX6UL_CLK_I2C3>; | |
565 | status = "disabled"; | |
566 | }; | |
567 | ||
568 | uart2: serial@021e8000 { | |
569 | compatible = "fsl,imx6ul-uart", | |
570 | "fsl,imx6q-uart"; | |
571 | reg = <0x021e8000 0x4000>; | |
572 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
573 | clocks = <&clks IMX6UL_CLK_UART2_IPG>, | |
574 | <&clks IMX6UL_CLK_UART2_SERIAL>; | |
575 | clock-names = "ipg", "per"; | |
576 | status = "disabled"; | |
577 | }; | |
578 | ||
579 | uart3: serial@021ec000 { | |
580 | compatible = "fsl,imx6ul-uart", | |
581 | "fsl,imx6q-uart"; | |
582 | reg = <0x021ec000 0x4000>; | |
583 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
584 | clocks = <&clks IMX6UL_CLK_UART3_IPG>, | |
585 | <&clks IMX6UL_CLK_UART3_SERIAL>; | |
586 | clock-names = "ipg", "per"; | |
587 | status = "disabled"; | |
588 | }; | |
589 | ||
590 | uart4: serial@021f0000 { | |
591 | compatible = "fsl,imx6ul-uart", | |
592 | "fsl,imx6q-uart"; | |
593 | reg = <0x021f0000 0x4000>; | |
594 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
595 | clocks = <&clks IMX6UL_CLK_UART4_IPG>, | |
596 | <&clks IMX6UL_CLK_UART4_SERIAL>; | |
597 | clock-names = "ipg", "per"; | |
598 | status = "disabled"; | |
599 | }; | |
600 | ||
601 | uart5: serial@021f4000 { | |
602 | compatible = "fsl,imx6ul-uart", | |
603 | "fsl,imx6q-uart"; | |
604 | reg = <0x021f4000 0x4000>; | |
605 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
606 | clocks = <&clks IMX6UL_CLK_UART5_IPG>, | |
607 | <&clks IMX6UL_CLK_UART5_SERIAL>; | |
608 | clock-names = "ipg", "per"; | |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
612 | i2c4: i2c@021f8000 { | |
613 | #address-cells = <1>; | |
614 | #size-cells = <0>; | |
615 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
616 | reg = <0x021f8000 0x4000>; | |
617 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
618 | clocks = <&clks IMX6UL_CLK_I2C4>; | |
619 | status = "disabled"; | |
620 | }; | |
621 | ||
622 | uart6: serial@021fc000 { | |
623 | compatible = "fsl,imx6ul-uart", | |
624 | "fsl,imx6q-uart"; | |
625 | reg = <0x021fc000 0x4000>; | |
626 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
627 | clocks = <&clks IMX6UL_CLK_UART6_IPG>, | |
628 | <&clks IMX6UL_CLK_UART6_SERIAL>; | |
629 | clock-names = "ipg", "per"; | |
630 | status = "disabled"; | |
631 | }; | |
632 | }; | |
633 | }; | |
634 | }; |