projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: imx6ul: add lcdif support
[deliverable/linux.git] / arch / arm / boot / dts / imx6ul.dtsi
CommitLineData
a5fcccbc
FL		 1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
89435fea 11#include <dt-bindings/input/input.h>
a5fcccbc
FL		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14#include "skeleton.dtsi"
15
16/ {
17 aliases {
01f3dc7d
FD		 18 ethernet0 = &fec1;
19 ethernet1 = &fec2;
a5fcccbc
FL		 20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 spi0 = &ecspi1;
40 spi1 = &ecspi2;
41 spi2 = &ecspi3;
42 spi3 = &ecspi4;
43 usbphy0 = &usbphy1;
44 usbphy1 = &usbphy2;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 compatible = "arm,cortex-a7";
53 device_type = "cpu";
54 reg = <0>;
55 clock-latency = <61036>; /* two CLK32 periods */
56 operating-points = <
57 /* kHz uV */
58 528000 1250000
59 396000 1150000
60 198000 1150000
61 >;
62 fsl,soc-operating-points = <
63 /* KHz uV */
64 528000 1250000
65 396000 1150000
66 198000 1150000
67 >;
68 clocks = <&clks IMX6UL_CLK_ARM>,
69 <&clks IMX6UL_CLK_PLL2_BUS>,
70 <&clks IMX6UL_CLK_PLL2_PFD2>,
71 <&clks IMX6UL_CA7_SECONDARY_SEL>,
72 <&clks IMX6UL_CLK_STEP>,
73 <&clks IMX6UL_CLK_PLL1_SW>,
74 <&clks IMX6UL_CLK_PLL1_SYS>,
75 <&clks IMX6UL_PLL1_BYPASS>,
76 <&clks IMX6UL_CLK_PLL1>,
77 <&clks IMX6UL_PLL1_BYPASS_SRC>,
78 <&clks IMX6UL_CLK_OSC>;
79 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
80 "secondary_sel", "step", "pll1_sw",
81 "pll1_sys", "pll1_bypass", "pll1",
82 "pll1_bypass_src", "osc";
83 arm-supply = <&reg_arm>;
84 soc-supply = <&reg_soc>;
85 };
86 };
87
88 intc: interrupt-controller@00a01000 {
89 compatible = "arm,cortex-a7-gic";
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 reg = <0x00a01000 0x1000>,
93 <0x00a02000 0x1000>,
94 <0x00a04000 0x2000>,
95 <0x00a06000 0x2000>;
96 };
97
98 ckil: clock-cli {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
110 };
111
112 ipp_di0: clock-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
117 };
118
119 ipp_di1: clock-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
124 };
125
126 soc {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-bus";
18619ff5 130 interrupt-parent = <&gpc>;
a5fcccbc
FL		 131 ranges;
132
133 pmu {
134 compatible = "arm,cortex-a7-pmu";
135 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
136 status = "disabled";
137 };
138
322d09d6
AH		 139 ocram: sram@00900000 {
140 compatible = "mmio-sram";
141 reg = <0x00900000 0x20000>;
142 };
143
a5fcccbc
FL		 144 aips1: aips-bus@02000000 {
145 compatible = "fsl,aips-bus", "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 reg = <0x02000000 0x100000>;
149 ranges;
150
151 spba-bus@02000000 {
152 compatible = "fsl,spba-bus", "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 reg = <0x02000000 0x40000>;
156 ranges;
157
158 ecspi1: ecspi@02008000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&clks IMX6UL_CLK_ECSPI1>,
165 <&clks IMX6UL_CLK_ECSPI1>;
166 clock-names = "ipg", "per";
167 status = "disabled";
168 };
169
170 ecspi2: ecspi@0200c000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
174 reg = <0x0200c000 0x4000>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6UL_CLK_ECSPI2>,
177 <&clks IMX6UL_CLK_ECSPI2>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
181
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clks IMX6UL_CLK_ECSPI3>,
189 <&clks IMX6UL_CLK_ECSPI3>;
190 clock-names = "ipg", "per";
191 status = "disabled";
192 };
193
194 ecspi4: ecspi@02014000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02014000 0x4000>;
199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6UL_CLK_ECSPI4>,
201 <&clks IMX6UL_CLK_ECSPI4>;
202 clock-names = "ipg", "per";
203 status = "disabled";
204 };
205
206 uart7: serial@02018000 {
207 compatible = "fsl,imx6ul-uart",
208 "fsl,imx6q-uart";
209 reg = <0x02018000 0x4000>;
210 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
212 <&clks IMX6UL_CLK_UART7_SERIAL>;
213 clock-names = "ipg", "per";
214 status = "disabled";
215 };
216
217 uart1: serial@02020000 {
218 compatible = "fsl,imx6ul-uart",
219 "fsl,imx6q-uart";
220 reg = <0x02020000 0x4000>;
221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
223 <&clks IMX6UL_CLK_UART1_SERIAL>;
224 clock-names = "ipg", "per";
225 status = "disabled";
226 };
227
228 uart8: serial@02024000 {
229 compatible = "fsl,imx6ul-uart",
230 "fsl,imx6q-uart";
231 reg = <0x02024000 0x4000>;
232 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
234 <&clks IMX6UL_CLK_UART8_SERIAL>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
36e2edf6
LW		 238
239 sai1: sai@02028000 {
240 #sound-dai-cells = <0>;
241 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
242 reg = <0x02028000 0x4000>;
243 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
245 <&clks IMX6UL_CLK_SAI1>,
246 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
247 clock-names = "bus", "mclk1", "mclk2", "mclk3";
248 dmas = <&sdma 35 24 0>,
249 <&sdma 36 24 0>;
250 dma-names = "rx", "tx";
251 status = "disabled";
252 };
253
254 sai2: sai@0202c000 {
255 #sound-dai-cells = <0>;
256 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
257 reg = <0x0202c000 0x4000>;
258 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
260 <&clks IMX6UL_CLK_SAI2>,
261 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
262 clock-names = "bus", "mclk1", "mclk2", "mclk3";
263 dmas = <&sdma 37 24 0>,
264 <&sdma 38 24 0>;
265 dma-names = "rx", "tx";
266 status = "disabled";
267 };
268
269 sai3: sai@02030000 {
270 #sound-dai-cells = <0>;
271 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
272 reg = <0x02030000 0x4000>;
273 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
275 <&clks IMX6UL_CLK_SAI3>,
276 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
277 clock-names = "bus", "mclk1", "mclk2", "mclk3";
278 dmas = <&sdma 39 24 0>,
279 <&sdma 40 24 0>;
280 dma-names = "rx", "tx";
281 status = "disabled";
282 };
a5fcccbc
FL		 283 };
284
302e01b2
LW		 285 tsc: tsc@02040000 {
286 compatible = "fsl,imx6ul-tsc";
287 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
288 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6UL_CLK_IPG>,
291 <&clks IMX6UL_CLK_ADC2>;
292 clock-names = "tsc", "adc";
293 status = "disabled";
294 };
295
b9901fe8
LW		 296 pwm1: pwm@02080000 {
297 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
298 reg = <0x02080000 0x4000>;
299 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clks IMX6UL_CLK_PWM1>,
301 <&clks IMX6UL_CLK_PWM1>;
302 clock-names = "ipg", "per";
303 #pwm-cells = <2>;
304 status = "disabled";
305 };
306
307 pwm2: pwm@02084000 {
308 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
309 reg = <0x02084000 0x4000>;
310 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks IMX6UL_CLK_PWM2>,
312 <&clks IMX6UL_CLK_PWM2>;
313 clock-names = "ipg", "per";
314 #pwm-cells = <2>;
315 status = "disabled";
316 };
317
318 pwm3: pwm@02088000 {
319 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
320 reg = <0x02088000 0x4000>;
321 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX6UL_CLK_PWM3>,
323 <&clks IMX6UL_CLK_PWM3>;
324 clock-names = "ipg", "per";
325 #pwm-cells = <2>;
326 status = "disabled";
327 };
328
329 pwm4: pwm@0208c000 {
330 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
331 reg = <0x0208c000 0x4000>;
332 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6UL_CLK_PWM4>,
334 <&clks IMX6UL_CLK_PWM4>;
335 clock-names = "ipg", "per";
336 #pwm-cells = <2>;
337 status = "disabled";
338 };
339
c4aac1b1
LW		 340 can1: flexcan@02090000 {
341 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
342 reg = <0x02090000 0x4000>;
343 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
345 <&clks IMX6UL_CLK_CAN1_SERIAL>;
346 clock-names = "ipg", "per";
347 status = "disabled";
348 };
349
350 can2: flexcan@02094000 {
351 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
352 reg = <0x02094000 0x4000>;
353 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
355 <&clks IMX6UL_CLK_CAN2_SERIAL>;
356 clock-names = "ipg", "per";
357 status = "disabled";
358 };
359
a5fcccbc
FL		 360 gpt1: gpt@02098000 {
361 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
362 reg = <0x02098000 0x4000>;
363 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
365 <&clks IMX6UL_CLK_GPT1_SERIAL>;
366 clock-names = "ipg", "per";
367 };
368
369 gpio1: gpio@0209c000 {
370 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
371 reg = <0x0209c000 0x4000>;
372 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
379
380 gpio2: gpio@020a0000 {
381 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
382 reg = <0x020a0000 0x4000>;
383 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
385 gpio-controller;
386 #gpio-cells = <2>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 };
390
391 gpio3: gpio@020a4000 {
392 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
393 reg = <0x020a4000 0x4000>;
394 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 };
401
402 gpio4: gpio@020a8000 {
403 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
404 reg = <0x020a8000 0x4000>;
405 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 };
412
413 gpio5: gpio@020ac000 {
414 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
415 reg = <0x020ac000 0x4000>;
416 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
01f3dc7d
FD		 424 fec2: ethernet@020b4000 {
425 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
426 reg = <0x020b4000 0x4000>;
427 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clks IMX6UL_CLK_ENET>,
430 <&clks IMX6UL_CLK_ENET_AHB>,
431 <&clks IMX6UL_CLK_ENET_PTP>,
432 <&clks IMX6UL_CLK_ENET2_REF_125M>,
433 <&clks IMX6UL_CLK_ENET2_REF_125M>;
434 clock-names = "ipg", "ahb", "ptp",
435 "enet_clk_ref", "enet_out";
436 fsl,num-tx-queues=<1>;
437 fsl,num-rx-queues=<1>;
438 status = "disabled";
439 };
440
a5fcccbc
FL		 441 wdog1: wdog@020bc000 {
442 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
443 reg = <0x020bc000 0x4000>;
444 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clks IMX6UL_CLK_WDOG1>;
446 };
447
448 wdog2: wdog@020c0000 {
449 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
450 reg = <0x020c0000 0x4000>;
451 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX6UL_CLK_WDOG2>;
453 status = "disabled";
454 };
455
456 clks: ccm@020c4000 {
457 compatible = "fsl,imx6ul-ccm";
458 reg = <0x020c4000 0x4000>;
459 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
461 #clock-cells = <1>;
462 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
463 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
464 };
465
466 anatop: anatop@020c8000 {
467 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
468 "syscon", "simple-bus";
469 reg = <0x020c8000 0x1000>;
470 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
473
474 reg_3p0: regulator-3p0@120 {
475 compatible = "fsl,anatop-regulator";
476 regulator-name = "vdd3p0";
477 regulator-min-microvolt = <2625000>;
478 regulator-max-microvolt = <3400000>;
479 anatop-reg-offset = <0x120>;
480 anatop-vol-bit-shift = <8>;
481 anatop-vol-bit-width = <5>;
482 anatop-min-bit-val = <0>;
483 anatop-min-voltage = <2625000>;
484 anatop-max-voltage = <3400000>;
485 anatop-enable-bit = <0>;
486 };
487
488 reg_arm: regulator-vddcore@140 {
489 compatible = "fsl,anatop-regulator";
490 regulator-name = "cpu";
491 regulator-min-microvolt = <725000>;
492 regulator-max-microvolt = <1450000>;
493 regulator-always-on;
494 anatop-reg-offset = <0x140>;
495 anatop-vol-bit-shift = <0>;
496 anatop-vol-bit-width = <5>;
497 anatop-delay-reg-offset = <0x170>;
498 anatop-delay-bit-shift = <24>;
499 anatop-delay-bit-width = <2>;
500 anatop-min-bit-val = <1>;
501 anatop-min-voltage = <725000>;
502 anatop-max-voltage = <1450000>;
503 };
504
505 reg_soc: regulator-vddsoc@140 {
506 compatible = "fsl,anatop-regulator";
507 regulator-name = "vddsoc";
508 regulator-min-microvolt = <725000>;
509 regulator-max-microvolt = <1450000>;
510 regulator-always-on;
511 anatop-reg-offset = <0x140>;
512 anatop-vol-bit-shift = <18>;
513 anatop-vol-bit-width = <5>;
514 anatop-delay-reg-offset = <0x170>;
515 anatop-delay-bit-shift = <28>;
516 anatop-delay-bit-width = <2>;
517 anatop-min-bit-val = <1>;
518 anatop-min-voltage = <725000>;
519 anatop-max-voltage = <1450000>;
520 };
521 };
522
523 usbphy1: usbphy@020c9000 {
524 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
525 reg = <0x020c9000 0x1000>;
526 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&clks IMX6UL_CLK_USBPHY1>;
528 phy-3p0-supply = <&reg_3p0>;
529 fsl,anatop = <&anatop>;
530 };
531
532 usbphy2: usbphy@020ca000 {
533 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
534 reg = <0x020ca000 0x1000>;
535 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&clks IMX6UL_CLK_USBPHY2>;
537 phy-3p0-supply = <&reg_3p0>;
538 fsl,anatop = <&anatop>;
539 };
540
5b032872
AH		 541 snvs: snvs@020cc000 {
542 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
543 reg = <0x020cc000 0x4000>;
544
545 snvs_rtc: snvs-rtc-lp {
546 compatible = "fsl,sec-v4.0-mon-rtc-lp";
547 regmap = <&snvs>;
548 offset = <0x34>;
549 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
551 };
36032575 552
ab0a05d8
AH		 553 snvs_poweroff: snvs-poweroff {
554 compatible = "syscon-poweroff";
555 regmap = <&snvs>;
556 offset = <0x38>;
557 mask = <0x60>;
558 status = "disabled";
559 };
560
36032575
AH		 561 snvs_pwrkey: snvs-powerkey {
562 compatible = "fsl,sec-v4.0-pwrkey";
563 regmap = <&snvs>;
564 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
565 linux,keycode = <KEY_POWER>;
566 wakeup-source;
567 };
5b032872
AH		 568 };
569
a5fcccbc
FL		 570 epit1: epit@020d0000 {
571 reg = <0x020d0000 0x4000>;
572 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
573 };
574
575 epit2: epit@020d4000 {
576 reg = <0x020d4000 0x4000>;
577 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
578 };
579
580 src: src@020d8000 {
581 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
582 reg = <0x020d8000 0x4000>;
583 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
585 #reset-cells = <1>;
586 };
587
588 gpc: gpc@020dc000 {
589 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
590 reg = <0x020dc000 0x4000>;
18619ff5
AH		 591 interrupt-controller;
592 #interrupt-cells = <3>;
a5fcccbc 593 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
18619ff5 594 interrupt-parent = <&intc>;
a5fcccbc
FL		 595 };
596
597 iomuxc: iomuxc@020e0000 {
598 compatible = "fsl,imx6ul-iomuxc";
599 reg = <0x020e0000 0x4000>;
600 };
601
602 gpr: iomuxc-gpr@020e4000 {
603 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
604 reg = <0x020e4000 0x4000>;
605 };
606
607 gpt2: gpt@020e8000 {
608 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
609 reg = <0x020e8000 0x4000>;
610 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
d97ca99f
LW		 611 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
612 <&clks IMX6UL_CLK_GPT2_SERIAL>;
a5fcccbc
FL		 613 clock-names = "ipg", "per";
614 };
615
76758c6a
LW		 616 sdma: sdma@020ec000 {
617 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
618 "fsl,imx35-sdma";
619 reg = <0x020ec000 0x4000>;
620 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&clks IMX6UL_CLK_SDMA>,
622 <&clks IMX6UL_CLK_SDMA>;
623 clock-names = "ipg", "ahb";
624 #dma-cells = <3>;
625 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
626 };
627
a5fcccbc
FL		 628 pwm5: pwm@020f0000 {
629 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
630 reg = <0x020f0000 0x4000>;
631 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 632 clocks = <&clks IMX6UL_CLK_PWM5>,
633 <&clks IMX6UL_CLK_PWM5>;
a5fcccbc
FL		 634 clock-names = "ipg", "per";
635 #pwm-cells = <2>;
dd135095 636 status = "disabled";
a5fcccbc
FL		 637 };
638
639 pwm6: pwm@020f4000 {
640 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
641 reg = <0x020f4000 0x4000>;
642 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 643 clocks = <&clks IMX6UL_CLK_PWM6>,
644 <&clks IMX6UL_CLK_PWM6>;
a5fcccbc
FL		 645 clock-names = "ipg", "per";
646 #pwm-cells = <2>;
dd135095 647 status = "disabled";
a5fcccbc
FL		 648 };
649
650 pwm7: pwm@020f8000 {
651 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
652 reg = <0x020f8000 0x4000>;
653 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 654 clocks = <&clks IMX6UL_CLK_PWM7>,
655 <&clks IMX6UL_CLK_PWM7>;
a5fcccbc
FL		 656 clock-names = "ipg", "per";
657 #pwm-cells = <2>;
dd135095 658 status = "disabled";
a5fcccbc
FL		 659 };
660
661 pwm8: pwm@020fc000 {
662 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
663 reg = <0x020fc000 0x4000>;
664 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 665 clocks = <&clks IMX6UL_CLK_PWM8>,
666 <&clks IMX6UL_CLK_PWM8>;
a5fcccbc
FL		 667 clock-names = "ipg", "per";
668 #pwm-cells = <2>;
dd135095 669 status = "disabled";
a5fcccbc
FL		 670 };
671 };
672
673 aips2: aips-bus@02100000 {
674 compatible = "fsl,aips-bus", "simple-bus";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 reg = <0x02100000 0x100000>;
678 ranges;
679
cad2cb69
FL		 680 usbotg1: usb@02184000 {
681 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
682 reg = <0x02184000 0x200>;
683 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&clks IMX6UL_CLK_USBOH3>;
685 fsl,usbphy = <&usbphy1>;
686 fsl,usbmisc = <&usbmisc 0>;
687 fsl,anatop = <&anatop>;
9493bf54 688 ahb-burst-config = <0x0>;
2b1a40e8
PC		 689 tx-burst-size-dword = <0x10>;
690 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 691 status = "disabled";
692 };
693
694 usbotg2: usb@02184200 {
695 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
696 reg = <0x02184200 0x200>;
697 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clks IMX6UL_CLK_USBOH3>;
699 fsl,usbphy = <&usbphy2>;
700 fsl,usbmisc = <&usbmisc 1>;
9493bf54 701 ahb-burst-config = <0x0>;
2b1a40e8
PC		 702 tx-burst-size-dword = <0x10>;
703 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 704 status = "disabled";
705 };
706
707 usbmisc: usbmisc@02184800 {
708 #index-cells = <1>;
709 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
710 reg = <0x02184800 0x200>;
711 };
712
01f3dc7d
FD		 713 fec1: ethernet@02188000 {
714 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
715 reg = <0x02188000 0x4000>;
716 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clks IMX6UL_CLK_ENET>,
719 <&clks IMX6UL_CLK_ENET_AHB>,
720 <&clks IMX6UL_CLK_ENET_PTP>,
721 <&clks IMX6UL_CLK_ENET_REF>,
722 <&clks IMX6UL_CLK_ENET_REF>;
723 clock-names = "ipg", "ahb", "ptp",
724 "enet_clk_ref", "enet_out";
725 fsl,num-tx-queues=<1>;
726 fsl,num-rx-queues=<1>;
727 status = "disabled";
728 };
729
a5fcccbc
FL		 730 usdhc1: usdhc@02190000 {
731 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
732 reg = <0x02190000 0x4000>;
733 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX6UL_CLK_USDHC1>,
735 <&clks IMX6UL_CLK_USDHC1>,
736 <&clks IMX6UL_CLK_USDHC1>;
737 clock-names = "ipg", "ahb", "per";
738 bus-width = <4>;
739 status = "disabled";
740 };
741
742 usdhc2: usdhc@02194000 {
743 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
744 reg = <0x02194000 0x4000>;
745 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&clks IMX6UL_CLK_USDHC2>,
747 <&clks IMX6UL_CLK_USDHC2>,
748 <&clks IMX6UL_CLK_USDHC2>;
749 clock-names = "ipg", "ahb", "per";
750 bus-width = <4>;
751 status = "disabled";
752 };
753
aab8ec0c
FE		 754 adc1: adc@02198000 {
755 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
756 reg = <0x02198000 0x4000>;
757 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&clks IMX6UL_CLK_ADC1>;
759 num-channels = <2>;
760 clock-names = "adc";
761 fsl,adck-max-frequency = <30000000>, <40000000>,
762 <20000000>;
763 status = "disabled";
764 };
765
a5fcccbc
FL		 766 i2c1: i2c@021a0000 {
767 #address-cells = <1>;
768 #size-cells = <0>;
769 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
770 reg = <0x021a0000 0x4000>;
771 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clks IMX6UL_CLK_I2C1>;
773 status = "disabled";
774 };
775
776 i2c2: i2c@021a4000 {
777 #address-cells = <1>;
778 #size-cells = <0>;
779 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
780 reg = <0x021a4000 0x4000>;
781 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clks IMX6UL_CLK_I2C2>;
783 status = "disabled";
784 };
785
786 i2c3: i2c@021a8000 {
787 #address-cells = <1>;
788 #size-cells = <0>;
789 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
790 reg = <0x021a8000 0x4000>;
791 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clks IMX6UL_CLK_I2C3>;
793 status = "disabled";
794 };
795
51a37443
AH		 796 mmdc: mmdc@021b0000 {
797 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
798 reg = <0x021b0000 0x4000>;
799 };
800
6fe01eb7
LW		 801 lcdif: lcdif@021c8000 {
802 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
803 reg = <0x021c8000 0x4000>;
804 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
806 <&clks IMX6UL_CLK_LCDIF_APB>,
807 <&clks IMX6UL_CLK_DUMMY>;
808 clock-names = "pix", "axi", "disp_axi";
809 status = "disabled";
810 };
811
5ff807a5
FL		 812 qspi: qspi@021e0000 {
813 #address-cells = <1>;
814 #size-cells = <0>;
815 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
816 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
817 reg-names = "QuadSPI", "QuadSPI-memory";
818 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6UL_CLK_QSPI>,
820 <&clks IMX6UL_CLK_QSPI>;
821 clock-names = "qspi_en", "qspi";
822 status = "disabled";
823 };
824
a5fcccbc
FL		 825 uart2: serial@021e8000 {
826 compatible = "fsl,imx6ul-uart",
827 "fsl,imx6q-uart";
828 reg = <0x021e8000 0x4000>;
829 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
831 <&clks IMX6UL_CLK_UART2_SERIAL>;
832 clock-names = "ipg", "per";
833 status = "disabled";
834 };
835
836 uart3: serial@021ec000 {
837 compatible = "fsl,imx6ul-uart",
838 "fsl,imx6q-uart";
839 reg = <0x021ec000 0x4000>;
840 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
842 <&clks IMX6UL_CLK_UART3_SERIAL>;
843 clock-names = "ipg", "per";
844 status = "disabled";
845 };
846
847 uart4: serial@021f0000 {
848 compatible = "fsl,imx6ul-uart",
849 "fsl,imx6q-uart";
850 reg = <0x021f0000 0x4000>;
851 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
853 <&clks IMX6UL_CLK_UART4_SERIAL>;
854 clock-names = "ipg", "per";
855 status = "disabled";
856 };
857
858 uart5: serial@021f4000 {
859 compatible = "fsl,imx6ul-uart",
860 "fsl,imx6q-uart";
861 reg = <0x021f4000 0x4000>;
862 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
864 <&clks IMX6UL_CLK_UART5_SERIAL>;
865 clock-names = "ipg", "per";
866 status = "disabled";
867 };
868
869 i2c4: i2c@021f8000 {
870 #address-cells = <1>;
871 #size-cells = <0>;
872 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
873 reg = <0x021f8000 0x4000>;
874 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clks IMX6UL_CLK_I2C4>;
876 status = "disabled";
877 };
878
879 uart6: serial@021fc000 {
880 compatible = "fsl,imx6ul-uart",
881 "fsl,imx6q-uart";
882 reg = <0x021fc000 0x4000>;
883 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
885 <&clks IMX6UL_CLK_UART6_SERIAL>;
886 clock-names = "ipg", "per";
887 status = "disabled";
888 };
889 };
890 };
891};
Linux kernel - Deliverables
This page took 0.086712 seconds and 5 git commands to generate.