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ARM: dts: imx6ul: add flexcan support
[deliverable/linux.git] / arch / arm / boot / dts / imx6ul.dtsi
CommitLineData
a5fcccbc
FL		 1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
89435fea 11#include <dt-bindings/input/input.h>
a5fcccbc
FL		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14#include "skeleton.dtsi"
15
16/ {
17 aliases {
01f3dc7d
FD		 18 ethernet0 = &fec1;
19 ethernet1 = &fec2;
a5fcccbc
FL		 20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 spi0 = &ecspi1;
40 spi1 = &ecspi2;
41 spi2 = &ecspi3;
42 spi3 = &ecspi4;
43 usbphy0 = &usbphy1;
44 usbphy1 = &usbphy2;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 compatible = "arm,cortex-a7";
53 device_type = "cpu";
54 reg = <0>;
55 clock-latency = <61036>; /* two CLK32 periods */
56 operating-points = <
57 /* kHz uV */
58 528000 1250000
59 396000 1150000
60 198000 1150000
61 >;
62 fsl,soc-operating-points = <
63 /* KHz uV */
64 528000 1250000
65 396000 1150000
66 198000 1150000
67 >;
68 clocks = <&clks IMX6UL_CLK_ARM>,
69 <&clks IMX6UL_CLK_PLL2_BUS>,
70 <&clks IMX6UL_CLK_PLL2_PFD2>,
71 <&clks IMX6UL_CA7_SECONDARY_SEL>,
72 <&clks IMX6UL_CLK_STEP>,
73 <&clks IMX6UL_CLK_PLL1_SW>,
74 <&clks IMX6UL_CLK_PLL1_SYS>,
75 <&clks IMX6UL_PLL1_BYPASS>,
76 <&clks IMX6UL_CLK_PLL1>,
77 <&clks IMX6UL_PLL1_BYPASS_SRC>,
78 <&clks IMX6UL_CLK_OSC>;
79 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
80 "secondary_sel", "step", "pll1_sw",
81 "pll1_sys", "pll1_bypass", "pll1",
82 "pll1_bypass_src", "osc";
83 arm-supply = <&reg_arm>;
84 soc-supply = <&reg_soc>;
85 };
86 };
87
88 intc: interrupt-controller@00a01000 {
89 compatible = "arm,cortex-a7-gic";
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 reg = <0x00a01000 0x1000>,
93 <0x00a02000 0x1000>,
94 <0x00a04000 0x2000>,
95 <0x00a06000 0x2000>;
96 };
97
98 ckil: clock-cli {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
110 };
111
112 ipp_di0: clock-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
117 };
118
119 ipp_di1: clock-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
124 };
125
126 soc {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-bus";
18619ff5 130 interrupt-parent = <&gpc>;
a5fcccbc
FL		 131 ranges;
132
133 pmu {
134 compatible = "arm,cortex-a7-pmu";
135 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
136 status = "disabled";
137 };
138
322d09d6
AH		 139 ocram: sram@00900000 {
140 compatible = "mmio-sram";
141 reg = <0x00900000 0x20000>;
142 };
143
a5fcccbc
FL		 144 aips1: aips-bus@02000000 {
145 compatible = "fsl,aips-bus", "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 reg = <0x02000000 0x100000>;
149 ranges;
150
151 spba-bus@02000000 {
152 compatible = "fsl,spba-bus", "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 reg = <0x02000000 0x40000>;
156 ranges;
157
158 ecspi1: ecspi@02008000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&clks IMX6UL_CLK_ECSPI1>,
165 <&clks IMX6UL_CLK_ECSPI1>;
166 clock-names = "ipg", "per";
167 status = "disabled";
168 };
169
170 ecspi2: ecspi@0200c000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
174 reg = <0x0200c000 0x4000>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6UL_CLK_ECSPI2>,
177 <&clks IMX6UL_CLK_ECSPI2>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
181
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clks IMX6UL_CLK_ECSPI3>,
189 <&clks IMX6UL_CLK_ECSPI3>;
190 clock-names = "ipg", "per";
191 status = "disabled";
192 };
193
194 ecspi4: ecspi@02014000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02014000 0x4000>;
199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6UL_CLK_ECSPI4>,
201 <&clks IMX6UL_CLK_ECSPI4>;
202 clock-names = "ipg", "per";
203 status = "disabled";
204 };
205
206 uart7: serial@02018000 {
207 compatible = "fsl,imx6ul-uart",
208 "fsl,imx6q-uart";
209 reg = <0x02018000 0x4000>;
210 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
212 <&clks IMX6UL_CLK_UART7_SERIAL>;
213 clock-names = "ipg", "per";
214 status = "disabled";
215 };
216
217 uart1: serial@02020000 {
218 compatible = "fsl,imx6ul-uart",
219 "fsl,imx6q-uart";
220 reg = <0x02020000 0x4000>;
221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
223 <&clks IMX6UL_CLK_UART1_SERIAL>;
224 clock-names = "ipg", "per";
225 status = "disabled";
226 };
227
228 uart8: serial@02024000 {
229 compatible = "fsl,imx6ul-uart",
230 "fsl,imx6q-uart";
231 reg = <0x02024000 0x4000>;
232 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
234 <&clks IMX6UL_CLK_UART8_SERIAL>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
238 };
239
302e01b2
LW		 240 tsc: tsc@02040000 {
241 compatible = "fsl,imx6ul-tsc";
242 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
243 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6UL_CLK_IPG>,
246 <&clks IMX6UL_CLK_ADC2>;
247 clock-names = "tsc", "adc";
248 status = "disabled";
249 };
250
b9901fe8
LW		 251 pwm1: pwm@02080000 {
252 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
253 reg = <0x02080000 0x4000>;
254 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX6UL_CLK_PWM1>,
256 <&clks IMX6UL_CLK_PWM1>;
257 clock-names = "ipg", "per";
258 #pwm-cells = <2>;
259 status = "disabled";
260 };
261
262 pwm2: pwm@02084000 {
263 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
264 reg = <0x02084000 0x4000>;
265 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6UL_CLK_PWM2>,
267 <&clks IMX6UL_CLK_PWM2>;
268 clock-names = "ipg", "per";
269 #pwm-cells = <2>;
270 status = "disabled";
271 };
272
273 pwm3: pwm@02088000 {
274 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
275 reg = <0x02088000 0x4000>;
276 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6UL_CLK_PWM3>,
278 <&clks IMX6UL_CLK_PWM3>;
279 clock-names = "ipg", "per";
280 #pwm-cells = <2>;
281 status = "disabled";
282 };
283
284 pwm4: pwm@0208c000 {
285 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
286 reg = <0x0208c000 0x4000>;
287 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clks IMX6UL_CLK_PWM4>,
289 <&clks IMX6UL_CLK_PWM4>;
290 clock-names = "ipg", "per";
291 #pwm-cells = <2>;
292 status = "disabled";
293 };
294
c4aac1b1
LW		 295 can1: flexcan@02090000 {
296 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
297 reg = <0x02090000 0x4000>;
298 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
300 <&clks IMX6UL_CLK_CAN1_SERIAL>;
301 clock-names = "ipg", "per";
302 status = "disabled";
303 };
304
305 can2: flexcan@02094000 {
306 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
307 reg = <0x02094000 0x4000>;
308 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
310 <&clks IMX6UL_CLK_CAN2_SERIAL>;
311 clock-names = "ipg", "per";
312 status = "disabled";
313 };
314
a5fcccbc
FL		 315 gpt1: gpt@02098000 {
316 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
317 reg = <0x02098000 0x4000>;
318 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
320 <&clks IMX6UL_CLK_GPT1_SERIAL>;
321 clock-names = "ipg", "per";
322 };
323
324 gpio1: gpio@0209c000 {
325 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
326 reg = <0x0209c000 0x4000>;
327 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
334
335 gpio2: gpio@020a0000 {
336 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
337 reg = <0x020a0000 0x4000>;
338 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 };
345
346 gpio3: gpio@020a4000 {
347 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
348 reg = <0x020a4000 0x4000>;
349 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 };
356
357 gpio4: gpio@020a8000 {
358 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
359 reg = <0x020a8000 0x4000>;
360 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 };
367
368 gpio5: gpio@020ac000 {
369 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
370 reg = <0x020ac000 0x4000>;
371 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 };
378
01f3dc7d
FD		 379 fec2: ethernet@020b4000 {
380 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
381 reg = <0x020b4000 0x4000>;
382 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clks IMX6UL_CLK_ENET>,
385 <&clks IMX6UL_CLK_ENET_AHB>,
386 <&clks IMX6UL_CLK_ENET_PTP>,
387 <&clks IMX6UL_CLK_ENET2_REF_125M>,
388 <&clks IMX6UL_CLK_ENET2_REF_125M>;
389 clock-names = "ipg", "ahb", "ptp",
390 "enet_clk_ref", "enet_out";
391 fsl,num-tx-queues=<1>;
392 fsl,num-rx-queues=<1>;
393 status = "disabled";
394 };
395
a5fcccbc
FL		 396 wdog1: wdog@020bc000 {
397 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
398 reg = <0x020bc000 0x4000>;
399 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6UL_CLK_WDOG1>;
401 };
402
403 wdog2: wdog@020c0000 {
404 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
405 reg = <0x020c0000 0x4000>;
406 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks IMX6UL_CLK_WDOG2>;
408 status = "disabled";
409 };
410
411 clks: ccm@020c4000 {
412 compatible = "fsl,imx6ul-ccm";
413 reg = <0x020c4000 0x4000>;
414 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
416 #clock-cells = <1>;
417 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
418 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
419 };
420
421 anatop: anatop@020c8000 {
422 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
423 "syscon", "simple-bus";
424 reg = <0x020c8000 0x1000>;
425 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
428
429 reg_3p0: regulator-3p0@120 {
430 compatible = "fsl,anatop-regulator";
431 regulator-name = "vdd3p0";
432 regulator-min-microvolt = <2625000>;
433 regulator-max-microvolt = <3400000>;
434 anatop-reg-offset = <0x120>;
435 anatop-vol-bit-shift = <8>;
436 anatop-vol-bit-width = <5>;
437 anatop-min-bit-val = <0>;
438 anatop-min-voltage = <2625000>;
439 anatop-max-voltage = <3400000>;
440 anatop-enable-bit = <0>;
441 };
442
443 reg_arm: regulator-vddcore@140 {
444 compatible = "fsl,anatop-regulator";
445 regulator-name = "cpu";
446 regulator-min-microvolt = <725000>;
447 regulator-max-microvolt = <1450000>;
448 regulator-always-on;
449 anatop-reg-offset = <0x140>;
450 anatop-vol-bit-shift = <0>;
451 anatop-vol-bit-width = <5>;
452 anatop-delay-reg-offset = <0x170>;
453 anatop-delay-bit-shift = <24>;
454 anatop-delay-bit-width = <2>;
455 anatop-min-bit-val = <1>;
456 anatop-min-voltage = <725000>;
457 anatop-max-voltage = <1450000>;
458 };
459
460 reg_soc: regulator-vddsoc@140 {
461 compatible = "fsl,anatop-regulator";
462 regulator-name = "vddsoc";
463 regulator-min-microvolt = <725000>;
464 regulator-max-microvolt = <1450000>;
465 regulator-always-on;
466 anatop-reg-offset = <0x140>;
467 anatop-vol-bit-shift = <18>;
468 anatop-vol-bit-width = <5>;
469 anatop-delay-reg-offset = <0x170>;
470 anatop-delay-bit-shift = <28>;
471 anatop-delay-bit-width = <2>;
472 anatop-min-bit-val = <1>;
473 anatop-min-voltage = <725000>;
474 anatop-max-voltage = <1450000>;
475 };
476 };
477
478 usbphy1: usbphy@020c9000 {
479 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
480 reg = <0x020c9000 0x1000>;
481 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clks IMX6UL_CLK_USBPHY1>;
483 phy-3p0-supply = <&reg_3p0>;
484 fsl,anatop = <&anatop>;
485 };
486
487 usbphy2: usbphy@020ca000 {
488 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
489 reg = <0x020ca000 0x1000>;
490 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clks IMX6UL_CLK_USBPHY2>;
492 phy-3p0-supply = <&reg_3p0>;
493 fsl,anatop = <&anatop>;
494 };
495
5b032872
AH		 496 snvs: snvs@020cc000 {
497 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
498 reg = <0x020cc000 0x4000>;
499
500 snvs_rtc: snvs-rtc-lp {
501 compatible = "fsl,sec-v4.0-mon-rtc-lp";
502 regmap = <&snvs>;
503 offset = <0x34>;
504 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
506 };
36032575 507
ab0a05d8
AH		 508 snvs_poweroff: snvs-poweroff {
509 compatible = "syscon-poweroff";
510 regmap = <&snvs>;
511 offset = <0x38>;
512 mask = <0x60>;
513 status = "disabled";
514 };
515
36032575
AH		 516 snvs_pwrkey: snvs-powerkey {
517 compatible = "fsl,sec-v4.0-pwrkey";
518 regmap = <&snvs>;
519 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
520 linux,keycode = <KEY_POWER>;
521 wakeup-source;
522 };
5b032872
AH		 523 };
524
a5fcccbc
FL		 525 epit1: epit@020d0000 {
526 reg = <0x020d0000 0x4000>;
527 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
528 };
529
530 epit2: epit@020d4000 {
531 reg = <0x020d4000 0x4000>;
532 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
533 };
534
535 src: src@020d8000 {
536 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
537 reg = <0x020d8000 0x4000>;
538 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
540 #reset-cells = <1>;
541 };
542
543 gpc: gpc@020dc000 {
544 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
545 reg = <0x020dc000 0x4000>;
18619ff5
AH		 546 interrupt-controller;
547 #interrupt-cells = <3>;
a5fcccbc 548 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
18619ff5 549 interrupt-parent = <&intc>;
a5fcccbc
FL		 550 };
551
552 iomuxc: iomuxc@020e0000 {
553 compatible = "fsl,imx6ul-iomuxc";
554 reg = <0x020e0000 0x4000>;
555 };
556
557 gpr: iomuxc-gpr@020e4000 {
558 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
559 reg = <0x020e4000 0x4000>;
560 };
561
562 gpt2: gpt@020e8000 {
563 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
564 reg = <0x020e8000 0x4000>;
565 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
d97ca99f
LW		 566 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
567 <&clks IMX6UL_CLK_GPT2_SERIAL>;
a5fcccbc
FL		 568 clock-names = "ipg", "per";
569 };
570
76758c6a
LW		 571 sdma: sdma@020ec000 {
572 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
573 "fsl,imx35-sdma";
574 reg = <0x020ec000 0x4000>;
575 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&clks IMX6UL_CLK_SDMA>,
577 <&clks IMX6UL_CLK_SDMA>;
578 clock-names = "ipg", "ahb";
579 #dma-cells = <3>;
580 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
581 };
582
a5fcccbc
FL		 583 pwm5: pwm@020f0000 {
584 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
585 reg = <0x020f0000 0x4000>;
586 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 587 clocks = <&clks IMX6UL_CLK_PWM5>,
588 <&clks IMX6UL_CLK_PWM5>;
a5fcccbc
FL		 589 clock-names = "ipg", "per";
590 #pwm-cells = <2>;
dd135095 591 status = "disabled";
a5fcccbc
FL		 592 };
593
594 pwm6: pwm@020f4000 {
595 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
596 reg = <0x020f4000 0x4000>;
597 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 598 clocks = <&clks IMX6UL_CLK_PWM6>,
599 <&clks IMX6UL_CLK_PWM6>;
a5fcccbc
FL		 600 clock-names = "ipg", "per";
601 #pwm-cells = <2>;
dd135095 602 status = "disabled";
a5fcccbc
FL		 603 };
604
605 pwm7: pwm@020f8000 {
606 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
607 reg = <0x020f8000 0x4000>;
608 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 609 clocks = <&clks IMX6UL_CLK_PWM7>,
610 <&clks IMX6UL_CLK_PWM7>;
a5fcccbc
FL		 611 clock-names = "ipg", "per";
612 #pwm-cells = <2>;
dd135095 613 status = "disabled";
a5fcccbc
FL		 614 };
615
616 pwm8: pwm@020fc000 {
617 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
618 reg = <0x020fc000 0x4000>;
619 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 620 clocks = <&clks IMX6UL_CLK_PWM8>,
621 <&clks IMX6UL_CLK_PWM8>;
a5fcccbc
FL		 622 clock-names = "ipg", "per";
623 #pwm-cells = <2>;
dd135095 624 status = "disabled";
a5fcccbc
FL		 625 };
626 };
627
628 aips2: aips-bus@02100000 {
629 compatible = "fsl,aips-bus", "simple-bus";
630 #address-cells = <1>;
631 #size-cells = <1>;
632 reg = <0x02100000 0x100000>;
633 ranges;
634
cad2cb69
FL		 635 usbotg1: usb@02184000 {
636 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
637 reg = <0x02184000 0x200>;
638 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&clks IMX6UL_CLK_USBOH3>;
640 fsl,usbphy = <&usbphy1>;
641 fsl,usbmisc = <&usbmisc 0>;
642 fsl,anatop = <&anatop>;
9493bf54 643 ahb-burst-config = <0x0>;
2b1a40e8
PC		 644 tx-burst-size-dword = <0x10>;
645 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 646 status = "disabled";
647 };
648
649 usbotg2: usb@02184200 {
650 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
651 reg = <0x02184200 0x200>;
652 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX6UL_CLK_USBOH3>;
654 fsl,usbphy = <&usbphy2>;
655 fsl,usbmisc = <&usbmisc 1>;
9493bf54 656 ahb-burst-config = <0x0>;
2b1a40e8
PC		 657 tx-burst-size-dword = <0x10>;
658 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 659 status = "disabled";
660 };
661
662 usbmisc: usbmisc@02184800 {
663 #index-cells = <1>;
664 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
665 reg = <0x02184800 0x200>;
666 };
667
01f3dc7d
FD		 668 fec1: ethernet@02188000 {
669 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
670 reg = <0x02188000 0x4000>;
671 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6UL_CLK_ENET>,
674 <&clks IMX6UL_CLK_ENET_AHB>,
675 <&clks IMX6UL_CLK_ENET_PTP>,
676 <&clks IMX6UL_CLK_ENET_REF>,
677 <&clks IMX6UL_CLK_ENET_REF>;
678 clock-names = "ipg", "ahb", "ptp",
679 "enet_clk_ref", "enet_out";
680 fsl,num-tx-queues=<1>;
681 fsl,num-rx-queues=<1>;
682 status = "disabled";
683 };
684
a5fcccbc
FL		 685 usdhc1: usdhc@02190000 {
686 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
687 reg = <0x02190000 0x4000>;
688 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clks IMX6UL_CLK_USDHC1>,
690 <&clks IMX6UL_CLK_USDHC1>,
691 <&clks IMX6UL_CLK_USDHC1>;
692 clock-names = "ipg", "ahb", "per";
693 bus-width = <4>;
694 status = "disabled";
695 };
696
697 usdhc2: usdhc@02194000 {
698 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
699 reg = <0x02194000 0x4000>;
700 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clks IMX6UL_CLK_USDHC2>,
702 <&clks IMX6UL_CLK_USDHC2>,
703 <&clks IMX6UL_CLK_USDHC2>;
704 clock-names = "ipg", "ahb", "per";
705 bus-width = <4>;
706 status = "disabled";
707 };
708
aab8ec0c
FE		 709 adc1: adc@02198000 {
710 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
711 reg = <0x02198000 0x4000>;
712 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX6UL_CLK_ADC1>;
714 num-channels = <2>;
715 clock-names = "adc";
716 fsl,adck-max-frequency = <30000000>, <40000000>,
717 <20000000>;
718 status = "disabled";
719 };
720
a5fcccbc
FL		 721 i2c1: i2c@021a0000 {
722 #address-cells = <1>;
723 #size-cells = <0>;
724 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
725 reg = <0x021a0000 0x4000>;
726 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clks IMX6UL_CLK_I2C1>;
728 status = "disabled";
729 };
730
731 i2c2: i2c@021a4000 {
732 #address-cells = <1>;
733 #size-cells = <0>;
734 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
735 reg = <0x021a4000 0x4000>;
736 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clks IMX6UL_CLK_I2C2>;
738 status = "disabled";
739 };
740
741 i2c3: i2c@021a8000 {
742 #address-cells = <1>;
743 #size-cells = <0>;
744 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
745 reg = <0x021a8000 0x4000>;
746 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clks IMX6UL_CLK_I2C3>;
748 status = "disabled";
749 };
750
51a37443
AH		 751 mmdc: mmdc@021b0000 {
752 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
753 reg = <0x021b0000 0x4000>;
754 };
755
5ff807a5
FL		 756 qspi: qspi@021e0000 {
757 #address-cells = <1>;
758 #size-cells = <0>;
759 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
760 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
761 reg-names = "QuadSPI", "QuadSPI-memory";
762 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX6UL_CLK_QSPI>,
764 <&clks IMX6UL_CLK_QSPI>;
765 clock-names = "qspi_en", "qspi";
766 status = "disabled";
767 };
768
a5fcccbc
FL		 769 uart2: serial@021e8000 {
770 compatible = "fsl,imx6ul-uart",
771 "fsl,imx6q-uart";
772 reg = <0x021e8000 0x4000>;
773 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
775 <&clks IMX6UL_CLK_UART2_SERIAL>;
776 clock-names = "ipg", "per";
777 status = "disabled";
778 };
779
780 uart3: serial@021ec000 {
781 compatible = "fsl,imx6ul-uart",
782 "fsl,imx6q-uart";
783 reg = <0x021ec000 0x4000>;
784 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
786 <&clks IMX6UL_CLK_UART3_SERIAL>;
787 clock-names = "ipg", "per";
788 status = "disabled";
789 };
790
791 uart4: serial@021f0000 {
792 compatible = "fsl,imx6ul-uart",
793 "fsl,imx6q-uart";
794 reg = <0x021f0000 0x4000>;
795 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
797 <&clks IMX6UL_CLK_UART4_SERIAL>;
798 clock-names = "ipg", "per";
799 status = "disabled";
800 };
801
802 uart5: serial@021f4000 {
803 compatible = "fsl,imx6ul-uart",
804 "fsl,imx6q-uart";
805 reg = <0x021f4000 0x4000>;
806 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
808 <&clks IMX6UL_CLK_UART5_SERIAL>;
809 clock-names = "ipg", "per";
810 status = "disabled";
811 };
812
813 i2c4: i2c@021f8000 {
814 #address-cells = <1>;
815 #size-cells = <0>;
816 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
817 reg = <0x021f8000 0x4000>;
818 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6UL_CLK_I2C4>;
820 status = "disabled";
821 };
822
823 uart6: serial@021fc000 {
824 compatible = "fsl,imx6ul-uart",
825 "fsl,imx6q-uart";
826 reg = <0x021fc000 0x4000>;
827 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
829 <&clks IMX6UL_CLK_UART6_SERIAL>;
830 clock-names = "ipg", "per";
831 status = "disabled";
832 };
833 };
834 };
835};
Linux kernel - Deliverables
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