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470f269c IL |
1 | /* |
2 | * Support for CompuLab CL-SOM-iMX7 System-on-Module | |
3 | * | |
4 | * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ | |
5 | * Author: Ilya Ledvich <ilya@compulab.co.il> | |
6 | * | |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
14 | ||
15 | #include <dt-bindings/input/input.h> | |
16 | #include "imx7d.dtsi" | |
17 | ||
18 | / { | |
19 | model = "CompuLab CL-SOM-iMX7"; | |
20 | compatible = "compulab,cl-som-imx7", "fsl,imx7d"; | |
21 | ||
22 | memory { | |
23 | reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ | |
24 | }; | |
25 | ||
26 | reg_usb_otg1_vbus: regulator-vbus { | |
27 | compatible = "regulator-fixed"; | |
28 | regulator-name = "usb_otg1_vbus"; | |
29 | regulator-min-microvolt = <5000000>; | |
30 | regulator-max-microvolt = <5000000>; | |
31 | gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; | |
32 | enable-active-high; | |
33 | }; | |
34 | }; | |
35 | ||
36 | &cpu0 { | |
37 | arm-supply = <&sw1a_reg>; | |
38 | }; | |
39 | ||
40 | &fec1 { | |
41 | pinctrl-names = "default"; | |
42 | pinctrl-0 = <&pinctrl_enet1>; | |
43 | assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, | |
44 | <&clks IMX7D_ENET1_TIME_ROOT_CLK>; | |
45 | assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; | |
46 | assigned-clock-rates = <0>, <100000000>; | |
47 | phy-mode = "rgmii"; | |
48 | phy-handle = <ðphy0>; | |
49 | fsl,magic-packet; | |
50 | status = "okay"; | |
51 | ||
52 | mdio { | |
53 | #address-cells = <1>; | |
54 | #size-cells = <0>; | |
55 | ||
56 | ethphy0: ethernet-phy@0 { | |
57 | reg = <0>; | |
58 | }; | |
59 | ||
60 | ethphy1: ethernet-phy@1 { | |
61 | reg = <1>; | |
62 | }; | |
63 | }; | |
64 | }; | |
65 | ||
66 | &fec2 { | |
67 | pinctrl-names = "default"; | |
68 | pinctrl-0 = <&pinctrl_enet2>; | |
69 | assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, | |
70 | <&clks IMX7D_ENET2_TIME_ROOT_CLK>; | |
71 | assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; | |
72 | assigned-clock-rates = <0>, <100000000>; | |
73 | phy-mode = "rgmii"; | |
74 | phy-handle = <ðphy1>; | |
75 | fsl,magic-packet; | |
76 | status = "okay"; | |
77 | }; | |
78 | ||
79 | &i2c2 { | |
80 | pinctrl-names = "default"; | |
81 | pinctrl-0 = <&pinctrl_i2c2>; | |
82 | status = "okay"; | |
83 | ||
84 | pmic: pmic@8 { | |
85 | compatible = "fsl,pfuze3000"; | |
86 | reg = <0x08>; | |
87 | ||
88 | regulators { | |
89 | sw1a_reg: sw1a { | |
90 | regulator-min-microvolt = <700000>; | |
91 | regulator-max-microvolt = <1475000>; | |
92 | regulator-boot-on; | |
93 | regulator-always-on; | |
94 | regulator-ramp-delay = <6250>; | |
95 | }; | |
96 | ||
97 | /* use sw1c_reg to align with pfuze100/pfuze200 */ | |
98 | sw1c_reg: sw1b { | |
99 | regulator-min-microvolt = <700000>; | |
100 | regulator-max-microvolt = <1475000>; | |
101 | regulator-boot-on; | |
102 | regulator-always-on; | |
103 | regulator-ramp-delay = <6250>; | |
104 | }; | |
105 | ||
106 | sw2_reg: sw2 { | |
107 | regulator-min-microvolt = <1500000>; | |
108 | regulator-max-microvolt = <1850000>; | |
109 | regulator-boot-on; | |
110 | regulator-always-on; | |
111 | }; | |
112 | ||
113 | sw3a_reg: sw3 { | |
114 | regulator-min-microvolt = <900000>; | |
115 | regulator-max-microvolt = <1650000>; | |
116 | regulator-boot-on; | |
117 | regulator-always-on; | |
118 | }; | |
119 | ||
120 | swbst_reg: swbst { | |
121 | regulator-min-microvolt = <5000000>; | |
122 | regulator-max-microvolt = <5150000>; | |
123 | }; | |
124 | ||
125 | snvs_reg: vsnvs { | |
126 | regulator-min-microvolt = <1000000>; | |
127 | regulator-max-microvolt = <3000000>; | |
128 | regulator-boot-on; | |
129 | regulator-always-on; | |
130 | }; | |
131 | ||
132 | vref_reg: vrefddr { | |
133 | regulator-boot-on; | |
134 | regulator-always-on; | |
135 | }; | |
136 | ||
137 | vgen1_reg: vldo1 { | |
138 | regulator-min-microvolt = <1800000>; | |
139 | regulator-max-microvolt = <3300000>; | |
140 | regulator-always-on; | |
141 | }; | |
142 | ||
143 | vgen2_reg: vldo2 { | |
144 | regulator-min-microvolt = <800000>; | |
145 | regulator-max-microvolt = <1550000>; | |
146 | }; | |
147 | ||
148 | vgen3_reg: vccsd { | |
149 | regulator-min-microvolt = <2850000>; | |
150 | regulator-max-microvolt = <3300000>; | |
151 | regulator-always-on; | |
152 | }; | |
153 | ||
154 | vgen4_reg: v33 { | |
155 | regulator-min-microvolt = <2850000>; | |
156 | regulator-max-microvolt = <3300000>; | |
157 | regulator-always-on; | |
158 | }; | |
159 | ||
160 | vgen5_reg: vldo3 { | |
161 | regulator-min-microvolt = <1800000>; | |
162 | regulator-max-microvolt = <3300000>; | |
163 | regulator-always-on; | |
164 | }; | |
165 | ||
166 | vgen6_reg: vldo4 { | |
167 | regulator-min-microvolt = <1800000>; | |
168 | regulator-max-microvolt = <3300000>; | |
169 | regulator-always-on; | |
170 | }; | |
171 | }; | |
172 | }; | |
173 | ||
174 | pca9555: pca9555@20 { | |
175 | compatible = "nxp,pca9555"; | |
176 | gpio-controller; | |
177 | #gpio-cells = <2>; | |
178 | reg = <0x20>; | |
179 | }; | |
180 | ||
181 | eeprom@50 { | |
182 | compatible = "atmel,24c08"; | |
183 | reg = <0x50>; | |
184 | pagesize = <16>; | |
185 | }; | |
186 | }; | |
187 | ||
188 | &uart1 { | |
189 | pinctrl-names = "default"; | |
190 | pinctrl-0 = <&pinctrl_uart1>; | |
191 | assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; | |
192 | assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; | |
193 | status = "okay"; | |
194 | }; | |
195 | ||
196 | &usbotg1 { | |
197 | pinctrl-names = "default"; | |
198 | pinctrl-0 = <&pinctrl_usbotg1>; | |
199 | vbus-supply = <®_usb_otg1_vbus>; | |
200 | status = "okay"; | |
201 | }; | |
202 | ||
203 | &usdhc3 { | |
204 | pinctrl-names = "default"; | |
205 | pinctrl-0 = <&pinctrl_usdhc3>; | |
206 | assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; | |
207 | assigned-clock-rates = <400000000>; | |
208 | bus-width = <8>; | |
209 | fsl,tuning-step = <2>; | |
210 | non-removable; | |
211 | status = "okay"; | |
212 | }; | |
213 | ||
214 | &iomuxc { | |
215 | pinctrl_enet1: enet1grp { | |
216 | fsl,pins = < | |
217 | MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 | |
218 | MX7D_PAD_SD2_WP__ENET1_MDC 0x3 | |
219 | MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 | |
220 | MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 | |
221 | MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 | |
222 | MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 | |
223 | MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 | |
224 | MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 | |
225 | MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 | |
226 | MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 | |
227 | MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 | |
228 | MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 | |
229 | MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 | |
230 | MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 | |
231 | >; | |
232 | }; | |
233 | ||
234 | pinctrl_enet2: enet2grp { | |
235 | fsl,pins = < | |
236 | MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 | |
237 | MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 | |
238 | MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 | |
239 | MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 | |
240 | MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 | |
241 | MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 | |
242 | MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 | |
243 | MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 | |
244 | MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 | |
245 | MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 | |
246 | MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 | |
247 | MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 | |
248 | >; | |
249 | }; | |
250 | ||
251 | pinctrl_i2c2: i2c2grp { | |
252 | fsl,pins = < | |
253 | MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f | |
254 | MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f | |
255 | >; | |
256 | }; | |
257 | ||
258 | pinctrl_uart1: uart1grp { | |
259 | fsl,pins = < | |
260 | MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 | |
261 | MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 | |
262 | >; | |
263 | }; | |
264 | ||
265 | pinctrl_usbotg1: usbotg1grp { | |
266 | fsl,pins = < | |
267 | MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ | |
268 | >; | |
269 | }; | |
270 | ||
271 | pinctrl_usdhc3: usdhc3grp { | |
272 | fsl,pins = < | |
273 | MX7D_PAD_SD3_CMD__SD3_CMD 0x59 | |
274 | MX7D_PAD_SD3_CLK__SD3_CLK 0x19 | |
275 | MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 | |
276 | MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 | |
277 | MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 | |
278 | MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 | |
279 | MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 | |
280 | MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 | |
281 | MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 | |
282 | MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 | |
283 | MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 | |
284 | >; | |
285 | }; | |
286 | }; |