Commit | Line | Data |
---|---|---|
4980f9bc LW |
1 | /* |
2 | * Device Tree for the ARM Integrator/AP platform | |
3 | */ | |
4 | ||
5 | /dts-v1/; | |
6 | /include/ "integrator.dtsi" | |
7 | ||
8 | / { | |
9 | model = "ARM Integrator/AP"; | |
10 | compatible = "arm,integrator-ap"; | |
11 | ||
12 | aliases { | |
13 | arm,timer-primary = &timer2; | |
14 | arm,timer-secondary = &timer1; | |
15 | }; | |
16 | ||
17 | chosen { | |
18 | bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; | |
19 | }; | |
20 | ||
e67ae6be LW |
21 | syscon { |
22 | /* AP system controller registers */ | |
23 | reg = <0x11000000 0x100>; | |
24 | }; | |
25 | ||
4980f9bc LW |
26 | timer0: timer@13000000 { |
27 | compatible = "arm,integrator-timer"; | |
28 | }; | |
29 | ||
30 | timer1: timer@13000100 { | |
31 | compatible = "arm,integrator-timer"; | |
32 | }; | |
33 | ||
34 | timer2: timer@13000200 { | |
35 | compatible = "arm,integrator-timer"; | |
36 | }; | |
37 | ||
38 | pic: pic@14000000 { | |
39 | valid-mask = <0x003fffff>; | |
40 | }; | |
4672cddf | 41 | |
f55b2b56 LW |
42 | pci: pciv3@62000000 { |
43 | compatible = "v3,v360epc-pci"; | |
44 | #interrupt-cells = <1>; | |
45 | #size-cells = <2>; | |
46 | #address-cells = <3>; | |
47 | reg = <0x62000000 0x10000>; | |
48 | interrupt-parent = <&pic>; | |
49 | interrupts = <17>; /* Bus error IRQ */ | |
50 | ranges = <0x00000000 0 0x61000000 /* config space */ | |
51 | 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ | |
56ce3ffb | 52 | 0x01000000 0 0x0 /* I/O space */ |
f55b2b56 | 53 | 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ |
56ce3ffb | 54 | 0x02000000 0 0x00000000 /* non-prefectable memory */ |
f55b2b56 | 55 | 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ |
56ce3ffb | 56 | 0x42000000 0 0x10000000 /* prefetchable memory */ |
f55b2b56 LW |
57 | 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ |
58 | interrupt-map-mask = <0xf800 0 0 0x7>; | |
59 | interrupt-map = < | |
60 | /* IDSEL 9 */ | |
61 | 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ | |
62 | 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ | |
63 | 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ | |
64 | 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ | |
65 | /* IDSEL 10 */ | |
66 | 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ | |
67 | 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ | |
68 | 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ | |
69 | 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ | |
70 | /* IDSEL 11 */ | |
71 | 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ | |
72 | 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ | |
73 | 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ | |
74 | 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ | |
75 | /* IDSEL 12 */ | |
76 | 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ | |
77 | 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ | |
78 | 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ | |
79 | 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ | |
80 | >; | |
81 | }; | |
82 | ||
4672cddf LW |
83 | fpga { |
84 | /* | |
85 | * The Integator/AP predates the idea to have magic numbers | |
86 | * identifying the PrimeCell in hardware, thus we have to | |
87 | * supply these from the device tree. | |
88 | */ | |
89 | rtc: rtc@15000000 { | |
90 | compatible = "arm,pl030", "arm,primecell"; | |
91 | arm,primecell-periphid = <0x00041030>; | |
92 | }; | |
93 | ||
94 | uart0: uart@16000000 { | |
95 | compatible = "arm,pl010", "arm,primecell"; | |
96 | arm,primecell-periphid = <0x00041010>; | |
97 | }; | |
98 | ||
99 | uart1: uart@17000000 { | |
100 | compatible = "arm,pl010", "arm,primecell"; | |
101 | arm,primecell-periphid = <0x00041010>; | |
102 | }; | |
103 | ||
104 | kmi0: kmi@18000000 { | |
105 | compatible = "arm,pl050", "arm,primecell"; | |
106 | arm,primecell-periphid = <0x00041050>; | |
107 | }; | |
108 | ||
109 | kmi1: kmi@19000000 { | |
110 | compatible = "arm,pl050", "arm,primecell"; | |
111 | arm,primecell-periphid = <0x00041050>; | |
112 | }; | |
113 | }; | |
4980f9bc | 114 | }; |