[deliverable/linux.git] / arch / arm / boot / dts / keystone.dtsi

/*
 * Copyright 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,keystone";
	model = "Texas Instruments Keystone 2 SoC";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	= &uart0;
	};

	memory {
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x02561000 0x0 0x1000>,
		      <0x0 0x02562000 0x0 0x2000>,
		      <0x0 0x02564000 0x0 0x1000>,
		      <0x0 0x02566000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;

		pllctrl: pll-controller@02310000 {
			compatible = "ti,keystone-pllctrl", "syscon";
			reg = <0x02310000 0x200>;
		};

		devctrl: device-state-control@02620000 {
			compatible = "ti,keystone-devctrl", "syscon";
			reg = <0x02620000 0x1000>;
		};

		rstctrl: reset-controller {
			compatible = "ti,keystone-reset";
			ti,syscon-pll = <&pllctrl 0xe4>;
			ti,syscon-dev = <&devctrl 0x328>;
			ti,wdt-list = <0>;
		};

		/include/ "keystone-clocks.dtsi"

		uart0: serial@02530c00 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			clocks	= <&clkuart0>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
		};

		uart1:	serial@02531000 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			clocks	= <&clkuart1>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
		};

		i2c0: i2c@2530000 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530000 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@2530400 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530400 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@2530800 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530800 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@21000400 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000400 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@21000600 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000600 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi2: spi@21000800 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000800 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_phy: usb_phy@2620738 {
			compatible = "ti,keystone-usbphy";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2620738 24>;
			status = "disabled";
		};

		usb: usb@2680000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2680000 0x10000>;
			clocks = <&clkusb>;
			clock-names = "usb";
			interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";

			dwc3@2690000 {
				compatible = "synopsys,dwc3";
				reg = <0x2690000 0x70000>;
				interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
				usb-phy = <&usb_phy>, <&usb_phy>;
			};
		};

		wdt: wdt@022f0080 {
			compatible = "ti,keystone-wdt","ti,davinci-wdt";
			reg = <0x022f0080 0x80>;
			clocks = <&clkwdtimer0>;
		};

		clock_event: timer@22f0000 {
			compatible = "ti,keystone-timer";
			reg = <0x022f0000 0x80>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clktimer15>;
		};

		gpio0: gpio@260bf00 {
			compatible = "ti,keystone-gpio";
			reg = <0x0260bf00 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			/* HW Interrupts mapped to GPIO pins */
			interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkgpio>;
			clock-names = "gpio";
			ti,ngpio = <32>;
			ti,davinci-gpio-unbanked = <32>;
		};

		aemif: aemif@21000A00 {
			compatible = "ti,keystone-aemif", "ti,davinci-aemif";
			#address-cells = <2>;
			#size-cells = <1>;
			clocks = <&clkaemif>;
			clock-names = "aemif";
			clock-ranges;

			reg = <0x21000A00 0x00000100>;
			ranges = <0 0 0x30000000 0x10000000
				  1 0 0x21000A00 0x00000100>;
		};

		kirq0: keystone_irq@26202a0 {
			compatible = "ti,keystone-irq";
			interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,syscon-dev = <&devctrl 0x2a0>;
		};

		pcie0: pcie@21800000 {
			compatible = "ti,keystone-pcie", "snps,dw-pcie";
			clocks = <&clkpcie>;
			clock-names = "pcie";
			#address-cells = <3>;
			#size-cells = <2>;
			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
			ranges = <0x81000000 0 0 0x23250000 0 0x4000
				0x82000000 0 0x50000000 0x50000000 0 0x10000000>;

			status = "disabled";
			device_type = "pci";
			num-lanes = <2>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
					<0 0 0 2 &pcie_intc0 1>, /* INT B */
					<0 0 0 3 &pcie_intc0 2>, /* INT C */
					<0 0 0 4 &pcie_intc0 3>; /* INT D */

			pcie_msi_intc0: msi-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
			};

			pcie_intc0: legacy-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
			};
		};
	};
};
Commit	Line	Data
d5e9fe84 SS	1	/*
	2	* Copyright 2013 Texas Instruments, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
eb788f43	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
970c2256	10	#include <dt-bindings/gpio/gpio.h>
eb788f43	11
226d1c5b	12	#include "skeleton.dtsi"
d5e9fe84 SS	13
d5e9fe84 SS	14	/ {
91dca0f0	15	compatible = "ti,keystone";
d5e9fe84	16	model = "Texas Instruments Keystone 2 SoC";
d5e9fe84 SS	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	interrupt-parent = <&gic>;
	20
	21	aliases {
	22	serial0 = &uart0;
	23	};
	24
	25	memory {
	26	reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	27	};
	28
d5e9fe84 SS	29	gic: interrupt-controller {
	30	compatible = "arm,cortex-a15-gic";
	31	#interrupt-cells = <3>;
d5e9fe84 SS	32	interrupt-controller;
d5e9fe84 SS	33	reg = <0x0 0x02561000 0x0 0x1000>,
a18b4aa2 SS	34	<0x0 0x02562000 0x0 0x2000>,
	35	<0x0 0x02564000 0x0 0x1000>,
	36	<0x0 0x02566000 0x0 0x2000>;
0ee15444 SS	37	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
0ee15444 SS	38	IRQ_TYPE_LEVEL_HIGH)>;
d5e9fe84 SS	39	};
	40
	41	timer {
	42	compatible = "arm,armv7-timer";
eb788f43 SS	43	interrupts =
	44	<GIC_PPI 13
	45	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	46	<GIC_PPI 14
	47	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	48	<GIC_PPI 11
	49	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	50	<GIC_PPI 10
	51	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
d5e9fe84 SS	52	};
	53
	54	pmu {
	55	compatible = "arm,cortex-a15-pmu";
eb788f43 SS	56	interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
	57	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	58	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
	59	<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	60	};
	61
	62	soc {
	63	#address-cells = <1>;
	64	#size-cells = <1>;
	65	compatible = "ti,keystone","simple-bus";
	66	interrupt-parent = <&gic>;
	67	ranges = <0x0 0x0 0x0 0xc0000000>;
4d46596d	68	dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
d5e9fe84	69
ded79beb IK	70	pllctrl: pll-controller@02310000 {
	71	compatible = "ti,keystone-pllctrl", "syscon";
	72	reg = <0x02310000 0x200>;
	73	};
	74
	75	devctrl: device-state-control@02620000 {
	76	compatible = "ti,keystone-devctrl", "syscon";
	77	reg = <0x02620000 0x1000>;
	78	};
	79
d5e9fe84 SS	80	rstctrl: reset-controller {
d5e9fe84 SS	81	compatible = "ti,keystone-reset";
ded79beb IK	82	ti,syscon-pll = <&pllctrl 0xe4>;
	83	ti,syscon-dev = <&devctrl 0x328>;
	84	ti,wdt-list = <0>;
d5e9fe84 SS	85	};
d5e9fe84 SS	86
feeea8f3 SS	87	/include/ "keystone-clocks.dtsi"
feeea8f3 SS	88
d5e9fe84 SS	89	uart0: serial@02530c00 {
	90	compatible = "ns16550a";
	91	current-speed = <115200>;
	92	reg-shift = <2>;
	93	reg-io-width = <4>;
	94	reg = <0x02530c00 0x100>;
f023bd10	95	clocks = <&clkuart0>;
eb788f43	96	interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	97	};
	98
	99	uart1: serial@02531000 {
	100	compatible = "ns16550a";
	101	current-speed = <115200>;
	102	reg-shift = <2>;
	103	reg-io-width = <4>;
	104	reg = <0x02531000 0x100>;
f023bd10	105	clocks = <&clkuart1>;
eb788f43	106	interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	107	};
d5e9fe84 SS	108
6120ac23 SS	109	i2c0: i2c@2530000 {
	110	compatible = "ti,davinci-i2c";
	111	reg = <0x02530000 0x400>;
	112	clock-frequency = <100000>;
	113	clocks = <&clki2c>;
	114	interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
	115	#address-cells = <1>;
	116	#size-cells = <0>;
6120ac23 SS	117	};
	118
	119	i2c1: i2c@2530400 {
	120	compatible = "ti,davinci-i2c";
	121	reg = <0x02530400 0x400>;
	122	clock-frequency = <100000>;
	123	clocks = <&clki2c>;
	124	interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
3953505a GS	125	#address-cells = <1>;
3953505a GS	126	#size-cells = <0>;
6120ac23 SS	127	};
	128
	129	i2c2: i2c@2530800 {
	130	compatible = "ti,davinci-i2c";
	131	reg = <0x02530800 0x400>;
	132	clock-frequency = <100000>;
	133	clocks = <&clki2c>;
	134	interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
3953505a GS	135	#address-cells = <1>;
3953505a GS	136	#size-cells = <0>;
6120ac23	137	};
b3bd6c59 SS	138
b3bd6c59 SS	139	spi0: spi@21000400 {
1a344e9b	140	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	141	reg = <0x21000400 0x200>;
	142	num-cs = <4>;
	143	ti,davinci-spi-intr-line = <0>;
	144	interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
	145	clocks = <&clkspi>;
509046a7 GS	146	#address-cells = <1>;
509046a7 GS	147	#size-cells = <0>;
b3bd6c59 SS	148	};
	149
	150	spi1: spi@21000600 {
1a344e9b	151	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	152	reg = <0x21000600 0x200>;
	153	num-cs = <4>;
	154	ti,davinci-spi-intr-line = <0>;
	155	interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
	156	clocks = <&clkspi>;
509046a7 GS	157	#address-cells = <1>;
509046a7 GS	158	#size-cells = <0>;
b3bd6c59 SS	159	};
	160
	161	spi2: spi@21000800 {
1a344e9b	162	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	163	reg = <0x21000800 0x200>;
	164	num-cs = <4>;
	165	ti,davinci-spi-intr-line = <0>;
	166	interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
	167	clocks = <&clkspi>;
509046a7 GS	168	#address-cells = <1>;
509046a7 GS	169	#size-cells = <0>;
b3bd6c59	170	};
08c36762 WK	171
	172	usb_phy: usb_phy@2620738 {
	173	compatible = "ti,keystone-usbphy";
	174	#address-cells = <1>;
	175	#size-cells = <1>;
cfb198ce	176	reg = <0x2620738 24>;
08c36762 WK	177	status = "disabled";
08c36762 WK	178	};
73207956 WK	179
	180	usb: usb@2680000 {
	181	compatible = "ti,keystone-dwc3";
	182	#address-cells = <1>;
	183	#size-cells = <1>;
	184	reg = <0x2680000 0x10000>;
	185	clocks = <&clkusb>;
	186	clock-names = "usb";
	187	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	188	ranges;
86156978 SS	189	dma-coherent;
86156978 SS	190	dma-ranges;
73207956 WK	191	status = "disabled";
	192
	193	dwc3@2690000 {
	194	compatible = "synopsys,dwc3";
	195	reg = <0x2690000 0x70000>;
	196	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	197	usb-phy = <&usb_phy>, <&usb_phy>;
	198	};
	199	};
20d89313 IK	200
	201	wdt: wdt@022f0080 {
	202	compatible = "ti,keystone-wdt","ti,davinci-wdt";
	203	reg = <0x022f0080 0x80>;
	204	clocks = <&clkwdtimer0>;
	205	};
2b4f76b6 IK	206
	207	clock_event: timer@22f0000 {
	208	compatible = "ti,keystone-timer";
	209	reg = <0x022f0000 0x80>;
	210	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
	211	clocks = <&clktimer15>;
	212	};
970c2256 GS	213
	214	gpio0: gpio@260bf00 {
	215	compatible = "ti,keystone-gpio";
	216	reg = <0x0260bf00 0x100>;
	217	gpio-controller;
	218	#gpio-cells = <2>;
	219	/* HW Interrupts mapped to GPIO pins */
	220	interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
	221	<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
	222	<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
	223	<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
	224	<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
	225	<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
	226	<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
	227	<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
	228	<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
	229	<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
	230	<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
	231	<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
	232	<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
	233	<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
	234	<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
	235	<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
	236	<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
	237	<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
	238	<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
	239	<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
	240	<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
	241	<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
	242	<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
	243	<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
	244	<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
	245	<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
	246	<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
	247	<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
	248	<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
	249	<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
	250	<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
	251	<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
	252	clocks = <&clkgpio>;
	253	clock-names = "gpio";
	254	ti,ngpio = <32>;
	255	ti,davinci-gpio-unbanked = <32>;
	256	};
82c04f71 IK	257
	258	aemif: aemif@21000A00 {
	259	compatible = "ti,keystone-aemif", "ti,davinci-aemif";
	260	#address-cells = <2>;
	261	#size-cells = <1>;
	262	clocks = <&clkaemif>;
	263	clock-names = "aemif";
	264	clock-ranges;
	265
	266	reg = <0x21000A00 0x00000100>;
	267	ranges = <0 0 0x30000000 0x10000000
	268	1 0 0x21000A00 0x00000100>;
	269	};
979c36c8	270
a392d42d GS	271	kirq0: keystone_irq@26202a0 {
	272	compatible = "ti,keystone-irq";
	273	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
	274	interrupt-controller;
	275	#interrupt-cells = <1>;
	276	ti,syscon-dev = <&devctrl 0x2a0>;
	277	};
bed80507	278
8b4769cc	279	pcie0: pcie@21800000 {
bed80507 MK	280	compatible = "ti,keystone-pcie", "snps,dw-pcie";
	281	clocks = <&clkpcie>;
	282	clock-names = "pcie";
	283	#address-cells = <3>;
	284	#size-cells = <2>;
	285	reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
	286	ranges = <0x81000000 0 0 0x23250000 0 0x4000
	287	0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
	288
9dd4f28f	289	status = "disabled";
bed80507 MK	290	device_type = "pci";
	291	num-lanes = <2>;
	292
	293	#interrupt-cells = <1>;
	294	interrupt-map-mask = <0 0 0 7>;
	295	interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
	296	<0 0 0 2 &pcie_intc0 1>, /* INT B */
	297	<0 0 0 3 &pcie_intc0 2>, /* INT C */
	298	<0 0 0 4 &pcie_intc0 3>; /* INT D */
	299
	300	pcie_msi_intc0: msi-interrupt-controller {
	301	interrupt-controller;
	302	#interrupt-cells = <1>;
	303	interrupt-parent = <&gic>;
	304	interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
	305	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
	306	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
	307	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
	308	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
	309	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
	310	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
	311	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	312	};
	313
	314	pcie_intc0: legacy-interrupt-controller {
	315	interrupt-controller;
	316	#interrupt-cells = <1>;
	317	interrupt-parent = <&gic>;
	318	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
	319	<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
	320	<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
	321	<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	322	};
	323	};
d5e9fe84 SS	324	};
d5e9fe84 SS	325	};