Commit | Line | Data |
---|---|---|
82bb2da1 AL |
1 | / { |
2 | ocp@f1000000 { | |
3 | pinctrl: pinctrl@10000 { | |
4 | compatible = "marvell,88f6281-pinctrl"; | |
5 | reg = <0x10000 0x20>; | |
6 | ||
7 | pmx_nand: pmx-nand { | |
8 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | |
9 | "mpp4", "mpp5", "mpp18", | |
10 | "mpp19"; | |
11 | marvell,function = "nand"; | |
12 | }; | |
13 | pmx_sata0: pmx-sata0 { | |
14 | marvell,pins = "mpp5", "mpp21", "mpp23"; | |
15 | marvell,function = "sata0"; | |
16 | }; | |
17 | pmx_sata1: pmx-sata1 { | |
18 | marvell,pins = "mpp4", "mpp20", "mpp22"; | |
19 | marvell,function = "sata1"; | |
20 | }; | |
21 | pmx_spi: pmx-spi { | |
22 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | |
23 | marvell,function = "spi"; | |
24 | }; | |
25 | pmx_twsi0: pmx-twsi0 { | |
26 | marvell,pins = "mpp8", "mpp9"; | |
27 | marvell,function = "twsi0"; | |
28 | }; | |
29 | pmx_uart0: pmx-uart0 { | |
30 | marvell,pins = "mpp10", "mpp11"; | |
31 | marvell,function = "uart0"; | |
32 | }; | |
33 | pmx_uart1: pmx-uart1 { | |
34 | marvell,pins = "mpp13", "mpp14"; | |
35 | marvell,function = "uart1"; | |
36 | }; | |
de64ee5e SP |
37 | pmx_sdio: pmx-sdio { |
38 | marvell,pins = "mpp12", "mpp13", "mpp14", | |
39 | "mpp15", "mpp16", "mpp17"; | |
40 | marvell,function = "sdio"; | |
41 | }; | |
82bb2da1 | 42 | }; |
670ee03c TP |
43 | |
44 | pcie-controller { | |
45 | compatible = "marvell,kirkwood-pcie"; | |
46 | status = "disabled"; | |
47 | device_type = "pci"; | |
48 | ||
49 | #address-cells = <3>; | |
50 | #size-cells = <2>; | |
51 | ||
52 | bus-range = <0x00 0xff>; | |
53 | ||
54 | ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ | |
55 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | |
56 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | |
57 | ||
58 | pcie@1,0 { | |
59 | device_type = "pci"; | |
60 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | |
61 | reg = <0x0800 0 0 0 0>; | |
62 | #address-cells = <3>; | |
63 | #size-cells = <2>; | |
64 | #interrupt-cells = <1>; | |
65 | ranges; | |
66 | interrupt-map-mask = <0 0 0 0>; | |
67 | interrupt-map = <0 0 0 0 &intc 9>; | |
68 | marvell,pcie-port = <0>; | |
69 | marvell,pcie-lane = <0>; | |
70 | clocks = <&gate_clk 2>; | |
71 | status = "disabled"; | |
72 | }; | |
73 | }; | |
ee1a8d40 | 74 | |
df6bf2e9 VL |
75 | rtc@10300 { |
76 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | |
77 | reg = <0x10300 0x20>; | |
78 | interrupts = <53>; | |
79 | clocks = <&gate_clk 7>; | |
80 | }; | |
81 | ||
82 | sata@80000 { | |
83 | compatible = "marvell,orion-sata"; | |
84 | reg = <0x80000 0x5000>; | |
85 | interrupts = <21>; | |
86 | clocks = <&gate_clk 14>, <&gate_clk 15>; | |
87 | clock-names = "0", "1"; | |
88 | status = "disabled"; | |
89 | }; | |
90 | ||
91 | mvsdio@90000 { | |
92 | compatible = "marvell,orion-sdio"; | |
93 | reg = <0x90000 0x200>; | |
94 | interrupts = <28>; | |
95 | clocks = <&gate_clk 4>; | |
96 | bus-width = <4>; | |
97 | cap-sdio-irq; | |
98 | cap-sd-highspeed; | |
99 | cap-mmc-highspeed; | |
100 | status = "disabled"; | |
101 | }; | |
82bb2da1 | 102 | }; |
de64ee5e | 103 | }; |