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0c2d652f SG |
1 | /* |
2 | * Device Tree file for LaCie 2Big NAS | |
3 | * | |
4 | * Copyright (C) 2015 Seagate | |
5 | * | |
6 | * Author: Simon Guinot <simon.guinot@sequanux.org> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
14 | ||
15 | #include "kirkwood-netxbig.dtsi" | |
16 | ||
17 | / { | |
18 | model = "LaCie 2Big NAS"; | |
19 | compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; | |
20 | ||
21 | memory { | |
22 | device_type = "memory"; | |
23 | reg = <0x00000000 0x10000000>; | |
24 | }; | |
25 | ||
26 | chosen { | |
27 | bootargs = "console=ttyS0,115200n8"; | |
28 | stdout-path = &uart0; | |
29 | }; | |
30 | ||
0c2d652f SG |
31 | ocp@f1000000 { |
32 | rtc@10300 { | |
33 | /* The on-chip RTC is not powered (no supercap). */ | |
34 | status = "disabled"; | |
35 | }; | |
36 | spi@10600 { | |
37 | /* | |
38 | * A NAND flash is used instead of an SPI flash for | |
39 | * the other netxbig-compatible boards. | |
40 | */ | |
41 | status = "disabled"; | |
42 | }; | |
43 | }; | |
44 | ||
45 | fan { | |
46 | /* | |
47 | * An I2C fan controller (GMT G762) is used but alarm is | |
48 | * wired to a separate GPIO. | |
49 | */ | |
50 | compatible = "gpio-fan"; | |
51 | alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; | |
52 | }; | |
53 | ||
54 | regulators: regulators { | |
55 | status = "okay"; | |
56 | compatible = "simple-bus"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | pinctrl-names = "default"; | |
60 | ||
61 | regulator@2 { | |
62 | compatible = "regulator-fixed"; | |
63 | reg = <2>; | |
64 | regulator-name = "hdd1power"; | |
65 | regulator-min-microvolt = <5000000>; | |
66 | regulator-max-microvolt = <5000000>; | |
67 | enable-active-high; | |
68 | regulator-always-on; | |
69 | regulator-boot-on; | |
70 | gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; | |
71 | }; | |
72 | clocks { | |
73 | g762_clk: g762-oscillator { | |
74 | compatible = "fixed-clock"; | |
75 | #clock-cells = <0>; | |
76 | clock-frequency = <32768>; | |
77 | }; | |
78 | }; | |
79 | }; | |
80 | }; | |
81 | ||
82 | &mdio { | |
83 | status = "okay"; | |
84 | ||
85 | ethphy0: ethernet-phy@0 { | |
86 | reg = <0>; | |
87 | }; | |
88 | }; | |
89 | ||
90 | &i2c0 { | |
91 | status = "okay"; | |
92 | ||
93 | /* | |
94 | * An external I2C RTC (Dallas DS1337S+) is used. This allows | |
95 | * to power-up the board on an RTC alarm. The external RTC can | |
96 | * be kept powered, even when the SoC is off. | |
97 | */ | |
98 | rtc@68 { | |
99 | compatible = "dallas,ds1307"; | |
100 | reg = <0x68>; | |
101 | interrupts = <43>; | |
102 | }; | |
103 | g762@3e { | |
104 | compatible = "gmt,g762"; | |
105 | reg = <0x3e>; | |
106 | clocks = <&g762_clk>; | |
107 | }; | |
108 | }; | |
109 | ||
110 | &nand { | |
111 | chip-delay = <50>; | |
112 | status = "okay"; | |
113 | ||
114 | partition@0 { | |
115 | label = "U-Boot"; | |
116 | reg = <0x0 0x100000>; | |
117 | }; | |
118 | ||
119 | partition@100000 { | |
120 | label = "uImage"; | |
121 | reg = <0x100000 0x1000000>; | |
122 | }; | |
123 | ||
124 | partition@1100000 { | |
125 | label = "root"; | |
126 | reg = <0x1100000 0x8000000>; | |
127 | }; | |
128 | ||
129 | partition@9100000 { | |
130 | label = "unused"; | |
131 | reg = <0x9100000 0x6f00000>; | |
132 | }; | |
133 | }; | |
eb13cf83 AL |
134 | |
135 | &pciec { | |
136 | status = "okay"; | |
137 | }; | |
138 | ||
139 | &pcie0 { | |
140 | status = "okay"; | |
141 | }; |