Commit | Line | Data |
---|---|---|
3d468b6d JC |
1 | /include/ "skeleton.dtsi" |
2 | ||
3 | / { | |
77843504 | 4 | compatible = "marvell,kirkwood"; |
278b45b0 AL |
5 | interrupt-parent = <&intc>; |
6 | ||
33a66754 AB |
7 | cpus { |
8 | #address-cells = <1>; | |
9 | #size-cells = <0>; | |
10 | ||
11 | cpu@0 { | |
12 | device_type = "cpu"; | |
13 | compatible = "marvell,feroceon"; | |
14 | clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; | |
15 | clock-names = "cpu_clk", "ddrclk", "powersave"; | |
16 | }; | |
17 | }; | |
18 | ||
f9e75922 AL |
19 | aliases { |
20 | gpio0 = &gpio0; | |
21 | gpio1 = &gpio1; | |
22 | }; | |
278b45b0 AL |
23 | intc: interrupt-controller { |
24 | compatible = "marvell,orion-intc", "marvell,intc"; | |
25 | interrupt-controller; | |
26 | #interrupt-cells = <1>; | |
27 | reg = <0xf1020204 0x04>, | |
28 | <0xf1020214 0x04>; | |
29 | }; | |
3d468b6d | 30 | |
163f2cea JC |
31 | ocp@f1000000 { |
32 | compatible = "simple-bus"; | |
01db527e | 33 | ranges = <0x00000000 0xf1000000 0x0100000 |
670ee03c | 34 | 0xe0000000 0xe0000000 0x8100000 /* PCIE */ |
01db527e | 35 | 0xf4000000 0xf4000000 0x0000400 |
f37fbd36 | 36 | 0xf5000000 0xf5000000 0x0000400>; |
163f2cea JC |
37 | #address-cells = <1>; |
38 | #size-cells = <1>; | |
39 | ||
1611f872 AL |
40 | core_clk: core-clocks@10030 { |
41 | compatible = "marvell,kirkwood-core-clock"; | |
42 | reg = <0x10030 0x4>; | |
43 | #clock-cells = <1>; | |
44 | }; | |
45 | ||
278b45b0 AL |
46 | gpio0: gpio@10100 { |
47 | compatible = "marvell,orion-gpio"; | |
48 | #gpio-cells = <2>; | |
49 | gpio-controller; | |
50 | reg = <0x10100 0x40>; | |
f9e75922 AL |
51 | ngpios = <32>; |
52 | interrupt-controller; | |
09d75bc7 | 53 | #interrupt-cells = <2>; |
278b45b0 | 54 | interrupts = <35>, <36>, <37>, <38>; |
de88747f | 55 | clocks = <&gate_clk 7>; |
278b45b0 AL |
56 | }; |
57 | ||
58 | gpio1: gpio@10140 { | |
59 | compatible = "marvell,orion-gpio"; | |
60 | #gpio-cells = <2>; | |
61 | gpio-controller; | |
62 | reg = <0x10140 0x40>; | |
f9e75922 AL |
63 | ngpios = <18>; |
64 | interrupt-controller; | |
09d75bc7 | 65 | #interrupt-cells = <2>; |
278b45b0 | 66 | interrupts = <39>, <40>, <41>; |
de88747f | 67 | clocks = <&gate_clk 7>; |
278b45b0 AL |
68 | }; |
69 | ||
163f2cea JC |
70 | serial@12000 { |
71 | compatible = "ns16550a"; | |
72 | reg = <0x12000 0x100>; | |
73 | reg-shift = <2>; | |
74 | interrupts = <33>; | |
1611f872 | 75 | clocks = <&gate_clk 7>; |
163f2cea JC |
76 | status = "disabled"; |
77 | }; | |
78 | ||
79 | serial@12100 { | |
80 | compatible = "ns16550a"; | |
81 | reg = <0x12100 0x100>; | |
82 | reg-shift = <2>; | |
83 | interrupts = <34>; | |
1611f872 | 84 | clocks = <&gate_clk 7>; |
163f2cea JC |
85 | status = "disabled"; |
86 | }; | |
e871b87a | 87 | |
76372120 MW |
88 | spi@10600 { |
89 | compatible = "marvell,orion-spi"; | |
90 | #address-cells = <1>; | |
91 | #size-cells = <0>; | |
92 | cell-index = <0>; | |
93 | interrupts = <23>; | |
94 | reg = <0x10600 0x28>; | |
1611f872 | 95 | clocks = <&gate_clk 7>; |
76372120 MW |
96 | status = "disabled"; |
97 | }; | |
98 | ||
1611f872 AL |
99 | gate_clk: clock-gating-control@2011c { |
100 | compatible = "marvell,kirkwood-gating-clock"; | |
101 | reg = <0x2011c 0x4>; | |
102 | clocks = <&core_clk 0>; | |
103 | #clock-cells = <1>; | |
104 | }; | |
105 | ||
1e7bad0f AL |
106 | wdt@20300 { |
107 | compatible = "marvell,orion-wdt"; | |
108 | reg = <0x20300 0x28>; | |
1611f872 | 109 | clocks = <&gate_clk 7>; |
1e7bad0f AL |
110 | status = "okay"; |
111 | }; | |
112 | ||
c896ed0f AL |
113 | xor@60800 { |
114 | compatible = "marvell,orion-xor"; | |
115 | reg = <0x60800 0x100 | |
116 | 0x60A00 0x100>; | |
117 | status = "okay"; | |
118 | clocks = <&gate_clk 8>; | |
119 | ||
120 | xor00 { | |
121 | interrupts = <5>; | |
122 | dmacap,memcpy; | |
123 | dmacap,xor; | |
124 | }; | |
125 | xor01 { | |
126 | interrupts = <6>; | |
127 | dmacap,memcpy; | |
128 | dmacap,xor; | |
129 | dmacap,memset; | |
130 | }; | |
131 | }; | |
132 | ||
133 | xor@60900 { | |
134 | compatible = "marvell,orion-xor"; | |
135 | reg = <0x60900 0x100 | |
136 | 0xd0B00 0x100>; | |
1e7bad0f | 137 | status = "okay"; |
c896ed0f AL |
138 | clocks = <&gate_clk 16>; |
139 | ||
140 | xor00 { | |
141 | interrupts = <7>; | |
142 | dmacap,memcpy; | |
143 | dmacap,xor; | |
144 | }; | |
145 | xor01 { | |
146 | interrupts = <8>; | |
147 | dmacap,memcpy; | |
148 | dmacap,xor; | |
149 | dmacap,memset; | |
150 | }; | |
1e7bad0f AL |
151 | }; |
152 | ||
b6cf8070 AL |
153 | ehci@50000 { |
154 | compatible = "marvell,orion-ehci"; | |
155 | reg = <0x50000 0x1000>; | |
156 | interrupts = <19>; | |
53dfa8e4 | 157 | clocks = <&gate_clk 3>; |
b6cf8070 AL |
158 | status = "okay"; |
159 | }; | |
160 | ||
858156bd JL |
161 | nand@3000000 { |
162 | #address-cells = <1>; | |
163 | #size-cells = <1>; | |
164 | cle = <0>; | |
165 | ale = <1>; | |
166 | bank-width = <1>; | |
77843504 | 167 | compatible = "marvell,orion-nand"; |
01db527e | 168 | reg = <0xf4000000 0x400>; |
858156bd JL |
169 | chip-delay = <25>; |
170 | /* set partition map and/or chip-delay in board dts */ | |
1611f872 | 171 | clocks = <&gate_clk 7>; |
858156bd JL |
172 | status = "disabled"; |
173 | }; | |
e91cac0a AL |
174 | |
175 | i2c@11000 { | |
176 | compatible = "marvell,mv64xxx-i2c"; | |
177 | reg = <0x11000 0x20>; | |
178 | #address-cells = <1>; | |
179 | #size-cells = <0>; | |
180 | interrupts = <29>; | |
181 | clock-frequency = <100000>; | |
1611f872 | 182 | clocks = <&gate_clk 7>; |
e91cac0a AL |
183 | status = "disabled"; |
184 | }; | |
f37fbd36 AL |
185 | |
186 | crypto@30000 { | |
187 | compatible = "marvell,orion-crypto"; | |
188 | reg = <0x30000 0x10000>, | |
189 | <0xf5000000 0x800>; | |
190 | reg-names = "regs", "sram"; | |
191 | interrupts = <22>; | |
1611f872 | 192 | clocks = <&gate_clk 17>; |
f37fbd36 AL |
193 | status = "okay"; |
194 | }; | |
163f2cea JC |
195 | }; |
196 | }; |