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804a5dd6 JE |
1 | /* |
2 | * Common base for NXP LPC18xx and LPC43xx devices. | |
3 | * | |
4 | * Copyright 2015 Joachim Eastwood <manabian@gmail.com> | |
5 | * | |
6 | * This code is released using a dual license strategy: BSD/GPL | |
7 | * You can choose the licence that better fits your requirements. | |
8 | * | |
9 | * Released under the terms of 3-clause BSD License | |
10 | * Released under the terms of GNU General Public License Version 2.0 | |
11 | * | |
12 | */ | |
13 | ||
14 | #include "armv7-m.dtsi" | |
15 | ||
ba2db535 JE |
16 | #include "dt-bindings/clock/lpc18xx-cgu.h" |
17 | #include "dt-bindings/clock/lpc18xx-ccu.h" | |
18 | ||
7836dce4 JE |
19 | #define LPC_PIN(port, pin) (0x##port * 32 + pin) |
20 | #define LPC_GPIO(port, pin) (port * 32 + pin) | |
21 | ||
804a5dd6 JE |
22 | / { |
23 | cpus { | |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
26 | ||
27 | cpu@0 { | |
28 | compatible = "arm,cortex-m3"; | |
29 | device_type = "cpu"; | |
30 | reg = <0x0>; | |
ba2db535 | 31 | clocks = <&ccu1 CLK_CPU_CORE>; |
804a5dd6 JE |
32 | }; |
33 | }; | |
34 | ||
35 | clocks { | |
36 | xtal: xtal { | |
37 | compatible = "fixed-clock"; | |
38 | #clock-cells = <0>; | |
39 | clock-frequency = <12000000>; | |
40 | }; | |
41 | ||
ba2db535 JE |
42 | xtal32: xtal32 { |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <32768>; | |
46 | }; | |
47 | ||
48 | enet_rx_clk: enet_rx_clk { | |
49 | compatible = "fixed-clock"; | |
50 | #clock-cells = <0>; | |
51 | clock-frequency = <0>; | |
52 | clock-output-names = "enet_rx_clk"; | |
53 | }; | |
54 | ||
55 | enet_tx_clk: enet_tx_clk { | |
56 | compatible = "fixed-clock"; | |
57 | #clock-cells = <0>; | |
58 | clock-frequency = <0>; | |
59 | clock-output-names = "enet_tx_clk"; | |
60 | }; | |
61 | ||
62 | gp_clkin: gp_clkin { | |
63 | compatible = "fixed-clock"; | |
804a5dd6 | 64 | #clock-cells = <0>; |
ba2db535 JE |
65 | clock-frequency = <0>; |
66 | clock-output-names = "gp_clkin"; | |
804a5dd6 JE |
67 | }; |
68 | }; | |
69 | ||
70 | soc { | |
b8da65d1 AA |
71 | sct_pwm: pwm@40000000 { |
72 | compatible = "nxp,lpc1850-sct-pwm"; | |
73 | reg = <0x40000000 0x1000>; | |
74 | clocks =<&ccu1 CLK_CPU_SCT>; | |
75 | clock-names = "pwm"; | |
76 | resets = <&rgu 37>; | |
77 | #pwm-cells = <3>; | |
78 | status = "disabled"; | |
79 | }; | |
80 | ||
5924007c JE |
81 | dmac: dma-controller@40002000 { |
82 | compatible = "arm,pl080", "arm,primecell"; | |
83 | arm,primecell-periphid = <0x00041080>; | |
84 | reg = <0x40002000 0x1000>; | |
85 | interrupts = <2>; | |
86 | clocks = <&ccu1 CLK_CPU_DMA>; | |
87 | clock-names = "apb_pclk"; | |
88 | resets = <&rgu 19>; | |
89 | #dma-cells = <2>; | |
90 | dma-channels = <8>; | |
91 | dma-requests = <16>; | |
92 | lli-bus-interface-ahb1; | |
93 | lli-bus-interface-ahb2; | |
94 | mem-bus-interface-ahb1; | |
95 | mem-bus-interface-ahb2; | |
96 | memcpy-burst-size = <256>; | |
97 | memcpy-bus-width = <32>; | |
98 | }; | |
99 | ||
4f85dd16 JE |
100 | spifi: flash-controller@40003000 { |
101 | compatible = "nxp,lpc1773-spifi"; | |
102 | reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; | |
103 | reg-names = "spifi", "flash"; | |
104 | interrupts = <30>; | |
105 | clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; | |
106 | clock-names = "spifi", "reg"; | |
107 | resets = <&rgu 53>; | |
108 | status = "disabled"; | |
109 | }; | |
110 | ||
cd07154f JE |
111 | mmcsd: mmcsd@40004000 { |
112 | compatible = "snps,dw-mshc"; | |
113 | reg = <0x40004000 0x1000>; | |
114 | interrupts = <6>; | |
115 | num-slots = <1>; | |
116 | clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; | |
117 | clock-names = "ciu", "biu"; | |
2300830f | 118 | resets = <&rgu 20>; |
cd07154f JE |
119 | status = "disabled"; |
120 | }; | |
121 | ||
b06cdb79 JE |
122 | usb0: ehci@40006100 { |
123 | compatible = "nxp,lpc1850-ehci", "generic-ehci"; | |
124 | reg = <0x40006100 0x100>; | |
125 | interrupts = <8>; | |
126 | clocks = <&ccu1 CLK_CPU_USB0>; | |
2300830f | 127 | resets = <&rgu 17>; |
6d6d6b55 JE |
128 | phys = <&usb0_otg_phy>; |
129 | phy-names = "usb"; | |
b06cdb79 JE |
130 | has-transaction-translator; |
131 | status = "disabled"; | |
132 | }; | |
133 | ||
134 | usb1: ehci@40007100 { | |
135 | compatible = "nxp,lpc1850-ehci", "generic-ehci"; | |
136 | reg = <0x40007100 0x100>; | |
137 | interrupts = <9>; | |
138 | clocks = <&ccu1 CLK_CPU_USB1>; | |
2300830f | 139 | resets = <&rgu 18>; |
b06cdb79 JE |
140 | status = "disabled"; |
141 | }; | |
142 | ||
50016385 JE |
143 | emc: memory-controller@40005000 { |
144 | compatible = "arm,pl172", "arm,primecell"; | |
145 | reg = <0x40005000 0x1000>; | |
146 | clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; | |
147 | clock-names = "mpmcclk", "apb_pclk"; | |
2300830f | 148 | resets = <&rgu 21>; |
50016385 JE |
149 | #address-cells = <2>; |
150 | #size-cells = <1>; | |
151 | ranges = <0 0 0x1c000000 0x1000000 | |
152 | 1 0 0x1d000000 0x1000000 | |
153 | 2 0 0x1e000000 0x1000000 | |
154 | 3 0 0x1f000000 0x1000000>; | |
155 | status = "disabled"; | |
156 | }; | |
157 | ||
9cf6267d JE |
158 | lcdc: lcd-controller@40008000 { |
159 | compatible = "arm,pl111", "arm,primecell"; | |
160 | reg = <0x40008000 0x1000>; | |
161 | interrupts = <7>; | |
162 | interrupt-names = "combined"; | |
163 | clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; | |
164 | clock-names = "clcdclk", "apb_pclk"; | |
2300830f | 165 | resets = <&rgu 16>; |
9cf6267d JE |
166 | status = "disabled"; |
167 | }; | |
168 | ||
5c36aa6f AA |
169 | eeprom: eeprom@4000e000 { |
170 | compatible = "nxp,lpc1857-eeprom"; | |
171 | reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; | |
172 | reg-names = "reg", "mem"; | |
173 | clocks = <&ccu1 CLK_CPU_EEPROM>; | |
174 | clock-names = "eeprom"; | |
175 | resets = <&rgu 27>; | |
176 | interrupts = <4>; | |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
fe968589 JE |
180 | mac: ethernet@40010000 { |
181 | compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; | |
182 | reg = <0x40010000 0x2000>; | |
183 | interrupts = <5>; | |
184 | interrupt-names = "macirq"; | |
185 | clocks = <&ccu1 CLK_CPU_ETHERNET>; | |
186 | clock-names = "stmmaceth"; | |
2300830f JE |
187 | resets = <&rgu 22>; |
188 | reset-names = "stmmaceth"; | |
fe968589 JE |
189 | status = "disabled"; |
190 | }; | |
191 | ||
16df2b86 JE |
192 | creg: syscon@40043000 { |
193 | compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; | |
194 | reg = <0x40043000 0x1000>; | |
195 | clocks = <&ccu1 CLK_CPU_CREG>; | |
2300830f | 196 | resets = <&rgu 5>; |
6d6d6b55 | 197 | |
52d7c426 JE |
198 | creg_clk: clock-controller { |
199 | compatible = "nxp,lpc1850-creg-clk"; | |
200 | clocks = <&xtal32>; | |
201 | #clock-cells = <1>; | |
202 | }; | |
203 | ||
472a5a3d | 204 | usb0_otg_phy: phy { |
6d6d6b55 JE |
205 | compatible = "nxp,lpc1850-usb-otg-phy"; |
206 | clocks = <&ccu1 CLK_USB0>; | |
207 | #phy-cells = <0>; | |
208 | }; | |
5913f559 | 209 | |
472a5a3d | 210 | dmamux: dma-mux { |
5913f559 JE |
211 | compatible = "nxp,lpc1850-dmamux"; |
212 | #dma-cells = <3>; | |
213 | dma-requests = <64>; | |
214 | dma-masters = <&dmac>; | |
215 | }; | |
16df2b86 JE |
216 | }; |
217 | ||
246fee6c JE |
218 | rtc: rtc@40046000 { |
219 | compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; | |
220 | reg = <0x40046000 0x1000>; | |
221 | interrupts = <47>; | |
222 | clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; | |
223 | clock-names = "rtc", "reg"; | |
224 | }; | |
225 | ||
ba2db535 JE |
226 | cgu: clock-controller@40050000 { |
227 | compatible = "nxp,lpc1850-cgu"; | |
228 | reg = <0x40050000 0x1000>; | |
229 | #clock-cells = <1>; | |
52d7c426 | 230 | clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; |
ba2db535 JE |
231 | }; |
232 | ||
233 | ccu1: clock-controller@40051000 { | |
234 | compatible = "nxp,lpc1850-ccu"; | |
235 | reg = <0x40051000 0x1000>; | |
236 | #clock-cells = <1>; | |
237 | clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, | |
238 | <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, | |
239 | <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, | |
240 | <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; | |
241 | clock-names = "base_apb3_clk", "base_apb1_clk", | |
242 | "base_spifi_clk", "base_cpu_clk", | |
243 | "base_periph_clk", "base_usb0_clk", | |
244 | "base_usb1_clk", "base_spi_clk"; | |
245 | }; | |
246 | ||
247 | ccu2: clock-controller@40052000 { | |
248 | compatible = "nxp,lpc1850-ccu"; | |
249 | reg = <0x40052000 0x1000>; | |
250 | #clock-cells = <1>; | |
251 | clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, | |
252 | <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, | |
253 | <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, | |
254 | <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; | |
255 | clock-names = "base_audio_clk", "base_uart3_clk", | |
256 | "base_uart2_clk", "base_uart1_clk", | |
257 | "base_uart0_clk", "base_ssp1_clk", | |
258 | "base_ssp0_clk", "base_sdio_clk"; | |
259 | }; | |
260 | ||
0745c702 JE |
261 | rgu: reset-controller@40053000 { |
262 | compatible = "nxp,lpc1850-rgu"; | |
263 | reg = <0x40053000 0x1000>; | |
264 | clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; | |
265 | clock-names = "delay", "reg"; | |
266 | #reset-cells = <1>; | |
267 | }; | |
268 | ||
9c8a5cdc AA |
269 | watchdog@40080000 { |
270 | compatible = "nxp,lpc1850-wwdt"; | |
271 | reg = <0x40080000 0x24>; | |
272 | interrupts = <49>; | |
273 | clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; | |
274 | clock-names = "wdtclk", "reg"; | |
275 | }; | |
276 | ||
804a5dd6 | 277 | uart0: serial@40081000 { |
f2b1c507 | 278 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
279 | reg = <0x40081000 0x1000>; |
280 | reg-shift = <2>; | |
281 | interrupts = <24>; | |
ba2db535 | 282 | clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; |
f2b1c507 | 283 | clock-names = "uartclk", "reg"; |
2300830f | 284 | resets = <&rgu 44>; |
4e9c5aa8 JE |
285 | dmas = <&dmamux 1 1 2 |
286 | &dmamux 2 1 2 | |
287 | &dmamux 11 2 2 | |
288 | &dmamux 12 2 2>; | |
289 | dma-names = "tx", "rx", "tx", "rx"; | |
804a5dd6 JE |
290 | status = "disabled"; |
291 | }; | |
292 | ||
293 | uart1: serial@40082000 { | |
f2b1c507 | 294 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
295 | reg = <0x40082000 0x1000>; |
296 | reg-shift = <2>; | |
297 | interrupts = <25>; | |
ba2db535 | 298 | clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; |
f2b1c507 | 299 | clock-names = "uartclk", "reg"; |
2300830f | 300 | resets = <&rgu 45>; |
4e9c5aa8 JE |
301 | dmas = <&dmamux 3 1 2 |
302 | &dmamux 4 1 2>; | |
303 | dma-names = "tx", "rx"; | |
804a5dd6 JE |
304 | status = "disabled"; |
305 | }; | |
306 | ||
5d2ea79c JE |
307 | ssp0: spi@40083000 { |
308 | compatible = "arm,pl022", "arm,primecell"; | |
309 | reg = <0x40083000 0x1000>; | |
310 | interrupts = <22>; | |
311 | clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; | |
312 | clock-names = "sspclk", "apb_pclk"; | |
2300830f | 313 | resets = <&rgu 50>; |
c5288091 JE |
314 | dmas = <&dmamux 9 0 2 |
315 | &dmamux 10 0 2>; | |
316 | dma-names = "rx", "tx"; | |
5d2ea79c JE |
317 | #address-cells = <1>; |
318 | #size-cells = <0>; | |
319 | status = "disabled"; | |
320 | }; | |
321 | ||
804a5dd6 JE |
322 | timer0: timer@40084000 { |
323 | compatible = "nxp,lpc3220-timer"; | |
324 | reg = <0x40084000 0x1000>; | |
325 | interrupts = <12>; | |
ba2db535 | 326 | clocks = <&ccu1 CLK_CPU_TIMER0>; |
804a5dd6 | 327 | clock-names = "timerclk"; |
2300830f | 328 | resets = <&rgu 32>; |
804a5dd6 JE |
329 | }; |
330 | ||
331 | timer1: timer@40085000 { | |
332 | compatible = "nxp,lpc3220-timer"; | |
333 | reg = <0x40085000 0x1000>; | |
334 | interrupts = <13>; | |
ba2db535 | 335 | clocks = <&ccu1 CLK_CPU_TIMER1>; |
804a5dd6 | 336 | clock-names = "timerclk"; |
2300830f | 337 | resets = <&rgu 33>; |
804a5dd6 JE |
338 | }; |
339 | ||
d881f5e2 JE |
340 | pinctrl: pinctrl@40086000 { |
341 | compatible = "nxp,lpc1850-scu"; | |
342 | reg = <0x40086000 0x1000>; | |
343 | clocks = <&ccu1 CLK_CPU_SCU>; | |
344 | }; | |
345 | ||
06713a94 JE |
346 | i2c0: i2c@400a1000 { |
347 | compatible = "nxp,lpc1788-i2c"; | |
348 | reg = <0x400a1000 0x1000>; | |
349 | interrupts = <18>; | |
350 | clocks = <&ccu1 CLK_APB1_I2C0>; | |
351 | resets = <&rgu 48>; | |
352 | #address-cells = <1>; | |
353 | #size-cells = <0>; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
7e6c8376 JE |
357 | can1: can@400a4000 { |
358 | compatible = "bosch,c_can"; | |
359 | reg = <0x400a4000 0x1000>; | |
360 | interrupts = <43>; | |
361 | clocks = <&ccu1 CLK_APB1_CAN1>; | |
2300830f | 362 | resets = <&rgu 54>; |
7e6c8376 JE |
363 | status = "disabled"; |
364 | }; | |
365 | ||
804a5dd6 | 366 | uart2: serial@400c1000 { |
f2b1c507 | 367 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
368 | reg = <0x400c1000 0x1000>; |
369 | reg-shift = <2>; | |
370 | interrupts = <26>; | |
ba2db535 | 371 | clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; |
f2b1c507 | 372 | clock-names = "uartclk", "reg"; |
2300830f | 373 | resets = <&rgu 46>; |
4e9c5aa8 JE |
374 | dmas = <&dmamux 5 1 2 |
375 | &dmamux 6 1 2>; | |
376 | dma-names = "tx", "rx"; | |
804a5dd6 JE |
377 | status = "disabled"; |
378 | }; | |
379 | ||
380 | uart3: serial@400c2000 { | |
f2b1c507 | 381 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
382 | reg = <0x400c2000 0x1000>; |
383 | reg-shift = <2>; | |
384 | interrupts = <27>; | |
ba2db535 | 385 | clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; |
f2b1c507 | 386 | clock-names = "uartclk", "reg"; |
2300830f | 387 | resets = <&rgu 47>; |
4e9c5aa8 JE |
388 | dmas = <&dmamux 7 1 2 |
389 | &dmamux 8 1 2 | |
390 | &dmamux 13 3 2 | |
391 | &dmamux 14 3 2>; | |
392 | dma-names = "tx", "rx", "rx", "tx"; | |
804a5dd6 JE |
393 | status = "disabled"; |
394 | }; | |
395 | ||
396 | timer2: timer@400c3000 { | |
397 | compatible = "nxp,lpc3220-timer"; | |
398 | reg = <0x400c3000 0x1000>; | |
399 | interrupts = <14>; | |
ba2db535 | 400 | clocks = <&ccu1 CLK_CPU_TIMER2>; |
804a5dd6 | 401 | clock-names = "timerclk"; |
2300830f | 402 | resets = <&rgu 34>; |
804a5dd6 JE |
403 | }; |
404 | ||
405 | timer3: timer@400c4000 { | |
406 | compatible = "nxp,lpc3220-timer"; | |
407 | reg = <0x400c4000 0x1000>; | |
408 | interrupts = <15>; | |
ba2db535 | 409 | clocks = <&ccu1 CLK_CPU_TIMER3>; |
804a5dd6 | 410 | clock-names = "timerclk"; |
2300830f | 411 | resets = <&rgu 35>; |
804a5dd6 | 412 | }; |
7836dce4 | 413 | |
5d2ea79c JE |
414 | ssp1: spi@400c5000 { |
415 | compatible = "arm,pl022", "arm,primecell"; | |
416 | reg = <0x400c5000 0x1000>; | |
417 | interrupts = <23>; | |
418 | clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; | |
419 | clock-names = "sspclk", "apb_pclk"; | |
2300830f | 420 | resets = <&rgu 51>; |
c5288091 JE |
421 | dmas = <&dmamux 11 2 2 |
422 | &dmamux 12 2 2 | |
423 | &dmamux 3 3 2 | |
424 | &dmamux 4 3 2 | |
425 | &dmamux 5 2 2 | |
426 | &dmamux 6 2 2 | |
427 | &dmamux 13 2 2 | |
428 | &dmamux 14 2 2>; | |
429 | dma-names = "rx", "tx", "tx", "rx", | |
430 | "tx", "rx", "rx", "tx"; | |
5d2ea79c JE |
431 | #address-cells = <1>; |
432 | #size-cells = <0>; | |
433 | status = "disabled"; | |
434 | }; | |
435 | ||
06713a94 JE |
436 | i2c1: i2c@400e0000 { |
437 | compatible = "nxp,lpc1788-i2c"; | |
438 | reg = <0x400e0000 0x1000>; | |
439 | interrupts = <19>; | |
440 | clocks = <&ccu1 CLK_APB3_I2C1>; | |
441 | resets = <&rgu 49>; | |
442 | #address-cells = <1>; | |
443 | #size-cells = <0>; | |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
8c938004 JE |
447 | dac: dac@400e1000 { |
448 | compatible = "nxp,lpc1850-dac"; | |
449 | reg = <0x400e1000 0x1000>; | |
450 | interrupts = <0>; | |
451 | clocks = <&ccu1 CLK_APB3_DAC>; | |
452 | resets = <&rgu 42>; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
7e6c8376 JE |
456 | can0: can@400e2000 { |
457 | compatible = "bosch,c_can"; | |
458 | reg = <0x400e2000 0x1000>; | |
459 | interrupts = <51>; | |
460 | clocks = <&ccu1 CLK_APB3_CAN0>; | |
2300830f | 461 | resets = <&rgu 55>; |
7e6c8376 JE |
462 | status = "disabled"; |
463 | }; | |
464 | ||
e162f9c2 JE |
465 | adc0: adc@400e3000 { |
466 | compatible = "nxp,lpc1850-adc"; | |
467 | reg = <0x400e3000 0x1000>; | |
468 | interrupts = <17>; | |
469 | clocks = <&ccu1 CLK_APB3_ADC0>; | |
470 | resets = <&rgu 40>; | |
471 | status = "disabled"; | |
472 | }; | |
473 | ||
474 | adc1: adc@400e4000 { | |
475 | compatible = "nxp,lpc1850-adc"; | |
476 | reg = <0x400e4000 0x1000>; | |
477 | interrupts = <21>; | |
478 | clocks = <&ccu1 CLK_APB3_ADC1>; | |
479 | resets = <&rgu 41>; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
7836dce4 JE |
483 | gpio: gpio@400f4000 { |
484 | compatible = "nxp,lpc1850-gpio"; | |
485 | reg = <0x400f4000 0x4000>; | |
486 | clocks = <&ccu1 CLK_CPU_GPIO>; | |
487 | gpio-controller; | |
488 | #gpio-cells = <2>; | |
489 | gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, | |
490 | <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, | |
491 | <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, | |
492 | <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, | |
493 | <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, | |
494 | <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, | |
495 | <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, | |
496 | <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, | |
497 | <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, | |
498 | <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, | |
499 | <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, | |
500 | <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, | |
501 | <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, | |
502 | <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, | |
503 | <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, | |
504 | <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, | |
505 | <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, | |
506 | <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, | |
507 | <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, | |
508 | <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, | |
509 | <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, | |
510 | <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, | |
511 | <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, | |
512 | <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, | |
513 | <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, | |
514 | <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, | |
515 | <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, | |
516 | <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, | |
517 | <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, | |
518 | <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, | |
519 | <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, | |
520 | <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, | |
521 | <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, | |
522 | <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, | |
523 | <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, | |
524 | <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, | |
525 | <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, | |
526 | <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, | |
527 | <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, | |
528 | <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; | |
529 | }; | |
804a5dd6 JE |
530 | }; |
531 | }; |