[deliverable/linux.git] / arch / arm / boot / dts / lpc18xx.dtsi

/*
 * Common base for NXP LPC18xx and LPC43xx devices.
 *
 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
 *
 * This code is released using a dual license strategy: BSD/GPL
 * You can choose the licence that better fits your requirements.
 *
 * Released under the terms of 3-clause BSD License
 * Released under the terms of GNU General Public License Version 2.0
 *
 */

#include "armv7-m.dtsi"

#include "dt-bindings/clock/lpc18xx-cgu.h"
#include "dt-bindings/clock/lpc18xx-ccu.h"

#define LPC_PIN(port, pin)	(0x##port * 32 + pin)
#define LPC_GPIO(port, pin)	(port * 32 + pin)

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-m3";
			device_type = "cpu";
			reg = <0x0>;
			clocks = <&ccu1 CLK_CPU_CORE>;
		};
	};

	clocks {
		xtal: xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		xtal32: xtal32 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		enet_rx_clk: enet_rx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_rx_clk";
		};

		enet_tx_clk: enet_tx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_tx_clk";
		};

		gp_clkin: gp_clkin {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "gp_clkin";
		};
	};

	soc {
		dmac: dma-controller@40002000 {
			compatible = "arm,pl080", "arm,primecell";
			arm,primecell-periphid = <0x00041080>;
			reg = <0x40002000 0x1000>;
			interrupts = <2>;
			clocks = <&ccu1 CLK_CPU_DMA>;
			clock-names = "apb_pclk";
			resets = <&rgu 19>;
			#dma-cells = <2>;
			dma-channels = <8>;
			dma-requests = <16>;
			lli-bus-interface-ahb1;
			lli-bus-interface-ahb2;
			mem-bus-interface-ahb1;
			mem-bus-interface-ahb2;
			memcpy-burst-size = <256>;
			memcpy-bus-width = <32>;
		};

		spifi: flash-controller@40003000 {
			compatible = "nxp,lpc1773-spifi";
			reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
			reg-names = "spifi", "flash";
			interrupts = <30>;
			clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
			clock-names = "spifi", "reg";
			resets = <&rgu 53>;
			status = "disabled";
		};

		mmcsd: mmcsd@40004000 {
			compatible = "snps,dw-mshc";
			reg = <0x40004000 0x1000>;
			interrupts = <6>;
			num-slots = <1>;
			clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
			clock-names = "ciu", "biu";
			status = "disabled";
		};

		usb0: ehci@40006100 {
			compatible = "nxp,lpc1850-ehci", "generic-ehci";
			reg = <0x40006100 0x100>;
			interrupts = <8>;
			clocks = <&ccu1 CLK_CPU_USB0>;
			phys = <&usb0_otg_phy>;
			phy-names = "usb";
			has-transaction-translator;
			status = "disabled";
		};

		usb1: ehci@40007100 {
			compatible = "nxp,lpc1850-ehci", "generic-ehci";
			reg = <0x40007100 0x100>;
			interrupts = <9>;
			clocks = <&ccu1 CLK_CPU_USB1>;
			status = "disabled";
		};

		emc: memory-controller@40005000 {
			compatible = "arm,pl172", "arm,primecell";
			reg = <0x40005000 0x1000>;
			clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
			clock-names = "mpmcclk", "apb_pclk";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0 0x1c000000 0x1000000
				  1 0 0x1d000000 0x1000000
				  2 0 0x1e000000 0x1000000
				  3 0 0x1f000000 0x1000000>;
			status = "disabled";
		};

		lcdc: lcd-controller@40008000 {
			compatible = "arm,pl111", "arm,primecell";
			reg = <0x40008000 0x1000>;
			interrupts = <7>;
			interrupt-names = "combined";
			clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
			clock-names = "clcdclk", "apb_pclk";
			status = "disabled";
		};

		mac: ethernet@40010000 {
			compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
			reg = <0x40010000 0x2000>;
			interrupts = <5>;
			interrupt-names	= "macirq";
			clocks = <&ccu1 CLK_CPU_ETHERNET>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		creg: syscon@40043000 {
			compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
			reg = <0x40043000 0x1000>;
			clocks = <&ccu1 CLK_CPU_CREG>;

			usb0_otg_phy: phy@004 {
				compatible = "nxp,lpc1850-usb-otg-phy";
				clocks = <&ccu1 CLK_USB0>;
				#phy-cells = <0>;
			};

			dmamux: dma-mux@11c {
				compatible = "nxp,lpc1850-dmamux";
				#dma-cells = <3>;
				dma-requests = <64>;
				dma-masters = <&dmac>;
			};
		};

		cgu: clock-controller@40050000 {
			compatible = "nxp,lpc1850-cgu";
			reg = <0x40050000 0x1000>;
			#clock-cells = <1>;
			clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
		};

		ccu1: clock-controller@40051000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40051000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
				 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
				 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
				 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
			clock-names = "base_apb3_clk",   "base_apb1_clk",
				      "base_spifi_clk",  "base_cpu_clk",
				      "base_periph_clk", "base_usb0_clk",
				      "base_usb1_clk",   "base_spi_clk";
		};

		ccu2: clock-controller@40052000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40052000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
				 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
				 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
				 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
			clock-names = "base_audio_clk", "base_uart3_clk",
				      "base_uart2_clk", "base_uart1_clk",
				      "base_uart0_clk", "base_ssp1_clk",
				      "base_ssp0_clk",  "base_sdio_clk";
		};

		rgu: reset-controller@40053000 {
			compatible = "nxp,lpc1850-rgu";
			reg = <0x40053000 0x1000>;
			clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
			clock-names = "delay", "reg";
			#reset-cells = <1>;
		};

		uart0: serial@40081000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40081000 0x1000>;
			reg-shift = <2>;
			interrupts = <24>;
			clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
			clock-names = "uartclk", "reg";
			dmas = <&dmamux  1 1 2
				&dmamux  2 1 2
				&dmamux 11 2 2
				&dmamux 12 2 2>;
			dma-names = "tx", "rx", "tx", "rx";
			status = "disabled";
		};

		uart1: serial@40082000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40082000 0x1000>;
			reg-shift = <2>;
			interrupts = <25>;
			clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
			clock-names = "uartclk", "reg";
			dmas = <&dmamux 3 1 2
				&dmamux 4 1 2>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		ssp0: spi@40083000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x40083000 0x1000>;
			interrupts = <22>;
			clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dmamux  9 0 2
				&dmamux 10 0 2>;
			dma-names = "rx", "tx";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		timer0: timer@40084000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40084000 0x1000>;
			interrupts = <12>;
			clocks = <&ccu1 CLK_CPU_TIMER0>;
			clock-names = "timerclk";
		};

		timer1: timer@40085000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40085000 0x1000>;
			interrupts = <13>;
			clocks = <&ccu1 CLK_CPU_TIMER1>;
			clock-names = "timerclk";
		};

		pinctrl: pinctrl@40086000 {
			compatible = "nxp,lpc1850-scu";
			reg = <0x40086000 0x1000>;
			clocks = <&ccu1 CLK_CPU_SCU>;
		};

		i2c0: i2c@400a1000 {
			compatible = "nxp,lpc1788-i2c";
			reg = <0x400a1000 0x1000>;
			interrupts = <18>;
			clocks = <&ccu1 CLK_APB1_I2C0>;
			resets = <&rgu 48>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can1: can@400a4000 {
			compatible = "bosch,c_can";
			reg = <0x400a4000 0x1000>;
			interrupts = <43>;
			clocks = <&ccu1 CLK_APB1_CAN1>;
			status = "disabled";
		};

		uart2: serial@400c1000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c1000 0x1000>;
			reg-shift = <2>;
			interrupts = <26>;
			clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
			clock-names = "uartclk", "reg";
			dmas = <&dmamux 5 1 2
				&dmamux 6 1 2>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart3: serial@400c2000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c2000 0x1000>;
			reg-shift = <2>;
			interrupts = <27>;
			clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
			clock-names = "uartclk", "reg";
			dmas = <&dmamux  7 1 2
				&dmamux  8 1 2
				&dmamux 13 3 2
				&dmamux 14 3 2>;
			dma-names = "tx", "rx", "rx", "tx";
			status = "disabled";
		};

		timer2: timer@400c3000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c3000 0x1000>;
			interrupts = <14>;
			clocks = <&ccu1 CLK_CPU_TIMER2>;
			clock-names = "timerclk";
		};

		timer3: timer@400c4000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c4000 0x1000>;
			interrupts = <15>;
			clocks = <&ccu1 CLK_CPU_TIMER3>;
			clock-names = "timerclk";
		};

		ssp1: spi@400c5000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x400c5000 0x1000>;
			interrupts = <23>;
			clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dmamux 11 2 2
				&dmamux 12 2 2
				&dmamux  3 3 2
				&dmamux  4 3 2
				&dmamux  5 2 2
				&dmamux  6 2 2
				&dmamux 13 2 2
				&dmamux 14 2 2>;
			dma-names = "rx", "tx", "tx", "rx",
				    "tx", "rx", "rx", "tx";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@400e0000 {
			compatible = "nxp,lpc1788-i2c";
			reg = <0x400e0000 0x1000>;
			interrupts = <19>;
			clocks = <&ccu1 CLK_APB3_I2C1>;
			resets = <&rgu 49>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@400e2000 {
			compatible = "bosch,c_can";
			reg = <0x400e2000 0x1000>;
			interrupts = <51>;
			clocks = <&ccu1 CLK_APB3_CAN0>;
			status = "disabled";
		};

		gpio: gpio@400f4000 {
			compatible = "nxp,lpc1850-gpio";
			reg = <0x400f4000 0x4000>;
			clocks = <&ccu1 CLK_CPU_GPIO>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges =	<&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
					<&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
					<&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
					<&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
					<&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
					<&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
					<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
					<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
					<&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
					<&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
					<&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
					<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
					<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
					<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
					<&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
					<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
					<&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
					<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
					<&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
					<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
					<&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
					<&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
					<&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
					<&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
					<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
					<&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
					<&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
					<&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
					<&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
					<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
					<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
					<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
					<&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
					<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
					<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
					<&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
					<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
					<&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
					<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
					<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
		};
	};
};
Commit	Line	Data
804a5dd6 JE	1	/*
	2	* Common base for NXP LPC18xx and LPC43xx devices.
	3	*
	4	* Copyright 2015 Joachim Eastwood <manabian@gmail.com>
	5	*
	6	* This code is released using a dual license strategy: BSD/GPL
	7	* You can choose the licence that better fits your requirements.
	8	*
	9	* Released under the terms of 3-clause BSD License
	10	* Released under the terms of GNU General Public License Version 2.0
	11	*
	12	*/
	13
	14	#include "armv7-m.dtsi"
	15
ba2db535 JE	16	#include "dt-bindings/clock/lpc18xx-cgu.h"
	17	#include "dt-bindings/clock/lpc18xx-ccu.h"
	18
7836dce4 JE	19	#define LPC_PIN(port, pin) (0x##port * 32 + pin)
	20	#define LPC_GPIO(port, pin) (port * 32 + pin)
	21
804a5dd6 JE	22	/ {
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	cpu@0 {
	28	compatible = "arm,cortex-m3";
	29	device_type = "cpu";
	30	reg = <0x0>;
ba2db535	31	clocks = <&ccu1 CLK_CPU_CORE>;
804a5dd6 JE	32	};
	33	};
	34
	35	clocks {
	36	xtal: xtal {
	37	compatible = "fixed-clock";
	38	#clock-cells = <0>;
	39	clock-frequency = <12000000>;
	40	};
	41
ba2db535 JE	42	xtal32: xtal32 {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <32768>;
	46	};
	47
	48	enet_rx_clk: enet_rx_clk {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	clock-frequency = <0>;
	52	clock-output-names = "enet_rx_clk";
	53	};
	54
	55	enet_tx_clk: enet_tx_clk {
	56	compatible = "fixed-clock";
	57	#clock-cells = <0>;
	58	clock-frequency = <0>;
	59	clock-output-names = "enet_tx_clk";
	60	};
	61
	62	gp_clkin: gp_clkin {
	63	compatible = "fixed-clock";
804a5dd6	64	#clock-cells = <0>;
ba2db535 JE	65	clock-frequency = <0>;
ba2db535 JE	66	clock-output-names = "gp_clkin";
804a5dd6 JE	67	};
	68	};
	69
	70	soc {
5924007c JE	71	dmac: dma-controller@40002000 {
	72	compatible = "arm,pl080", "arm,primecell";
	73	arm,primecell-periphid = <0x00041080>;
	74	reg = <0x40002000 0x1000>;
	75	interrupts = <2>;
	76	clocks = <&ccu1 CLK_CPU_DMA>;
	77	clock-names = "apb_pclk";
	78	resets = <&rgu 19>;
	79	#dma-cells = <2>;
	80	dma-channels = <8>;
	81	dma-requests = <16>;
	82	lli-bus-interface-ahb1;
	83	lli-bus-interface-ahb2;
	84	mem-bus-interface-ahb1;
	85	mem-bus-interface-ahb2;
	86	memcpy-burst-size = <256>;
	87	memcpy-bus-width = <32>;
	88	};
	89
4f85dd16 JE	90	spifi: flash-controller@40003000 {
	91	compatible = "nxp,lpc1773-spifi";
	92	reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
	93	reg-names = "spifi", "flash";
	94	interrupts = <30>;
	95	clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
	96	clock-names = "spifi", "reg";
	97	resets = <&rgu 53>;
	98	status = "disabled";
	99	};
	100
cd07154f JE	101	mmcsd: mmcsd@40004000 {
	102	compatible = "snps,dw-mshc";
	103	reg = <0x40004000 0x1000>;
	104	interrupts = <6>;
	105	num-slots = <1>;
	106	clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
	107	clock-names = "ciu", "biu";
	108	status = "disabled";
	109	};
	110
b06cdb79 JE	111	usb0: ehci@40006100 {
	112	compatible = "nxp,lpc1850-ehci", "generic-ehci";
	113	reg = <0x40006100 0x100>;
	114	interrupts = <8>;
	115	clocks = <&ccu1 CLK_CPU_USB0>;
6d6d6b55 JE	116	phys = <&usb0_otg_phy>;
6d6d6b55 JE	117	phy-names = "usb";
b06cdb79 JE	118	has-transaction-translator;
	119	status = "disabled";
	120	};
	121
	122	usb1: ehci@40007100 {
	123	compatible = "nxp,lpc1850-ehci", "generic-ehci";
	124	reg = <0x40007100 0x100>;
	125	interrupts = <9>;
	126	clocks = <&ccu1 CLK_CPU_USB1>;
	127	status = "disabled";
	128	};
	129
50016385 JE	130	emc: memory-controller@40005000 {
	131	compatible = "arm,pl172", "arm,primecell";
	132	reg = <0x40005000 0x1000>;
	133	clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
	134	clock-names = "mpmcclk", "apb_pclk";
	135	#address-cells = <2>;
	136	#size-cells = <1>;
	137	ranges = <0 0 0x1c000000 0x1000000
	138	1 0 0x1d000000 0x1000000
	139	2 0 0x1e000000 0x1000000
	140	3 0 0x1f000000 0x1000000>;
	141	status = "disabled";
	142	};
	143
9cf6267d JE	144	lcdc: lcd-controller@40008000 {
	145	compatible = "arm,pl111", "arm,primecell";
	146	reg = <0x40008000 0x1000>;
	147	interrupts = <7>;
	148	interrupt-names = "combined";
	149	clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
	150	clock-names = "clcdclk", "apb_pclk";
	151	status = "disabled";
	152	};
	153
fe968589 JE	154	mac: ethernet@40010000 {
	155	compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
	156	reg = <0x40010000 0x2000>;
	157	interrupts = <5>;
	158	interrupt-names = "macirq";
	159	clocks = <&ccu1 CLK_CPU_ETHERNET>;
	160	clock-names = "stmmaceth";
	161	status = "disabled";
	162	};
	163
16df2b86 JE	164	creg: syscon@40043000 {
	165	compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
	166	reg = <0x40043000 0x1000>;
	167	clocks = <&ccu1 CLK_CPU_CREG>;
6d6d6b55 JE	168
	169	usb0_otg_phy: phy@004 {
	170	compatible = "nxp,lpc1850-usb-otg-phy";
	171	clocks = <&ccu1 CLK_USB0>;
	172	#phy-cells = <0>;
	173	};
5913f559 JE	174
	175	dmamux: dma-mux@11c {
	176	compatible = "nxp,lpc1850-dmamux";
	177	#dma-cells = <3>;
	178	dma-requests = <64>;
	179	dma-masters = <&dmac>;
	180	};
16df2b86 JE	181	};
16df2b86 JE	182
ba2db535 JE	183	cgu: clock-controller@40050000 {
	184	compatible = "nxp,lpc1850-cgu";
	185	reg = <0x40050000 0x1000>;
	186	#clock-cells = <1>;
	187	clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
	188	};
	189
	190	ccu1: clock-controller@40051000 {
	191	compatible = "nxp,lpc1850-ccu";
	192	reg = <0x40051000 0x1000>;
	193	#clock-cells = <1>;
	194	clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
	195	<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
	196	<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
	197	<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
	198	clock-names = "base_apb3_clk", "base_apb1_clk",
	199	"base_spifi_clk", "base_cpu_clk",
	200	"base_periph_clk", "base_usb0_clk",
	201	"base_usb1_clk", "base_spi_clk";
	202	};
	203
	204	ccu2: clock-controller@40052000 {
	205	compatible = "nxp,lpc1850-ccu";
	206	reg = <0x40052000 0x1000>;
	207	#clock-cells = <1>;
	208	clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
	209	<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
	210	<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
	211	<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
	212	clock-names = "base_audio_clk", "base_uart3_clk",
	213	"base_uart2_clk", "base_uart1_clk",
	214	"base_uart0_clk", "base_ssp1_clk",
	215	"base_ssp0_clk", "base_sdio_clk";
	216	};
	217
0745c702 JE	218	rgu: reset-controller@40053000 {
	219	compatible = "nxp,lpc1850-rgu";
	220	reg = <0x40053000 0x1000>;
	221	clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
	222	clock-names = "delay", "reg";
	223	#reset-cells = <1>;
	224	};
	225
804a5dd6	226	uart0: serial@40081000 {
f2b1c507	227	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	228	reg = <0x40081000 0x1000>;
	229	reg-shift = <2>;
	230	interrupts = <24>;
ba2db535	231	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
f2b1c507	232	clock-names = "uartclk", "reg";
4e9c5aa8 JE	233	dmas = <&dmamux 1 1 2
	234	&dmamux 2 1 2
	235	&dmamux 11 2 2
	236	&dmamux 12 2 2>;
	237	dma-names = "tx", "rx", "tx", "rx";
804a5dd6 JE	238	status = "disabled";
	239	};
	240
	241	uart1: serial@40082000 {
f2b1c507	242	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	243	reg = <0x40082000 0x1000>;
	244	reg-shift = <2>;
	245	interrupts = <25>;
ba2db535	246	clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
f2b1c507	247	clock-names = "uartclk", "reg";
4e9c5aa8 JE	248	dmas = <&dmamux 3 1 2
	249	&dmamux 4 1 2>;
	250	dma-names = "tx", "rx";
804a5dd6 JE	251	status = "disabled";
	252	};
	253
5d2ea79c JE	254	ssp0: spi@40083000 {
	255	compatible = "arm,pl022", "arm,primecell";
	256	reg = <0x40083000 0x1000>;
	257	interrupts = <22>;
	258	clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
	259	clock-names = "sspclk", "apb_pclk";
c5288091 JE	260	dmas = <&dmamux 9 0 2
	261	&dmamux 10 0 2>;
	262	dma-names = "rx", "tx";
5d2ea79c JE	263	#address-cells = <1>;
	264	#size-cells = <0>;
	265	status = "disabled";
	266	};
	267
804a5dd6 JE	268	timer0: timer@40084000 {
	269	compatible = "nxp,lpc3220-timer";
	270	reg = <0x40084000 0x1000>;
	271	interrupts = <12>;
ba2db535	272	clocks = <&ccu1 CLK_CPU_TIMER0>;
804a5dd6 JE	273	clock-names = "timerclk";
	274	};
	275
	276	timer1: timer@40085000 {
	277	compatible = "nxp,lpc3220-timer";
	278	reg = <0x40085000 0x1000>;
	279	interrupts = <13>;
ba2db535	280	clocks = <&ccu1 CLK_CPU_TIMER1>;
804a5dd6 JE	281	clock-names = "timerclk";
	282	};
	283
d881f5e2 JE	284	pinctrl: pinctrl@40086000 {
	285	compatible = "nxp,lpc1850-scu";
	286	reg = <0x40086000 0x1000>;
	287	clocks = <&ccu1 CLK_CPU_SCU>;
	288	};
	289
06713a94 JE	290	i2c0: i2c@400a1000 {
	291	compatible = "nxp,lpc1788-i2c";
	292	reg = <0x400a1000 0x1000>;
	293	interrupts = <18>;
	294	clocks = <&ccu1 CLK_APB1_I2C0>;
	295	resets = <&rgu 48>;
	296	#address-cells = <1>;
	297	#size-cells = <0>;
	298	status = "disabled";
	299	};
	300
7e6c8376 JE	301	can1: can@400a4000 {
	302	compatible = "bosch,c_can";
	303	reg = <0x400a4000 0x1000>;
	304	interrupts = <43>;
	305	clocks = <&ccu1 CLK_APB1_CAN1>;
	306	status = "disabled";
	307	};
	308
804a5dd6	309	uart2: serial@400c1000 {
f2b1c507	310	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	311	reg = <0x400c1000 0x1000>;
	312	reg-shift = <2>;
	313	interrupts = <26>;
ba2db535	314	clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
f2b1c507	315	clock-names = "uartclk", "reg";
4e9c5aa8 JE	316	dmas = <&dmamux 5 1 2
	317	&dmamux 6 1 2>;
	318	dma-names = "tx", "rx";
804a5dd6 JE	319	status = "disabled";
	320	};
	321
	322	uart3: serial@400c2000 {
f2b1c507	323	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	324	reg = <0x400c2000 0x1000>;
	325	reg-shift = <2>;
	326	interrupts = <27>;
ba2db535	327	clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
f2b1c507	328	clock-names = "uartclk", "reg";
4e9c5aa8 JE	329	dmas = <&dmamux 7 1 2
	330	&dmamux 8 1 2
	331	&dmamux 13 3 2
	332	&dmamux 14 3 2>;
	333	dma-names = "tx", "rx", "rx", "tx";
804a5dd6 JE	334	status = "disabled";
	335	};
	336
	337	timer2: timer@400c3000 {
	338	compatible = "nxp,lpc3220-timer";
	339	reg = <0x400c3000 0x1000>;
	340	interrupts = <14>;
ba2db535	341	clocks = <&ccu1 CLK_CPU_TIMER2>;
804a5dd6 JE	342	clock-names = "timerclk";
	343	};
	344
	345	timer3: timer@400c4000 {
	346	compatible = "nxp,lpc3220-timer";
	347	reg = <0x400c4000 0x1000>;
	348	interrupts = <15>;
ba2db535	349	clocks = <&ccu1 CLK_CPU_TIMER3>;
804a5dd6 JE	350	clock-names = "timerclk";
804a5dd6 JE	351	};
7836dce4	352
5d2ea79c JE	353	ssp1: spi@400c5000 {
	354	compatible = "arm,pl022", "arm,primecell";
	355	reg = <0x400c5000 0x1000>;
	356	interrupts = <23>;
	357	clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
	358	clock-names = "sspclk", "apb_pclk";
c5288091 JE	359	dmas = <&dmamux 11 2 2
	360	&dmamux 12 2 2
	361	&dmamux 3 3 2
	362	&dmamux 4 3 2
	363	&dmamux 5 2 2
	364	&dmamux 6 2 2
	365	&dmamux 13 2 2
	366	&dmamux 14 2 2>;
	367	dma-names = "rx", "tx", "tx", "rx",
	368	"tx", "rx", "rx", "tx";
5d2ea79c JE	369	#address-cells = <1>;
	370	#size-cells = <0>;
	371	status = "disabled";
	372	};
	373
06713a94 JE	374	i2c1: i2c@400e0000 {
	375	compatible = "nxp,lpc1788-i2c";
	376	reg = <0x400e0000 0x1000>;
	377	interrupts = <19>;
	378	clocks = <&ccu1 CLK_APB3_I2C1>;
	379	resets = <&rgu 49>;
	380	#address-cells = <1>;
	381	#size-cells = <0>;
	382	status = "disabled";
	383	};
	384
7e6c8376 JE	385	can0: can@400e2000 {
	386	compatible = "bosch,c_can";
	387	reg = <0x400e2000 0x1000>;
	388	interrupts = <51>;
	389	clocks = <&ccu1 CLK_APB3_CAN0>;
	390	status = "disabled";
	391	};
	392
7836dce4 JE	393	gpio: gpio@400f4000 {
	394	compatible = "nxp,lpc1850-gpio";
	395	reg = <0x400f4000 0x4000>;
	396	clocks = <&ccu1 CLK_CPU_GPIO>;
	397	gpio-controller;
	398	#gpio-cells = <2>;
	399	gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
	400	<&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
	401	<&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
	402	<&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
	403	<&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
	404	<&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
	405	<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
	406	<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
	407	<&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
	408	<&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
	409	<&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
	410	<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
	411	<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
	412	<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
	413	<&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
	414	<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
	415	<&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
	416	<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
	417	<&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
	418	<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
	419	<&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
	420	<&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
	421	<&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
	422	<&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
	423	<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
	424	<&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
	425	<&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
	426	<&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
	427	<&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
	428	<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
	429	<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
	430	<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
	431	<&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
	432	<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
	433	<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
	434	<&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
	435	<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
	436	<&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
	437	<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
	438	<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
	439	};
804a5dd6 JE	440	};
804a5dd6 JE	441	};